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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -mtriple=mips -mcpu=mips32r2 -stop-before=finalize-isel < %s | FileCheck %s --check-prefix=MIPS3; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+micromips -stop-before=finalize-isel < %s | FileCheck %s --check-prefix=MICROMIPS4 5; Test that the correct ISA version of the unaligned memory operations is6; selected up front.7 8define void @g2(ptr %a, ptr %b) {9 ; MIPS-LABEL: name: g210 ; MIPS: bb.0.entry:11 ; MIPS: liveins: $a0, $a112 ; MIPS: [[COPY:%[0-9]+]]:gpr32 = COPY $a113 ; MIPS: [[COPY1:%[0-9]+]]:gpr32 = COPY $a014 ; MIPS: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF15 ; MIPS: [[LWL:%[0-9]+]]:gpr32 = LWL [[COPY1]], 0, [[DEF]] :: (load (s32) from %ir.a, align 1)16 ; MIPS: [[LWR:%[0-9]+]]:gpr32 = LWR [[COPY1]], 3, [[LWL]] :: (load (s32) from %ir.a, align 1)17 ; MIPS: SWL [[LWR]], [[COPY]], 0 :: (store (s32) into %ir.b, align 1)18 ; MIPS: SWR [[LWR]], [[COPY]], 3 :: (store (s32) into %ir.b, align 1)19 ; MIPS: RetRA20 ; MICROMIPS-LABEL: name: g221 ; MICROMIPS: bb.0.entry:22 ; MICROMIPS: liveins: $a0, $a123 ; MICROMIPS: [[COPY:%[0-9]+]]:gpr32 = COPY $a124 ; MICROMIPS: [[COPY1:%[0-9]+]]:gpr32 = COPY $a025 ; MICROMIPS: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF26 ; MICROMIPS: [[LWL_MM:%[0-9]+]]:gpr32 = LWL_MM [[COPY1]], 0, [[DEF]] :: (load (s32) from %ir.a, align 1)27 ; MICROMIPS: [[LWR_MM:%[0-9]+]]:gpr32 = LWR_MM [[COPY1]], 3, [[LWL_MM]] :: (load (s32) from %ir.a, align 1)28 ; MICROMIPS: SWL_MM [[LWR_MM]], [[COPY]], 0 :: (store (s32) into %ir.b, align 1)29 ; MICROMIPS: SWR_MM [[LWR_MM]], [[COPY]], 3 :: (store (s32) into %ir.b, align 1)30 ; MICROMIPS: RetRA31entry:32 %0 = load i32, ptr %a, align 133 store i32 %0, ptr %b, align 134 ret void35}36