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1; RUN: llc < %s -mtriple=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-CMOV2; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-CMOV3; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32R64; RUN: llc < %s -mtriple=mipsel -mcpu=mips4 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64-CMOV5; RUN: llc < %s -mtriple=mipsel -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64-CMOV6; RUN: llc < %s -mtriple=mipsel -mcpu=mips64r2 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64-CMOV7; RUN: llc < %s -mtriple=mipsel -mcpu=mips64r6 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64R68 9@g1 = external global i3210 11define i32 @sel_icmp_nez_i32_z0(i32 signext %s) nounwind readonly {12entry:13; ALL-LABEL: sel_icmp_nez_i32_z0:14 15; 32-CMOV: lw $2, 0(${{[0-9]+}})16; 32-CMOV: movn $2, $zero, $417 18; 32R6: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})19; 32R6: seleqz $2, $[[R0]], $420 21; 64-CMOV: lw $2, 0(${{[0-9]+}})22; 64-CMOV: movn $2, $zero, $423 24; 64R6: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})25; 64R6: seleqz $2, $[[R0]], $426 27 %tobool = icmp ne i32 %s, 028 %0 = load i32, ptr @g1, align 429 %cond = select i1 %tobool, i32 0, i32 %030 ret i32 %cond31}32 33define i32 @sel_icmp_nez_i32_z1(i32 signext %s) nounwind readonly {34entry:35; ALL-LABEL: sel_icmp_nez_i32_z1:36 37; 32-CMOV: lw $2, 0(${{[0-9]+}})38; 32-CMOV: movz $2, $zero, $439 40; 32R6: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})41; 32R6: selnez $2, $[[R0]], $442 43; 64-CMOV: lw $2, 0(${{[0-9]+}})44; 64-CMOV: movz $2, $zero, $445 46; 64R6: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})47; 64R6: selnez $2, $[[R0]], $448 49 %tobool = icmp ne i32 %s, 050 %0 = load i32, ptr @g1, align 451 %cond = select i1 %tobool, i32 %0, i32 052 ret i32 %cond53}54 55@g2 = external global i6456 57define i64 @sel_icmp_nez_i64_z0(i64 %s) nounwind readonly {58entry:59; ALL-LABEL: sel_icmp_nez_i64_z0:60 61; 32-CMOV-DAG: lw $[[R0:2]], 0(${{[0-9]+}})62; 32-CMOV-DAG: lw $[[R1:3]], 4(${{[0-9]+}})63; 32-CMOV-DAG: movn $[[R0]], $zero, $464; 32-CMOV-DAG: movn $[[R1]], $zero, $465 66; 32R6-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})67; 32R6-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})68; 32R6-DAG: or $[[CC:[0-9]+]], $4, $569; 32R6-DAG: seleqz $2, $[[R0]], $[[CC]]70; 32R6-DAG: seleqz $3, $[[R1]], $[[CC]]71 72; 64-CMOV: ld $2, 0(${{[0-9]+}})73; 64-CMOV: movn $2, $zero, $474 75; 64R6: ld $[[R0:[0-9]+]], 0(${{[0-9]+}})76; 64R6: seleqz $2, $[[R0]], $477 78 %tobool = icmp ne i64 %s, 079 %0 = load i64, ptr @g2, align 480 %cond = select i1 %tobool, i64 0, i64 %081 ret i64 %cond82}83 84define i64 @sel_icmp_nez_i64_z1(i64 %s) nounwind readonly {85entry:86; ALL-LABEL: sel_icmp_nez_i64_z1:87 88; 32-CMOV-DAG: lw $[[R0:2]], 0(${{[0-9]+}})89; 32-CMOV-DAG: lw $[[R1:3]], 4(${{[0-9]+}})90; 32-CMOV-DAG: movz $[[R0]], $zero, $491; 32-CMOV-DAG: movz $[[R1]], $zero, $492 93; 32R6-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})94; 32R6-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})95; 32R6-DAG: or $[[CC:[0-9]+]], $4, $596; 32R6-DAG: selnez $2, $[[R0]], $[[CC]]97; 32R6-DAG: selnez $3, $[[R1]], $[[CC]]98 99; 64-CMOV: ld $2, 0(${{[0-9]+}})100; 64-CMOV: movz $2, $zero, $4101 102; 64R6: ld $[[R0:[0-9]+]], 0(${{[0-9]+}})103; 64R6: selnez $2, $[[R0]], $4104 105 %tobool = icmp ne i64 %s, 0106 %0 = load i64, ptr @g2, align 4107 %cond = select i1 %tobool, i64 %0, i64 0108 ret i64 %cond109}110