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1; RUN: llc < %s -mtriple=nvptx -mcpu=sm_20 -fp-contract=fast | FileCheck %s2; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_20 -fp-contract=fast | FileCheck %s3; RUN: %if ptxas-ptr32 %{ llc < %s -mtriple=nvptx -mcpu=sm_20 -fp-contract=fast | %ptxas-verify %}4; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mcpu=sm_20 -fp-contract=fast | %ptxas-verify %}5 6;; These tests should run for all targets7 8;;===-- Basic instruction selection tests ---------------------------------===;;9 10 11;;; f6412 13define double @fadd_f64(double %a, double %b) {14; CHECK: add.f64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}}15; CHECK: ret16 %ret = fadd double %a, %b17 ret double %ret18}19 20define double @fsub_f64(double %a, double %b) {21; CHECK: sub.f64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}}22; CHECK: ret23 %ret = fsub double %a, %b24 ret double %ret25}26 27define double @fmul_f64(double %a, double %b) {28; CHECK: mul.f64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}}29; CHECK: ret30 %ret = fmul double %a, %b31 ret double %ret32}33 34define double @fdiv_f64(double %a, double %b) {35; CHECK: div.rn.f64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}}36; CHECK: ret37 %ret = fdiv double %a, %b38 ret double %ret39}40 41;; PTX does not have a floating-point rem instruction42 43 44;;; f3245 46define float @fadd_f32(float %a, float %b) {47; CHECK: add.f32 %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}48; CHECK: ret49 %ret = fadd float %a, %b50 ret float %ret51}52 53define float @fsub_f32(float %a, float %b) {54; CHECK: sub.f32 %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}55; CHECK: ret56 %ret = fsub float %a, %b57 ret float %ret58}59 60define float @fmul_f32(float %a, float %b) {61; CHECK: mul.f32 %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}62; CHECK: ret63 %ret = fmul float %a, %b64 ret float %ret65}66 67define float @fdiv_f32(float %a, float %b) {68; CHECK: div.rn.f32 %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}69; CHECK: ret70 %ret = fdiv float %a, %b71 ret float %ret72}73 74;; PTX does not have a floating-point rem instruction75