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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -o - %s -mtriple=nvptx64 -mcpu=sm_35 -run-pass=branch-folder | FileCheck %s3 4--- |5  ; ModuleID = '/mnt/nas/asavonic/work/llvm/llvm/test/CodeGen/NVPTX/branch-fold.ll'6  source_filename = "/mnt/nas/asavonic/work/llvm/llvm/test/CodeGen/NVPTX/branch-fold.ll"7  target datalayout = "e-i64:64-i128:128-v16:16-v32:32-n16:32:64"8  target triple = "nvptx64-nvidia-cuda"9 10  define ptx_kernel void @hoge() {11  bb:12    br i1 undef, label %bb1.preheader, label %bb4.preheader13 14  bb1.preheader:                                    ; preds = %bb15    br label %bb116 17  bb1:                                              ; preds = %bb1.preheader, %bb118    %lsr.iv = phi i64 [ undef, %bb1.preheader ], [ %lsr.iv.next, %bb1 ]19    %lsr.iv.next = add i64 %lsr.iv, 120    %tmp3 = icmp sle i64 %lsr.iv.next, 021    br i1 %tmp3, label %bb1, label %bb4.preheader22 23  bb4.preheader:                                    ; preds = %bb1, %bb24    br label %bb425 26  bb4:                                              ; preds = %bb4.preheader, %bb427    br label %bb428  }29 30...31---32name:            hoge33alignment:       134tracksRegLiveness: true35registers:36  - { id: 0, class: b64 }37  - { id: 1, class: b64 }38  - { id: 2, class: b1 }39  - { id: 3, class: b64 }40  - { id: 4, class: b1 }41  - { id: 5, class: b64 }42frameInfo:43  maxAlignment:    144machineFunctionInfo: {}45body:             |46  ; CHECK-LABEL: name: hoge47  ; CHECK: bb.0.bb:48  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.3(0x40000000)49  ; CHECK-NEXT: {{  $}}50  ; CHECK-NEXT:   CBranch undef %2:b1, %bb.351  ; CHECK-NEXT: {{  $}}52  ; CHECK-NEXT: bb.1.bb1.preheader:53  ; CHECK-NEXT:   successors: %bb.2(0x80000000)54  ; CHECK-NEXT: {{  $}}55  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:b64 = IMPLICIT_DEF56  ; CHECK-NEXT: {{  $}}57  ; CHECK-NEXT: bb.2.bb1:58  ; CHECK-NEXT:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)59  ; CHECK-NEXT: {{  $}}60  ; CHECK-NEXT:   [[ADDi64ri:%[0-9]+]]:b64 = ADD64ri [[ADDi64ri]], 161  ; CHECK-NEXT:   [[SETP_s64ri:%[0-9]+]]:b1 = SETP_i64ri [[ADDi64ri]], 1, 262  ; CHECK-NEXT:   CBranch [[SETP_s64ri]], %bb.263  ; CHECK-NEXT: {{  $}}64  ; CHECK-NEXT: bb.3.bb4:65  ; CHECK-NEXT:   successors: %bb.3(0x80000000)66  ; CHECK-NEXT: {{  $}}67  ; CHECK-NEXT:   GOTO %bb.368  bb.0.bb:69    successors: %bb.1, %bb.370 71    CBranch undef %2:b1, %bb.372 73  bb.1.bb1.preheader:74    %5:b64 = IMPLICIT_DEF75 76  bb.2.bb1:77    successors: %bb.2(0x7c000000), %bb.3(0x04000000)78 79    %5:b64 = ADD64ri %5, 180    %4:b1 = SETP_i64ri %5, 1, 281    CBranch %4, %bb.282 83  bb.3.bb4:84    GOTO %bb.385 86...87