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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_35 -verify-machineinstrs | FileCheck %s3; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mcpu=sm_35 | %ptxas-verify %}4 5; Verify that we correctly emit code for extending ldg/ldu. We do not expose6; extending variants in the backend, but the ldg/ldu selection code may pick7; extending loads as candidates. We do want to support this, so make sure we8; emit the necessary cvt.* instructions to implement the extension and let ptxas9; emit the real extending loads.10 11target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"12target triple = "nvptx64-nvidia-cuda"13 14define ptx_kernel void @spam(ptr addrspace(1) noalias nocapture readonly %arg, ptr addrspace(1) noalias nocapture %arg1, i64 %arg2, i64 %arg3) #0 {15; CHECK-LABEL: spam(16; CHECK: .maxntid 1, 1, 117; CHECK-NEXT: {18; CHECK-NEXT: .reg .b32 %r<2>;19; CHECK-NEXT: .reg .b64 %rd<9>;20; CHECK-EMPTY:21; CHECK-NEXT: // %bb.0: // %bb22; CHECK-NEXT: ld.param.b64 %rd1, [spam_param_0];23; CHECK-NEXT: ld.param.b64 %rd2, [spam_param_3];24; CHECK-NEXT: shl.b64 %rd3, %rd2, 1;25; CHECK-NEXT: add.s64 %rd4, %rd1, %rd3;26; CHECK-NEXT: ld.param.b64 %rd5, [spam_param_1];27; CHECK-NEXT: ld.global.nc.s16 %r1, [%rd4+16];28; CHECK-NEXT: mul.wide.s32 %rd6, %r1, %r1;29; CHECK-NEXT: ld.global.b64 %rd7, [%rd5];30; CHECK-NEXT: add.s64 %rd8, %rd6, %rd7;31; CHECK-NEXT: st.global.b64 [%rd5], %rd8;32; CHECK-NEXT: ret;33bb:34 %tmp5 = add nsw i64 %arg3, 835 %tmp6 = getelementptr i16, ptr addrspace(1) %arg, i64 %tmp536 %tmp7 = load i16, ptr addrspace(1) %tmp6, align 237 %tmp8 = sext i16 %tmp7 to i6438 %tmp9 = mul nsw i64 %tmp8, %tmp839 %tmp10 = load i64, ptr addrspace(1) %arg1, align 840 %tmp11 = add nsw i64 %tmp9, %tmp1041 store i64 %tmp11, ptr addrspace(1) %arg1, align 842 ret void43}44 45attributes #0 = { norecurse nounwind "polly.skip.fn" "nvvm.maxntid"="1,1,1" }46