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1; RUN: llc -O2 < %s -mtriple=nvptx64 -mcpu=sm_35 | FileCheck %s --check-prefix=O2 --check-prefix=CHECK2; RUN: llc -O0 < %s -mtriple=nvptx64 -mcpu=sm_35 | FileCheck %s --check-prefix=O0 --check-prefix=CHECK3; RUN: %if ptxas %{ llc -O2 < %s -mtriple=nvptx64 -mcpu=sm_35 | %ptxas-verify %}4; RUN: %if ptxas %{ llc -O0 < %s -mtriple=nvptx64 -mcpu=sm_35 | %ptxas-verify %}5 6; The following IR7;8; quot = n / d9; rem = n % d10;11; should be transformed into12;13; quot = n / d14; rem = n - (n / d) * d15;16; during NVPTX isel, at -O2. At -O0, we should leave it alone.17 18; CHECK-LABEL: sdiv32(19define void @sdiv32(i32 %n, i32 %d, ptr %quot_ret, ptr %rem_ret) {20 ; CHECK: div.s32 [[quot:%r[0-9]+]], [[num:%r[0-9]+]], [[den:%r[0-9]+]];21 %quot = sdiv i32 %n, %d22 23 ; O0: rem.s3224 ; (This is unfortunately order-sensitive, even though mul is commutative.)25 ; O2: mul.lo.s32 [[mul:%r[0-9]+]], [[quot]], [[den]];26 ; O2: sub.s32 [[rem:%r[0-9]+]], [[num]], [[mul]]27 %rem = srem i32 %n, %d28 29 ; O2: st{{.*}}[[quot]]30 store i32 %quot, ptr %quot_ret31 ; O2: st{{.*}}[[rem]]32 store i32 %rem, ptr %rem_ret33 ret void34}35 36; CHECK-LABEL: udiv32(37define void @udiv32(i32 %n, i32 %d, ptr %quot_ret, ptr %rem_ret) {38 ; CHECK: div.u32 [[quot:%r[0-9]+]], [[num:%r[0-9]+]], [[den:%r[0-9]+]];39 %quot = udiv i32 %n, %d40 41 ; O0: rem.u3242 43 ; Selection DAG doesn't know whether this is signed or unsigned44 ; multiplication and subtraction, but it doesn't make a difference either45 ; way.46 ; O2: mul.lo.{{u|s}}32 [[mul:%r[0-9]+]], [[quot]], [[den]];47 ; O2: sub.{{u|s}}32 [[rem:%r[0-9]+]], [[num]], [[mul]]48 %rem = urem i32 %n, %d49 50 ; O2: st{{.*}}[[quot]]51 store i32 %quot, ptr %quot_ret52 ; O2: st{{.*}}[[rem]]53 store i32 %rem, ptr %rem_ret54 ret void55}56 57; Check that we don't perform this optimization if one operation is signed and58; the other isn't.59; CHECK-LABEL: mismatched_types1(60define void @mismatched_types1(i32 %n, i32 %d, ptr %quot_ret, ptr %rem_ret) {61 ; CHECK: div.u3262 ; CHECK: rem.s3263 %quot = udiv i32 %n, %d64 %rem = srem i32 %n, %d65 store i32 %quot, ptr %quot_ret66 store i32 %rem, ptr %rem_ret67 ret void68}69 70; CHECK-LABEL: mismatched_types2(71define void @mismatched_types2(i32 %n, i32 %d, ptr %quot_ret, ptr %rem_ret) {72 ; CHECK: div.s3273 ; CHECK: rem.u3274 %quot = sdiv i32 %n, %d75 %rem = urem i32 %n, %d76 store i32 %quot, ptr %quot_ret77 store i32 %rem, ptr %rem_ret78 ret void79}80 81; Check that we don't perform this optimization if the inputs to the div don't82; match the inputs to the rem.83; CHECK-LABEL: mismatched_inputs1(84define void @mismatched_inputs1(i32 %n, i32 %d, ptr %quot_ret, ptr %rem_ret) {85 ; CHECK: div.s3286 ; CHECK: rem.s3287 %quot = sdiv i32 %n, %d88 %rem = srem i32 %d, %n89 store i32 %quot, ptr %quot_ret90 store i32 %rem, ptr %rem_ret91 ret void92}93 94; CHECK-LABEL: mismatched_inputs2(95define void @mismatched_inputs2(i32 %n1, i32 %n2, i32 %d, ptr %quot_ret, ptr %rem_ret) {96 ; CHECK: div.s3297 ; CHECK: rem.s3298 %quot = sdiv i32 %n1, %d99 %rem = srem i32 %n2, %d100 store i32 %quot, ptr %quot_ret101 store i32 %rem, ptr %rem_ret102 ret void103}104 105; CHECK-LABEL: mismatched_inputs3(106define void @mismatched_inputs3(i32 %n, i32 %d1, i32 %d2, ptr %quot_ret, ptr %rem_ret) {107 ; CHECK: div.s32108 ; CHECK: rem.s32109 %quot = sdiv i32 %n, %d1110 %rem = srem i32 %n, %d2111 store i32 %quot, ptr %quot_ret112 store i32 %rem, ptr %rem_ret113 ret void114}115