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1; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_20 -verify-machineinstrs | FileCheck %s2; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %}3 4 5declare i32 @llvm.nvvm.read.ptx.sreg.envreg0()6declare i32 @llvm.nvvm.read.ptx.sreg.envreg1()7declare i32 @llvm.nvvm.read.ptx.sreg.envreg2()8declare i32 @llvm.nvvm.read.ptx.sreg.envreg3()9declare i32 @llvm.nvvm.read.ptx.sreg.envreg4()10declare i32 @llvm.nvvm.read.ptx.sreg.envreg5()11declare i32 @llvm.nvvm.read.ptx.sreg.envreg6()12declare i32 @llvm.nvvm.read.ptx.sreg.envreg7()13declare i32 @llvm.nvvm.read.ptx.sreg.envreg8()14declare i32 @llvm.nvvm.read.ptx.sreg.envreg9()15declare i32 @llvm.nvvm.read.ptx.sreg.envreg10()16declare i32 @llvm.nvvm.read.ptx.sreg.envreg11()17declare i32 @llvm.nvvm.read.ptx.sreg.envreg12()18declare i32 @llvm.nvvm.read.ptx.sreg.envreg13()19declare i32 @llvm.nvvm.read.ptx.sreg.envreg14()20declare i32 @llvm.nvvm.read.ptx.sreg.envreg15()21declare i32 @llvm.nvvm.read.ptx.sreg.envreg16()22declare i32 @llvm.nvvm.read.ptx.sreg.envreg17()23declare i32 @llvm.nvvm.read.ptx.sreg.envreg18()24declare i32 @llvm.nvvm.read.ptx.sreg.envreg19()25declare i32 @llvm.nvvm.read.ptx.sreg.envreg20()26declare i32 @llvm.nvvm.read.ptx.sreg.envreg21()27declare i32 @llvm.nvvm.read.ptx.sreg.envreg22()28declare i32 @llvm.nvvm.read.ptx.sreg.envreg23()29declare i32 @llvm.nvvm.read.ptx.sreg.envreg24()30declare i32 @llvm.nvvm.read.ptx.sreg.envreg25()31declare i32 @llvm.nvvm.read.ptx.sreg.envreg26()32declare i32 @llvm.nvvm.read.ptx.sreg.envreg27()33declare i32 @llvm.nvvm.read.ptx.sreg.envreg28()34declare i32 @llvm.nvvm.read.ptx.sreg.envreg29()35declare i32 @llvm.nvvm.read.ptx.sreg.envreg30()36declare i32 @llvm.nvvm.read.ptx.sreg.envreg31()37 38 39; CHECK: foo40define i32 @foo() {41; CHECK: mov.b32 %r{{[0-9]+}}, %envreg042 %val0 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg0()43; CHECK: mov.b32 %r{{[0-9]+}}, %envreg144 %val1 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg1()45; CHECK: mov.b32 %r{{[0-9]+}}, %envreg246 %val2 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg2()47; CHECK: mov.b32 %r{{[0-9]+}}, %envreg348 %val3 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg3()49; CHECK: mov.b32 %r{{[0-9]+}}, %envreg450 %val4 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg4()51; CHECK: mov.b32 %r{{[0-9]+}}, %envreg552 %val5 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg5()53; CHECK: mov.b32 %r{{[0-9]+}}, %envreg654 %val6 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg6()55; CHECK: mov.b32 %r{{[0-9]+}}, %envreg756 %val7 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg7()57; CHECK: mov.b32 %r{{[0-9]+}}, %envreg858 %val8 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg8()59; CHECK: mov.b32 %r{{[0-9]+}}, %envreg960 %val9 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg9()61; CHECK: mov.b32 %r{{[0-9]+}}, %envreg1062 %val10 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg10()63; CHECK: mov.b32 %r{{[0-9]+}}, %envreg1164 %val11 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg11()65; CHECK: mov.b32 %r{{[0-9]+}}, %envreg1266 %val12 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg12()67; CHECK: mov.b32 %r{{[0-9]+}}, %envreg1368 %val13 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg13()69; CHECK: mov.b32 %r{{[0-9]+}}, %envreg1470 %val14 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg14()71; CHECK: mov.b32 %r{{[0-9]+}}, %envreg1572 %val15 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg15()73; CHECK: mov.b32 %r{{[0-9]+}}, %envreg1674 %val16 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg16()75; CHECK: mov.b32 %r{{[0-9]+}}, %envreg1776 %val17 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg17()77; CHECK: mov.b32 %r{{[0-9]+}}, %envreg1878 %val18 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg18()79; CHECK: mov.b32 %r{{[0-9]+}}, %envreg1980 %val19 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg19()81; CHECK: mov.b32 %r{{[0-9]+}}, %envreg2082 %val20 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg20()83; CHECK: mov.b32 %r{{[0-9]+}}, %envreg2184 %val21 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg21()85; CHECK: mov.b32 %r{{[0-9]+}}, %envreg2286 %val22 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg22()87; CHECK: mov.b32 %r{{[0-9]+}}, %envreg2388 %val23 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg23()89; CHECK: mov.b32 %r{{[0-9]+}}, %envreg2490 %val24 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg24()91; CHECK: mov.b32 %r{{[0-9]+}}, %envreg2592 %val25 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg25()93; CHECK: mov.b32 %r{{[0-9]+}}, %envreg2694 %val26 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg26()95; CHECK: mov.b32 %r{{[0-9]+}}, %envreg2796 %val27 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg27()97; CHECK: mov.b32 %r{{[0-9]+}}, %envreg2898 %val28 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg28()99; CHECK: mov.b32 %r{{[0-9]+}}, %envreg29100 %val29 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg29()101; CHECK: mov.b32 %r{{[0-9]+}}, %envreg30102 %val30 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg30()103; CHECK: mov.b32 %r{{[0-9]+}}, %envreg31104 %val31 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg31()105 106 107 %ret0 = add i32 %val0, %val1108 %ret1 = add i32 %ret0, %val2109 %ret2 = add i32 %ret1, %val3110 %ret3 = add i32 %ret2, %val4111 %ret4 = add i32 %ret3, %val5112 %ret5 = add i32 %ret4, %val6113 %ret6 = add i32 %ret5, %val7114 %ret7 = add i32 %ret6, %val8115 %ret8 = add i32 %ret7, %val9116 %ret9 = add i32 %ret8, %val10117 %ret10 = add i32 %ret9, %val11118 %ret11 = add i32 %ret10, %val12119 %ret12 = add i32 %ret11, %val13120 %ret13 = add i32 %ret12, %val14121 %ret14 = add i32 %ret13, %val15122 %ret15 = add i32 %ret14, %val16123 %ret16 = add i32 %ret15, %val17124 %ret17 = add i32 %ret16, %val18125 %ret18 = add i32 %ret17, %val19126 %ret19 = add i32 %ret18, %val20127 %ret20 = add i32 %ret19, %val21128 %ret21 = add i32 %ret20, %val22129 %ret22 = add i32 %ret21, %val23130 %ret23 = add i32 %ret22, %val24131 %ret24 = add i32 %ret23, %val25132 %ret25 = add i32 %ret24, %val26133 %ret26 = add i32 %ret25, %val27134 %ret27 = add i32 %ret26, %val28135 %ret28 = add i32 %ret27, %val29136 %ret29 = add i32 %ret28, %val30137 %ret30 = add i32 %ret29, %val31138 139 ret i32 %ret30140}141