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1; ## Full FP16 support enabled by default.2; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 -asm-verbose=false \3; RUN: -O0 -disable-post-ra -frame-pointer=all -verify-machineinstrs \4; RUN: -mattr=+ptx60 \5; RUN: | FileCheck -check-prefixes CHECK,CHECK-NOFTZ,CHECK-F16-NOFTZ %s6; RUN: %if ptxas-sm_53 && ptxas-isa-6.0 %{ \7; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 -asm-verbose=false \8; RUN: -O0 -disable-post-ra -frame-pointer=all -verify-machineinstrs \9; RUN: -mattr=+ptx60 \10; RUN: | %ptxas-verify -arch=sm_53 \11; RUN: %}12; ## Full FP16 with FTZ13; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 -asm-verbose=false \14; RUN: -O0 -disable-post-ra -frame-pointer=all -verify-machineinstrs \15; RUN: -denormal-fp-math-f32=preserve-sign -mattr=+ptx60 \16; RUN: | FileCheck -check-prefixes CHECK,CHECK-F16-FTZ %s17; RUN: %if ptxas-sm_53 && ptxas-isa-6.0 %{ \18; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 -asm-verbose=false \19; RUN: -O0 -disable-post-ra -frame-pointer=all -verify-machineinstrs \20; RUN: -denormal-fp-math-f32=preserve-sign -mattr=+ptx60 \21; RUN: | %ptxas-verify -arch=sm_53 \22; RUN: %}23; ## FP16 support explicitly disabled.24; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 -asm-verbose=false \25; RUN: -O0 -disable-post-ra -frame-pointer=all --nvptx-no-f16-math \26; RUN: -verify-machineinstrs -mattr=+ptx60 \27; RUN: | FileCheck -check-prefixes CHECK,CHECK-NOFTZ,CHECK-NOF16 %s28; RUN: %if ptxas-sm_53 %{ \29; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 -asm-verbose=false \30; RUN: -O0 -disable-post-ra -frame-pointer=all --nvptx-no-f16-math \31; RUN: | %ptxas-verify -arch=sm_53 \32; RUN: %}33; ## FP16 is not supported by hardware.34; RUN: llc < %s -O0 -mtriple=nvptx64-nvidia-cuda -mcpu=sm_52 -asm-verbose=false \35; RUN: -disable-post-ra -frame-pointer=all -verify-machineinstrs \36; RUN: | FileCheck -check-prefixes CHECK,CHECK-NOFTZ,CHECK-NOF16 %s37; RUN: %if ptxas-sm_52 %{ \38; RUN: llc < %s -O0 -mtriple=nvptx64-nvidia-cuda -mcpu=sm_52 -asm-verbose=false \39; RUN: -disable-post-ra -frame-pointer=all -verify-machineinstrs \40; RUN: | %ptxas-verify -arch=sm_52 \41; RUN: %}42 43target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"44 45; CHECK-LABEL: test_ret_const(46; CHECK: st.param.b16 [func_retval0], 0x3C00;47; CHECK-NEXT: ret;48define half @test_ret_const() #0 {49 ret half 1.050}51 52; CHECK-LABEL: test_fadd(53; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_fadd_param_0];54; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_fadd_param_1];55; CHECK-F16-NOFTZ-NEXT: add.rn.f16 [[R:%rs[0-9]+]], [[A]], [[B]];56; CHECK-F16-FTZ-NEXT: add.rn.ftz.f16 [[R:%rs[0-9]+]], [[A]], [[B]];57; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%r[0-9]+]], [[A]]58; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%r[0-9]+]], [[B]]59; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%r[0-9]+]], [[A32]], [[B32]];60; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%rs[0-9]+]], [[R32]]61; CHECK-NEXT: st.param.b16 [func_retval0], [[R]];62; CHECK-NEXT: ret;63define half @test_fadd(half %a, half %b) #0 {64 %r = fadd half %a, %b65 ret half %r66}67 68; CHECK-LABEL: test_fadd_v1f16(69; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_fadd_v1f16_param_0];70; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_fadd_v1f16_param_1];71; CHECK-F16-NOFTZ-NEXT: add.rn.f16 [[R:%rs[0-9]+]], [[A]], [[B]];72; CHECK-F16-FTZ-NEXT: add.rn.ftz.f16 [[R:%rs[0-9]+]], [[A]], [[B]];73; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%r[0-9]+]], [[A]]74; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%r[0-9]+]], [[B]]75; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%r[0-9]+]], [[A32]], [[B32]];76; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%rs[0-9]+]], [[R32]]77; CHECK-NEXT: st.param.b16 [func_retval0], [[R]];78; CHECK-NEXT: ret;79define <1 x half> @test_fadd_v1f16(<1 x half> %a, <1 x half> %b) #0 {80 %r = fadd <1 x half> %a, %b81 ret <1 x half> %r82}83 84; Check that we can lower fadd with immediate arguments.85; CHECK-LABEL: test_fadd_imm_0(86; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_fadd_imm_0_param_0];87; CHECK-F16-NOFTZ-DAG: mov.b16 [[A:%rs[0-9]+]], 0x3C00;88; CHECK-F16-NOFTZ-NEXT: add.rn.f16 [[R:%rs[0-9]+]], [[B]], [[A]];89; CHECK-F16-FTZ-DAG: mov.b16 [[A:%rs[0-9]+]], 0x3C00;90; CHECK-F16-FTZ-NEXT: add.rn.ftz.f16 [[R:%rs[0-9]+]], [[B]], [[A]];91; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%r[0-9]+]], [[B]]92; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%r[0-9]+]], [[B32]], 0f3F800000;93; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%rs[0-9]+]], [[R32]]94; CHECK-NEXT: st.param.b16 [func_retval0], [[R]];95; CHECK-NEXT: ret;96define half @test_fadd_imm_0(half %b) #0 {97 %r = fadd half 1.0, %b98 ret half %r99}100 101; CHECK-LABEL: test_fadd_imm_1(102; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_fadd_imm_1_param_0];103; CHECK-F16-NOFTZ-DAG: mov.b16 [[A:%rs[0-9]+]], 0x3C00;104; CHECK-F16-NOFTZ-NEXT: add.rn.f16 [[R:%rs[0-9]+]], [[B]], [[A]];105; CHECK-F16-FTZ-DAG: mov.b16 [[A:%rs[0-9]+]], 0x3C00;106; CHECK-F16-FTZ-NEXT: add.rn.ftz.f16 [[R:%rs[0-9]+]], [[B]], [[A]];107; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%r[0-9]+]], [[B]]108; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%r[0-9]+]], [[B32]], 0f3F800000;109; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%rs[0-9]+]], [[R32]]110; CHECK-NEXT: st.param.b16 [func_retval0], [[R]];111; CHECK-NEXT: ret;112define half @test_fadd_imm_1(half %a) #0 {113 %r = fadd half %a, 1.0114 ret half %r115}116 117; CHECK-LABEL: test_fsub(118; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_fsub_param_0];119; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_fsub_param_1];120; CHECK-F16-NOFTZ-NEXT: sub.rn.f16 [[R:%rs[0-9]+]], [[A]], [[B]];121; CHECK-F16-FTZ-NEXT: sub.rn.ftz.f16 [[R:%rs[0-9]+]], [[A]], [[B]];122; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%r[0-9]+]], [[A]]123; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%r[0-9]+]], [[B]]124; CHECK-NOF16-NEXT: sub.rn.f32 [[R32:%r[0-9]+]], [[A32]], [[B32]];125; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%rs[0-9]+]], [[R32]]126; CHECK-NEXT: st.param.b16 [func_retval0], [[R]];127; CHECK-NEXT: ret;128define half @test_fsub(half %a, half %b) #0 {129 %r = fsub half %a, %b130 ret half %r131}132 133; CHECK-LABEL: test_old_fneg(134; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_old_fneg_param_0];135; CHECK-F16-NOFTZ-NEXT: mov.b16 [[Z:%rs[0-9]+]], 0x0000136; CHECK-F16-NOFTZ-NEXT: sub.rn.f16 [[R:%rs[0-9]+]], [[Z]], [[A]];137; CHECK-F16-FTZ-NEXT: mov.b16 [[Z:%rs[0-9]+]], 0x0000138; CHECK-F16-FTZ-NEXT: sub.rn.ftz.f16 [[R:%rs[0-9]+]], [[Z]], [[A]];139; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%r[0-9]+]], [[A]]140; CHECK-NOF16-DAG: mov.b32 [[Z:%r[0-9]+]], 0f00000000;141; CHECK-NOF16-NEXT: sub.rn.f32 [[R32:%r[0-9]+]], [[Z]], [[A32]];142; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%rs[0-9]+]], [[R32]]143; CHECK-NEXT: st.param.b16 [func_retval0], [[R]];144; CHECK-NEXT: ret;145define half @test_old_fneg(half %a) #0 {146 %r = fsub half 0.0, %a147 ret half %r148}149 150; CHECK-LABEL: test_fneg(151; CHECK: ld.param.b16 [[A:%rs[0-9]+]], [test_fneg_param_0];152; CHECK-F16-NOFTZ-NEXT: neg.f16 [[R:%rs[0-9]+]], [[A]];153; CHECK-F16-FTZ-NEXT: neg.ftz.f16 [[R:%rs[0-9]+]], [[A]];154; CHECK-NOF16-NEXT: xor.b16 [[R:%rs[0-9]+]], [[A]], -32768;155; CHECK-NEXT: st.param.b16 [func_retval0], [[R]];156; CHECK-NEXT: ret;157define half @test_fneg(half %a) #0 {158 %r = fneg half %a159 ret half %r160}161 162; CHECK-LABEL: test_fmul(163; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_fmul_param_0];164; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_fmul_param_1];165; CHECK-F16-NOFTZ-NEXT: mul.rn.f16 [[R:%rs[0-9]+]], [[A]], [[B]];166; CHECK-F16-FTZ-NEXT: mul.rn.ftz.f16 [[R:%rs[0-9]+]], [[A]], [[B]];167; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%r[0-9]+]], [[A]]168; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%r[0-9]+]], [[B]]169; CHECK-NOF16-NEXT: mul.rn.f32 [[R32:%r[0-9]+]], [[A32]], [[B32]];170; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%rs[0-9]+]], [[R32]]171; CHECK-NEXT: st.param.b16 [func_retval0], [[R]];172; CHECK-NEXT: ret;173define half @test_fmul(half %a, half %b) #0 {174 %r = fmul half %a, %b175 ret half %r176}177 178; CHECK-LABEL: test_fdiv(179; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_fdiv_param_0];180; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_fdiv_param_1];181; CHECK-NOFTZ-DAG: cvt.f32.f16 [[F0:%r[0-9]+]], [[A]];182; CHECK-NOFTZ-DAG: cvt.f32.f16 [[F1:%r[0-9]+]], [[B]];183; CHECK-NOFTZ-NEXT: div.rn.f32 [[FR:%r[0-9]+]], [[F0]], [[F1]];184; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[F0:%r[0-9]+]], [[A]];185; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[F1:%r[0-9]+]], [[B]];186; CHECK-F16-FTZ-NEXT: div.rn.ftz.f32 [[FR:%r[0-9]+]], [[F0]], [[F1]];187; CHECK-NEXT: cvt.rn.f16.f32 [[R:%rs[0-9]+]], [[FR]];188; CHECK-NEXT: st.param.b16 [func_retval0], [[R]];189; CHECK-NEXT: ret;190define half @test_fdiv(half %a, half %b) #0 {191 %r = fdiv half %a, %b192 ret half %r193}194 195; CHECK-LABEL: test_frem(196; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_frem_param_0];197; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_frem_param_1];198; CHECK-NOFTZ-DAG: cvt.f32.f16 [[FA:%r[0-9]+]], [[A]];199; CHECK-NOFTZ-DAG: cvt.f32.f16 [[FB:%r[0-9]+]], [[B]];200; CHECK-NOFTZ-NEXT: div.rn.f32 [[D:%r[0-9]+]], [[FA]], [[FB]];201; CHECK-NOFTZ-NEXT: cvt.rzi.f32.f32 [[DI:%r[0-9]+]], [[D]];202; CHECK-NOFTZ-NEXT: neg.f32 [[DNEG:%r[0-9]+]], [[DI]];203; CHECK-NOFTZ-NEXT: fma.rn.f32 [[RF:%r[0-9]+]], [[DNEG]], [[FB]], [[FA]];204; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[FA:%r[0-9]+]], [[A]];205; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[FB:%r[0-9]+]], [[B]];206; CHECK-F16-FTZ-NEXT: div.rn.ftz.f32 [[D:%r[0-9]+]], [[FA]], [[FB]];207; CHECK-F16-FTZ-NEXT: cvt.rzi.ftz.f32.f32 [[DI:%r[0-9]+]], [[D]];208; CHECK-F16-FTZ-NEXT: neg.ftz.f32 [[DNEG:%r[0-9]+]], [[DI]];209; CHECK-F16-FTZ-NEXT: fma.rn.ftz.f32 [[RF:%r[0-9]+]], [[DNEG]], [[FB]], [[FA]];210; CHECK-NEXT: testp.infinite.f32 [[ISBINF:%p[0-9]+]], [[FB]];211; CHECK-NEXT: selp.f32 [[RESULT:%r[0-9]+]], [[FA]], [[RF]], [[ISBINF]];212; CHECK-NEXT: cvt.rn.f16.f32 [[R:%rs[0-9]+]], [[RESULT]];213; CHECK-NEXT: st.param.b16 [func_retval0], [[R]];214; CHECK-NEXT: ret;215define half @test_frem(half %a, half %b) #0 {216 %r = frem half %a, %b217 ret half %r218}219 220; CHECK-LABEL: test_store(221; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_store_param_0];222; CHECK-DAG: ld.param.b64 %[[PTR:rd[0-9]+]], [test_store_param_1];223; CHECK-NEXT: st.b16 [%[[PTR]]], [[A]];224; CHECK-NEXT: ret;225define void @test_store(half %a, ptr %b) #0 {226 store half %a, ptr %b227 ret void228}229 230; CHECK-LABEL: test_load(231; CHECK: ld.param.b64 %[[PTR:rd[0-9]+]], [test_load_param_0];232; CHECK-NEXT: ld.b16 [[R:%rs[0-9]+]], [%[[PTR]]];233; CHECK-NEXT: st.param.b16 [func_retval0], [[R]];234; CHECK-NEXT: ret;235define half @test_load(ptr %a) #0 {236 %r = load half, ptr %a237 ret half %r238}239 240; CHECK-LABEL: .visible .func test_halfp0a1(241; CHECK-DAG: ld.param.b64 %[[FROM:rd?[0-9]+]], [test_halfp0a1_param_0];242; CHECK-DAG: ld.param.b64 %[[TO:rd?[0-9]+]], [test_halfp0a1_param_1];243; CHECK-DAG: ld.b8 [[B0:%r[sd]?[0-9]+]], [%[[FROM]]]244; CHECK-DAG: st.b8 [%[[TO]]], [[B0]]245; CHECK-DAG: ld.b8 [[B1:%r[sd]?[0-9]+]], [%[[FROM]]+1]246; CHECK-DAG: st.b8 [%[[TO]]+1], [[B1]]247; CHECK: ret248define void @test_halfp0a1(ptr noalias readonly %rrom, ptr %to) {249 %1 = load half, ptr %rrom , align 1250 store half %1, ptr %to , align 1251 ret void252}253 254declare half @test_callee(half %a, half %b) #0255 256; CHECK-LABEL: test_call(257; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_call_param_0];258; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_call_param_1];259; CHECK: {260; CHECK-DAG: .param .align 2 .b8 param0[2];261; CHECK-DAG: .param .align 2 .b8 param1[2];262; CHECK-DAG: st.param.b16 [param0], [[A]];263; CHECK-DAG: st.param.b16 [param1], [[B]];264; CHECK-DAG: .param .align 2 .b8 retval0[2];265; CHECK: call.uni (retval0), test_callee, (param0, param1);266; CHECK-NEXT: ld.param.b16 [[R:%rs[0-9]+]], [retval0];267; CHECK-NEXT: }268; CHECK-NEXT: st.param.b16 [func_retval0], [[R]];269; CHECK-NEXT: ret;270define half @test_call(half %a, half %b) #0 {271 %r = call half @test_callee(half %a, half %b)272 ret half %r273}274 275; CHECK-LABEL: test_call_flipped(276; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_call_flipped_param_0];277; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_call_flipped_param_1];278; CHECK: {279; CHECK-DAG: .param .align 2 .b8 param0[2];280; CHECK-DAG: .param .align 2 .b8 param1[2];281; CHECK-DAG: st.param.b16 [param0], [[B]];282; CHECK-DAG: st.param.b16 [param1], [[A]];283; CHECK-DAG: .param .align 2 .b8 retval0[2];284; CHECK: call.uni (retval0), test_callee, (param0, param1);285; CHECK-NEXT: ld.param.b16 [[R:%rs[0-9]+]], [retval0];286; CHECK-NEXT: }287; CHECK-NEXT: st.param.b16 [func_retval0], [[R]];288; CHECK-NEXT: ret;289define half @test_call_flipped(half %a, half %b) #0 {290 %r = call half @test_callee(half %b, half %a)291 ret half %r292}293 294; CHECK-LABEL: test_tailcall_flipped(295; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_tailcall_flipped_param_0];296; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_tailcall_flipped_param_1];297; CHECK: {298; CHECK-DAG: .param .align 2 .b8 param0[2];299; CHECK-DAG: .param .align 2 .b8 param1[2];300; CHECK-DAG: st.param.b16 [param0], [[B]];301; CHECK-DAG: st.param.b16 [param1], [[A]];302; CHECK-DAG: .param .align 2 .b8 retval0[2];303; CHECK: call.uni (retval0), test_callee, (param0, param1);304; CHECK-NEXT: ld.param.b16 [[R:%rs[0-9]+]], [retval0];305; CHECK-NEXT: }306; CHECK-NEXT: st.param.b16 [func_retval0], [[R]];307; CHECK-NEXT: ret;308define half @test_tailcall_flipped(half %a, half %b) #0 {309 %r = tail call half @test_callee(half %b, half %a)310 ret half %r311}312 313; CHECK-LABEL: test_select(314; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_select_param_0];315; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_select_param_1];316; CHECK-DAG: setp.ne.b16 [[PRED:%p[0-9]+]], %rs{{.*}}, 0;317; CHECK-NEXT: selp.b16 [[R:%rs[0-9]+]], [[A]], [[B]], [[PRED]];318; CHECK-NEXT: st.param.b16 [func_retval0], [[R]];319; CHECK-NEXT: ret;320define half @test_select(half %a, half %b, i1 zeroext %c) #0 {321 %r = select i1 %c, half %a, half %b322 ret half %r323}324 325; CHECK-LABEL: test_select_cc(326; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_select_cc_param_0];327; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_select_cc_param_1];328; CHECK-DAG: ld.param.b16 [[C:%rs[0-9]+]], [test_select_cc_param_2];329; CHECK-DAG: ld.param.b16 [[D:%rs[0-9]+]], [test_select_cc_param_3];330; CHECK-F16-NOFTZ: setp.neu.f16 [[PRED:%p[0-9]+]], [[C]], [[D]]331; CHECK-NOF16-DAG: cvt.f32.f16 [[DF:%r[0-9]+]], [[D]];332; CHECK-NOF16-DAG: cvt.f32.f16 [[CF:%r[0-9]+]], [[C]];333; CHECK-NOF16: setp.neu.f32 [[PRED:%p[0-9]+]], [[CF]], [[DF]]334; CHECK: selp.b16 [[R:%rs[0-9]+]], [[A]], [[B]], [[PRED]];335; CHECK-NEXT: st.param.b16 [func_retval0], [[R]];336; CHECK-NEXT: ret;337define half @test_select_cc(half %a, half %b, half %c, half %d) #0 {338 %cc = fcmp une half %c, %d339 %r = select i1 %cc, half %a, half %b340 ret half %r341}342 343; CHECK-LABEL: test_select_cc_f32_f16(344; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_select_cc_f32_f16_param_0];345; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_select_cc_f32_f16_param_1];346; CHECK-DAG: ld.param.b16 [[C:%rs[0-9]+]], [test_select_cc_f32_f16_param_2];347; CHECK-DAG: ld.param.b16 [[D:%rs[0-9]+]], [test_select_cc_f32_f16_param_3];348; CHECK-F16-NOFTZ: setp.neu.f16 [[PRED:%p[0-9]+]], [[C]], [[D]]349; CHECK-F16-FTZ: setp.neu.ftz.f16 [[PRED:%p[0-9]+]], [[C]], [[D]]350; CHECK-NOF16-DAG: cvt.f32.f16 [[DF:%r[0-9]+]], [[D]];351; CHECK-NOF16-DAG: cvt.f32.f16 [[CF:%r[0-9]+]], [[C]];352; CHECK-NOF16: setp.neu.f32 [[PRED:%p[0-9]+]], [[CF]], [[DF]]353; CHECK-NEXT: selp.f32 [[R:%r[0-9]+]], [[A]], [[B]], [[PRED]];354; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];355; CHECK-NEXT: ret;356define float @test_select_cc_f32_f16(float %a, float %b, half %c, half %d) #0 {357 %cc = fcmp une half %c, %d358 %r = select i1 %cc, float %a, float %b359 ret float %r360}361 362; CHECK-LABEL: test_select_cc_f16_f32(363; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_select_cc_f16_f32_param_0];364; CHECK-DAG: ld.param.b32 [[C:%r[0-9]+]], [test_select_cc_f16_f32_param_2];365; CHECK-DAG: ld.param.b32 [[D:%r[0-9]+]], [test_select_cc_f16_f32_param_3];366; CHECK-NOFTZ-DAG: setp.neu.f32 [[PRED:%p[0-9]+]], [[C]], [[D]]367; CHECK-F16-FTZ-DAG: setp.neu.ftz.f32 [[PRED:%p[0-9]+]], [[C]], [[D]]368; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_select_cc_f16_f32_param_1];369; CHECK-NEXT: selp.b16 [[R:%rs[0-9]+]], [[A]], [[B]], [[PRED]];370; CHECK-NEXT: st.param.b16 [func_retval0], [[R]];371; CHECK-NEXT: ret;372define half @test_select_cc_f16_f32(half %a, half %b, float %c, float %d) #0 {373 %cc = fcmp une float %c, %d374 %r = select i1 %cc, half %a, half %b375 ret half %r376}377 378; CHECK-LABEL: test_fcmp_une(379; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_fcmp_une_param_0];380; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_fcmp_une_param_1];381; CHECK-F16-NOFTZ: setp.neu.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]382; CHECK-F16-FTZ: setp.neu.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]383; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%r[0-9]+]], [[A]];384; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%r[0-9]+]], [[B]];385; CHECK-NOF16: setp.neu.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]386; CHECK-NEXT: selp.b32 [[R:%r[0-9]+]], -1, 0, [[PRED]];387; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];388; CHECK-NEXT: ret;389define i1 @test_fcmp_une(half %a, half %b) #0 {390 %r = fcmp une half %a, %b391 ret i1 %r392}393 394; CHECK-LABEL: test_fcmp_ueq(395; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_fcmp_ueq_param_0];396; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_fcmp_ueq_param_1];397; CHECK-F16-NOFTZ: setp.equ.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]398; CHECK-F16-FTZ: setp.equ.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]399; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%r[0-9]+]], [[A]];400; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%r[0-9]+]], [[B]];401; CHECK-NOF16: setp.equ.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]402; CHECK-NEXT: selp.b32 [[R:%r[0-9]+]], -1, 0, [[PRED]];403; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];404; CHECK-NEXT: ret;405define i1 @test_fcmp_ueq(half %a, half %b) #0 {406 %r = fcmp ueq half %a, %b407 ret i1 %r408}409 410; CHECK-LABEL: test_fcmp_ugt(411; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_fcmp_ugt_param_0];412; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_fcmp_ugt_param_1];413; CHECK-F16-NOFTZ: setp.gtu.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]414; CHECK-F16-FTZ: setp.gtu.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]415; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%r[0-9]+]], [[A]];416; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%r[0-9]+]], [[B]];417; CHECK-NOF16: setp.gtu.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]418; CHECK-NEXT: selp.b32 [[R:%r[0-9]+]], -1, 0, [[PRED]];419; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];420; CHECK-NEXT: ret;421define i1 @test_fcmp_ugt(half %a, half %b) #0 {422 %r = fcmp ugt half %a, %b423 ret i1 %r424}425 426; CHECK-LABEL: test_fcmp_uge(427; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_fcmp_uge_param_0];428; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_fcmp_uge_param_1];429; CHECK-F16-NOFTZ: setp.geu.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]430; CHECK-F16-FTZ: setp.geu.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]431; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%r[0-9]+]], [[A]];432; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%r[0-9]+]], [[B]];433; CHECK-NOF16: setp.geu.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]434; CHECK-NEXT: selp.b32 [[R:%r[0-9]+]], -1, 0, [[PRED]];435; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];436; CHECK-NEXT: ret;437define i1 @test_fcmp_uge(half %a, half %b) #0 {438 %r = fcmp uge half %a, %b439 ret i1 %r440}441 442; CHECK-LABEL: test_fcmp_ult(443; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_fcmp_ult_param_0];444; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_fcmp_ult_param_1];445; CHECK-F16-NOFTZ: setp.ltu.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]446; CHECK-F16-FTZ: setp.ltu.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]447; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%r[0-9]+]], [[A]];448; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%r[0-9]+]], [[B]];449; CHECK-NOF16: setp.ltu.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]450; CHECK-NEXT: selp.b32 [[R:%r[0-9]+]], -1, 0, [[PRED]];451; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];452; CHECK-NEXT: ret;453define i1 @test_fcmp_ult(half %a, half %b) #0 {454 %r = fcmp ult half %a, %b455 ret i1 %r456}457 458; CHECK-LABEL: test_fcmp_ule(459; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_fcmp_ule_param_0];460; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_fcmp_ule_param_1];461; CHECK-F16-NOFTZ: setp.leu.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]462; CHECK-F16-FTZ: setp.leu.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]463; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%r[0-9]+]], [[A]];464; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%r[0-9]+]], [[B]];465; CHECK-NOF16: setp.leu.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]466; CHECK-NEXT: selp.b32 [[R:%r[0-9]+]], -1, 0, [[PRED]];467; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];468; CHECK-NEXT: ret;469define i1 @test_fcmp_ule(half %a, half %b) #0 {470 %r = fcmp ule half %a, %b471 ret i1 %r472}473 474 475; CHECK-LABEL: test_fcmp_uno(476; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_fcmp_uno_param_0];477; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_fcmp_uno_param_1];478; CHECK-F16-NOFTZ: setp.nan.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]479; CHECK-F16-FTZ: setp.nan.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]480; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%r[0-9]+]], [[A]];481; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%r[0-9]+]], [[B]];482; CHECK-NOF16: setp.nan.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]483; CHECK-NEXT: selp.b32 [[R:%r[0-9]+]], -1, 0, [[PRED]];484; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];485; CHECK-NEXT: ret;486define i1 @test_fcmp_uno(half %a, half %b) #0 {487 %r = fcmp uno half %a, %b488 ret i1 %r489}490 491; CHECK-LABEL: test_fcmp_one(492; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_fcmp_one_param_0];493; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_fcmp_one_param_1];494; CHECK-F16-NOFTZ: setp.ne.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]495; CHECK-F16-FTZ: setp.ne.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]496; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%r[0-9]+]], [[A]];497; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%r[0-9]+]], [[B]];498; CHECK-NOF16: setp.ne.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]499; CHECK-NEXT: selp.b32 [[R:%r[0-9]+]], -1, 0, [[PRED]];500; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];501; CHECK-NEXT: ret;502define i1 @test_fcmp_one(half %a, half %b) #0 {503 %r = fcmp one half %a, %b504 ret i1 %r505}506 507; CHECK-LABEL: test_fcmp_oeq(508; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_fcmp_oeq_param_0];509; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_fcmp_oeq_param_1];510; CHECK-F16-NOFTZ: setp.eq.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]511; CHECK-F16-FTZ: setp.eq.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]512; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%r[0-9]+]], [[A]];513; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%r[0-9]+]], [[B]];514; CHECK-NOF16: setp.eq.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]515; CHECK-NEXT: selp.b32 [[R:%r[0-9]+]], -1, 0, [[PRED]];516; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];517; CHECK-NEXT: ret;518define i1 @test_fcmp_oeq(half %a, half %b) #0 {519 %r = fcmp oeq half %a, %b520 ret i1 %r521}522 523; CHECK-LABEL: test_fcmp_ogt(524; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_fcmp_ogt_param_0];525; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_fcmp_ogt_param_1];526; CHECK-F16-NOFTZ: setp.gt.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]527; CHECK-F16-FTZ: setp.gt.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]528; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%r[0-9]+]], [[A]];529; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%r[0-9]+]], [[B]];530; CHECK-NOF16: setp.gt.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]531; CHECK-NEXT: selp.b32 [[R:%r[0-9]+]], -1, 0, [[PRED]];532; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];533; CHECK-NEXT: ret;534define i1 @test_fcmp_ogt(half %a, half %b) #0 {535 %r = fcmp ogt half %a, %b536 ret i1 %r537}538 539; CHECK-LABEL: test_fcmp_oge(540; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_fcmp_oge_param_0];541; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_fcmp_oge_param_1];542; CHECK-F16-NOFTZ: setp.ge.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]543; CHECK-F16-FTZ: setp.ge.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]544; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%r[0-9]+]], [[A]];545; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%r[0-9]+]], [[B]];546; CHECK-NOF16: setp.ge.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]547; CHECK-NEXT: selp.b32 [[R:%r[0-9]+]], -1, 0, [[PRED]];548; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];549; CHECK-NEXT: ret;550define i1 @test_fcmp_oge(half %a, half %b) #0 {551 %r = fcmp oge half %a, %b552 ret i1 %r553}554 555; XCHECK-LABEL: test_fcmp_olt(556; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_fcmp_olt_param_0];557; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_fcmp_olt_param_1];558; CHECK-F16-NOFTZ: setp.lt.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]559; CHECK-F16-FTZ: setp.lt.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]560; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%r[0-9]+]], [[A]];561; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%r[0-9]+]], [[B]];562; CHECK-NOF16: setp.lt.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]563; CHECK-NEXT: selp.b32 [[R:%r[0-9]+]], -1, 0, [[PRED]];564; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];565; CHECK-NEXT: ret;566define i1 @test_fcmp_olt(half %a, half %b) #0 {567 %r = fcmp olt half %a, %b568 ret i1 %r569}570 571; XCHECK-LABEL: test_fcmp_ole(572; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_fcmp_ole_param_0];573; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_fcmp_ole_param_1];574; CHECK-F16-NOFTZ: setp.le.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]575; CHECK-F16-FTZ: setp.le.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]576; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%r[0-9]+]], [[A]];577; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%r[0-9]+]], [[B]];578; CHECK-NOF16: setp.le.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]579; CHECK-NEXT: selp.b32 [[R:%r[0-9]+]], -1, 0, [[PRED]];580; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];581; CHECK-NEXT: ret;582define i1 @test_fcmp_ole(half %a, half %b) #0 {583 %r = fcmp ole half %a, %b584 ret i1 %r585}586 587; CHECK-LABEL: test_fcmp_ord(588; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_fcmp_ord_param_0];589; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_fcmp_ord_param_1];590; CHECK-F16-NOFTZ: setp.num.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]591; CHECK-F16-FTZ: setp.num.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]592; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%r[0-9]+]], [[A]];593; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%r[0-9]+]], [[B]];594; CHECK-NOF16: setp.num.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]595; CHECK-NEXT: selp.b32 [[R:%r[0-9]+]], -1, 0, [[PRED]];596; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];597; CHECK-NEXT: ret;598define i1 @test_fcmp_ord(half %a, half %b) #0 {599 %r = fcmp ord half %a, %b600 ret i1 %r601}602 603; CHECK-LABEL: test_br_cc(604; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_br_cc_param_0];605; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_br_cc_param_1];606; CHECK-DAG: ld.param.b64 %[[C:rd[0-9]+]], [test_br_cc_param_2];607; CHECK-DAG: ld.param.b64 %[[D:rd[0-9]+]], [test_br_cc_param_3];608; CHECK-F16-NOFTZ: setp.lt.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]609; CHECK-F16-FTZ: setp.lt.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]610; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%r[0-9]+]], [[A]];611; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%r[0-9]+]], [[B]];612; CHECK-NOF16: setp.lt.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]613; CHECK-NEXT: @[[PRED]] bra [[LABEL:\$L__BB.*]];614; CHECK: st.b32 [%[[C]]],615; CHECK: [[LABEL]]:616; CHECK: st.b32 [%[[D]]],617; CHECK: ret;618define void @test_br_cc(half %a, half %b, ptr %p1, ptr %p2) #0 {619 %c = fcmp uge half %a, %b620 br i1 %c, label %then, label %else621then:622 store i32 0, ptr %p1623 ret void624else:625 store i32 0, ptr %p2626 ret void627}628 629; CHECK-LABEL: test_phi(630; CHECK: ld.param.b64 %[[P1:rd[0-9]+]], [test_phi_param_0];631; CHECK: ld.b16 {{%rs[0-9]+}}, [%[[P1]]];632; CHECK: [[LOOP:\$L__BB[0-9_]+]]:633; CHECK: mov.b16 [[R:%rs[0-9]+]], [[AB:%rs[0-9]+]];634; CHECK: ld.b16 [[AB:%rs[0-9]+]], [%[[P1]]];635; CHECK: {636; CHECK: st.param.b64 [param0], %[[P1]];637; CHECK: call.uni (retval0), test_dummy638; CHECK: }639; CHECK: setp.ne.b32 [[PRED:%p[0-9]+]], %r{{[0-9]+}}, 0;640; CHECK: @[[PRED]] bra [[LOOP]];641; CHECK: st.param.b16 [func_retval0], [[R]];642; CHECK: ret;643define half @test_phi(ptr %p1) #0 {644entry:645 %a = load half, ptr %p1646 br label %loop647loop:648 %r = phi half [%a, %entry], [%b, %loop]649 %b = load half, ptr %p1650 %c = call i1 @test_dummy(ptr %p1)651 br i1 %c, label %loop, label %return652return:653 ret half %r654}655declare i1 @test_dummy(ptr %p1) #0656 657; CHECK-LABEL: test_fptosi_i32(658; CHECK: ld.param.b16 [[A:%rs[0-9]+]], [test_fptosi_i32_param_0];659; CHECK: cvt.rzi.s32.f16 [[R:%r[0-9]+]], [[A]];660; CHECK: st.param.b32 [func_retval0], [[R]];661; CHECK: ret;662define i32 @test_fptosi_i32(half %a) #0 {663 %r = fptosi half %a to i32664 ret i32 %r665}666 667; CHECK-LABEL: test_fptosi_i64(668; CHECK: ld.param.b16 [[A:%rs[0-9]+]], [test_fptosi_i64_param_0];669; CHECK: cvt.rzi.s64.f16 [[R:%rd[0-9]+]], [[A]];670; CHECK: st.param.b64 [func_retval0], [[R]];671; CHECK: ret;672define i64 @test_fptosi_i64(half %a) #0 {673 %r = fptosi half %a to i64674 ret i64 %r675}676 677; CHECK-LABEL: test_fptoui_i32(678; CHECK: ld.param.b16 [[A:%rs[0-9]+]], [test_fptoui_i32_param_0];679; CHECK: cvt.rzi.u32.f16 [[R:%r[0-9]+]], [[A]];680; CHECK: st.param.b32 [func_retval0], [[R]];681; CHECK: ret;682define i32 @test_fptoui_i32(half %a) #0 {683 %r = fptoui half %a to i32684 ret i32 %r685}686 687; CHECK-LABEL: test_fptoui_i64(688; CHECK: ld.param.b16 [[A:%rs[0-9]+]], [test_fptoui_i64_param_0];689; CHECK: cvt.rzi.u64.f16 [[R:%rd[0-9]+]], [[A]];690; CHECK: st.param.b64 [func_retval0], [[R]];691; CHECK: ret;692define i64 @test_fptoui_i64(half %a) #0 {693 %r = fptoui half %a to i64694 ret i64 %r695}696 697; CHECK-LABEL: test_uitofp_i32(698; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_uitofp_i32_param_0];699; CHECK: cvt.rn.f16.u32 [[R:%rs[0-9]+]], [[A]];700; CHECK: st.param.b16 [func_retval0], [[R]];701; CHECK: ret;702define half @test_uitofp_i32(i32 %a) #0 {703 %r = uitofp i32 %a to half704 ret half %r705}706 707; CHECK-LABEL: test_uitofp_i64(708; CHECK: ld.param.b64 [[A:%rd[0-9]+]], [test_uitofp_i64_param_0];709; CHECK: cvt.rn.f16.u64 [[R:%rs[0-9]+]], [[A]];710; CHECK: st.param.b16 [func_retval0], [[R]];711; CHECK: ret;712define half @test_uitofp_i64(i64 %a) #0 {713 %r = uitofp i64 %a to half714 ret half %r715}716 717; CHECK-LABEL: test_sitofp_i32(718; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_sitofp_i32_param_0];719; CHECK: cvt.rn.f16.s32 [[R:%rs[0-9]+]], [[A]];720; CHECK: st.param.b16 [func_retval0], [[R]];721; CHECK: ret;722define half @test_sitofp_i32(i32 %a) #0 {723 %r = sitofp i32 %a to half724 ret half %r725}726 727; CHECK-LABEL: test_sitofp_i64(728; CHECK: ld.param.b64 [[A:%rd[0-9]+]], [test_sitofp_i64_param_0];729; CHECK: cvt.rn.f16.s64 [[R:%rs[0-9]+]], [[A]];730; CHECK: st.param.b16 [func_retval0], [[R]];731; CHECK: ret;732define half @test_sitofp_i64(i64 %a) #0 {733 %r = sitofp i64 %a to half734 ret half %r735}736 737; CHECK-LABEL: test_uitofp_i32_fadd(738; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_uitofp_i32_fadd_param_0];739; CHECK-DAG: cvt.rn.f16.u32 [[C:%rs[0-9]+]], [[A]];740; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_uitofp_i32_fadd_param_1];741; CHECK-F16-NOFTZ: add.rn.f16 [[R:%rs[0-9]+]], [[B]], [[C]];742; CHECK-F16-FTZ: add.rn.ftz.f16 [[R:%rs[0-9]+]], [[B]], [[C]];743; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%r[0-9]+]], [[B]]744; CHECK-NOF16-DAG: cvt.f32.f16 [[C32:%r[0-9]+]], [[C]]745; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%r[0-9]+]], [[B32]], [[C32]];746; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%rs[0-9]+]], [[R32]]747; CHECK: st.param.b16 [func_retval0], [[R]];748; CHECK: ret;749define half @test_uitofp_i32_fadd(i32 %a, half %b) #0 {750 %c = uitofp i32 %a to half751 %r = fadd half %b, %c752 ret half %r753}754 755; CHECK-LABEL: test_sitofp_i32_fadd(756; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_sitofp_i32_fadd_param_0];757; CHECK-DAG: cvt.rn.f16.s32 [[C:%rs[0-9]+]], [[A]];758; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_sitofp_i32_fadd_param_1];759; CHECK-F16-NOFTZ: add.rn.f16 [[R:%rs[0-9]+]], [[B]], [[C]];760; CHECK-F16-FTZ: add.rn.ftz.f16 [[R:%rs[0-9]+]], [[B]], [[C]];761; XCHECK-NOF16-DAG: cvt.f32.f16 [[B32:%r[0-9]+]], [[B]]762; XCHECK-NOF16-DAG: cvt.f32.f16 [[C32:%r[0-9]+]], [[C]]763; XCHECK-NOF16-NEXT: add.rn.f32 [[R32:%r[0-9]+]], [[B32]], [[C32]];764; XCHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%rs[0-9]+]], [[R32]]765; CHECK: st.param.b16 [func_retval0], [[R]];766; CHECK: ret;767define half @test_sitofp_i32_fadd(i32 %a, half %b) #0 {768 %c = sitofp i32 %a to half769 %r = fadd half %b, %c770 ret half %r771}772 773; CHECK-LABEL: test_fptrunc_float(774; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_fptrunc_float_param_0];775; CHECK: cvt.rn.f16.f32 [[R:%rs[0-9]+]], [[A]];776; CHECK: st.param.b16 [func_retval0], [[R]];777; CHECK: ret;778define half @test_fptrunc_float(float %a) #0 {779 %r = fptrunc float %a to half780 ret half %r781}782 783; CHECK-LABEL: test_fptrunc_double(784; CHECK: ld.param.b64 [[A:%rd[0-9]+]], [test_fptrunc_double_param_0];785; CHECK: cvt.rn.f16.f64 [[R:%rs[0-9]+]], [[A]];786; CHECK: st.param.b16 [func_retval0], [[R]];787; CHECK: ret;788define half @test_fptrunc_double(double %a) #0 {789 %r = fptrunc double %a to half790 ret half %r791}792 793; CHECK-LABEL: test_fpext_float(794; CHECK: ld.param.b16 [[A:%rs[0-9]+]], [test_fpext_float_param_0];795; CHECK-NOFTZ: cvt.f32.f16 [[R:%r[0-9]+]], [[A]];796; CHECK-F16-FTZ: cvt.ftz.f32.f16 [[R:%r[0-9]+]], [[A]];797; CHECK: st.param.b32 [func_retval0], [[R]];798; CHECK: ret;799define float @test_fpext_float(half %a) #0 {800 %r = fpext half %a to float801 ret float %r802}803 804; CHECK-LABEL: test_fpext_double(805; CHECK: ld.param.b16 [[A:%rs[0-9]+]], [test_fpext_double_param_0];806; CHECK: cvt.f64.f16 [[R:%rd[0-9]+]], [[A]];807; CHECK: st.param.b64 [func_retval0], [[R]];808; CHECK: ret;809define double @test_fpext_double(half %a) #0 {810 %r = fpext half %a to double811 ret double %r812}813 814 815; CHECK-LABEL: test_bitcast_halftoi16(816; CHECK: ld.param.b16 [[AH:%rs[0-9]+]], [test_bitcast_halftoi16_param_0];817; CHECK: cvt.u32.u16 [[R:%r[0-9]+]], [[AH]]818; CHECK: st.param.b32 [func_retval0], [[R]];819; CHECK: ret;820define i16 @test_bitcast_halftoi16(half %a) #0 {821 %r = bitcast half %a to i16822 ret i16 %r823}824 825; CHECK-LABEL: test_bitcast_i16tohalf(826; CHECK: ld.param.b16 [[AS:%rs[0-9]+]], [test_bitcast_i16tohalf_param_0];827; CHECK: st.param.b16 [func_retval0], [[AS]];828; CHECK: ret;829define half @test_bitcast_i16tohalf(i16 %a) #0 {830 %r = bitcast i16 %a to half831 ret half %r832}833 834 835declare half @llvm.sqrt.f16(half %a) #0836declare half @llvm.powi.f16.i32(half %a, i32 %b) #0837declare half @llvm.sin.f16(half %a) #0838declare half @llvm.cos.f16(half %a) #0839declare half @llvm.pow.f16(half %a, half %b) #0840declare half @llvm.exp.f16(half %a) #0841declare half @llvm.exp2.f16(half %a) #0842declare half @llvm.log.f16(half %a) #0843declare half @llvm.log10.f16(half %a) #0844declare half @llvm.log2.f16(half %a) #0845declare half @llvm.fma.f16(half %a, half %b, half %c) #0846declare half @llvm.fabs.f16(half %a) #0847declare half @llvm.minnum.f16(half %a, half %b) #0848declare half @llvm.maxnum.f16(half %a, half %b) #0849declare half @llvm.copysign.f16(half %a, half %b) #0850declare half @llvm.floor.f16(half %a) #0851declare half @llvm.ceil.f16(half %a) #0852declare half @llvm.trunc.f16(half %a) #0853declare half @llvm.rint.f16(half %a) #0854declare half @llvm.nearbyint.f16(half %a) #0855declare half @llvm.round.f16(half %a) #0856declare half @llvm.roundeven.f16(half %a) #0857declare half @llvm.fmuladd.f16(half %a, half %b, half %c) #0858 859; CHECK-LABEL: test_sqrt(860; CHECK: ld.param.b16 [[A:%rs[0-9]+]], [test_sqrt_param_0];861; CHECK-NOFTZ: cvt.f32.f16 [[AF:%r[0-9]+]], [[A]];862; CHECK-NOFTZ: sqrt.rn.f32 [[RF:%r[0-9]+]], [[AF]];863; CHECK-F16-FTZ: cvt.ftz.f32.f16 [[AF:%r[0-9]+]], [[A]];864; CHECK-F16-FTZ: sqrt.rn.ftz.f32 [[RF:%r[0-9]+]], [[AF]];865; CHECK: cvt.rn.f16.f32 [[R:%rs[0-9]+]], [[RF]];866; CHECK: st.param.b16 [func_retval0], [[R]];867; CHECK: ret;868define half @test_sqrt(half %a) #0 {869 %r = call half @llvm.sqrt.f16(half %a)870 ret half %r871}872 873;;; Can't do this yet: requires libcall.874; XCHECK-LABEL: test_powi(875;define half @test_powi(half %a, i32 %b) #0 {876; %r = call half @llvm.powi.f16.i32(half %a, i32 %b)877; ret half %r878;}879 880; CHECK-LABEL: test_sin(881; CHECK: ld.param.b16 [[A:%rs[0-9]+]], [test_sin_param_0];882; CHECK-NOFTZ: cvt.f32.f16 [[AF:%r[0-9]+]], [[A]];883; CHECK-F16-FTZ: cvt.ftz.f32.f16 [[AF:%r[0-9]+]], [[A]];884; CHECK-NOF16: sin.approx.f32 [[RF:%r[0-9]+]], [[AF]];885; CHECK-F16-FTZ: sin.approx.ftz.f32 [[RF:%r[0-9]+]], [[AF]];886; CHECK: cvt.rn.f16.f32 [[R:%rs[0-9]+]], [[RF]];887; CHECK: st.param.b16 [func_retval0], [[R]];888; CHECK: ret;889define half @test_sin(half %a) #0 {890 %r = call afn half @llvm.sin.f16(half %a)891 ret half %r892}893 894; CHECK-LABEL: test_cos(895; CHECK: ld.param.b16 [[A:%rs[0-9]+]], [test_cos_param_0];896; CHECK-NOFTZ: cvt.f32.f16 [[AF:%r[0-9]+]], [[A]];897; CHECK-F16-FTZ: cvt.ftz.f32.f16 [[AF:%r[0-9]+]], [[A]];898; CHECK-NOF16: cos.approx.f32 [[RF:%r[0-9]+]], [[AF]];899; CHECK-F16-FTZ: cos.approx.ftz.f32 [[RF:%r[0-9]+]], [[AF]];900; CHECK: cvt.rn.f16.f32 [[R:%rs[0-9]+]], [[RF]];901; CHECK: st.param.b16 [func_retval0], [[R]];902; CHECK: ret;903define half @test_cos(half %a) #0 {904 %r = call afn half @llvm.cos.f16(half %a)905 ret half %r906}907 908;;; Can't do this yet: requires libcall.909; XCHECK-LABEL: test_pow(910;define half @test_pow(half %a, half %b) #0 {911; %r = call half @llvm.pow.f16(half %a, half %b)912; ret half %r913;}914 915;;; Can't do this yet: requires libcall.916; XCHECK-LABEL: test_exp(917;define half @test_exp(half %a) #0 {918; %r = call half @llvm.exp.f16(half %a)919; ret half %r920;}921 922;;; Can't do this yet: requires libcall.923; XCHECK-LABEL: test_exp2(924;define half @test_exp2(half %a) #0 {925; %r = call half @llvm.exp2.f16(half %a)926; ret half %r927;}928 929;;; Can't do this yet: requires libcall.930; XCHECK-LABEL: test_log(931;define half @test_log(half %a) #0 {932; %r = call half @llvm.log.f16(half %a)933; ret half %r934;}935 936;;; Can't do this yet: requires libcall.937; XCHECK-LABEL: test_log10(938;define half @test_log10(half %a) #0 {939; %r = call half @llvm.log10.f16(half %a)940; ret half %r941;}942 943;;; Can't do this yet: requires libcall.944; XCHECK-LABEL: test_log2(945;define half @test_log2(half %a) #0 {946; %r = call half @llvm.log2.f16(half %a)947; ret half %r948;}949 950; CHECK-LABEL: test_fma(951; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_fma_param_0];952; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_fma_param_1];953; CHECK-DAG: ld.param.b16 [[C:%rs[0-9]+]], [test_fma_param_2];954; CHECK-F16-NOFTZ: fma.rn.f16 [[R:%rs[0-9]+]], [[A]], [[B]], [[C]];955; CHECK-F16-FTZ: fma.rn.ftz.f16 [[R:%rs[0-9]+]], [[A]], [[B]], [[C]];956; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%r[0-9]+]], [[A]]957; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%r[0-9]+]], [[B]]958; CHECK-NOF16-DAG: cvt.f32.f16 [[C32:%r[0-9]+]], [[C]]959; CHECK-NOF16-NEXT: fma.rn.f32 [[R32:%r[0-9]+]], [[A32]], [[B32]], [[C32]];960; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%rs[0-9]+]], [[R32]]961; CHECK: st.param.b16 [func_retval0], [[R]];962; CHECK: ret963define half @test_fma(half %a, half %b, half %c) #0 {964 %r = call half @llvm.fma.f16(half %a, half %b, half %c)965 ret half %r966}967 968; CHECK-LABEL: test_fabs(969; CHECK: ld.param.b16 [[A:%rs[0-9]+]], [test_fabs_param_0];970; CHECK-NOFTZ: cvt.f32.f16 [[AF:%r[0-9]+]], [[A]];971; CHECK-NOFTZ: abs.f32 [[RF:%r[0-9]+]], [[AF]];972; CHECK-F16-FTZ: cvt.ftz.f32.f16 [[AF:%r[0-9]+]], [[A]];973; CHECK-F16-FTZ: abs.ftz.f32 [[RF:%r[0-9]+]], [[AF]];974; CHECK: cvt.rn.f16.f32 [[R:%rs[0-9]+]], [[RF]];975; CHECK: st.param.b16 [func_retval0], [[R]];976; CHECK: ret;977define half @test_fabs(half %a) #0 {978 %r = call half @llvm.fabs.f16(half %a)979 ret half %r980}981 982; CHECK-LABEL: test_minnum(983; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_minnum_param_0];984; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_minnum_param_1];985; CHECK-NOFTZ-DAG: cvt.f32.f16 [[AF:%r[0-9]+]], [[A]];986; CHECK-NOFTZ-DAG: cvt.f32.f16 [[BF:%r[0-9]+]], [[B]];987; CHECK-NOFTZ: min.f32 [[RF:%r[0-9]+]], [[AF]], [[BF]];988; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[AF:%r[0-9]+]], [[A]];989; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[BF:%r[0-9]+]], [[B]];990; CHECK-F16-FTZ: min.ftz.f32 [[RF:%r[0-9]+]], [[AF]], [[BF]];991; CHECK: cvt.rn.f16.f32 [[R:%rs[0-9]+]], [[RF]];992; CHECK: st.param.b16 [func_retval0], [[R]];993; CHECK: ret;994define half @test_minnum(half %a, half %b) #0 {995 %r = call half @llvm.minnum.f16(half %a, half %b)996 ret half %r997}998 999; CHECK-LABEL: test_maxnum(1000; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_maxnum_param_0];1001; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_maxnum_param_1];1002; CHECK-NOFTZ-DAG: cvt.f32.f16 [[AF:%r[0-9]+]], [[A]];1003; CHECK-NOFTZ-DAG: cvt.f32.f16 [[BF:%r[0-9]+]], [[B]];1004; CHECK-NOFTZ: max.f32 [[RF:%r[0-9]+]], [[AF]], [[BF]];1005; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[AF:%r[0-9]+]], [[A]];1006; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[BF:%r[0-9]+]], [[B]];1007; CHECK-F16-FTZ: max.ftz.f32 [[RF:%r[0-9]+]], [[AF]], [[BF]];1008; CHECK: cvt.rn.f16.f32 [[R:%rs[0-9]+]], [[RF]];1009; CHECK: st.param.b16 [func_retval0], [[R]];1010; CHECK: ret;1011define half @test_maxnum(half %a, half %b) #0 {1012 %r = call half @llvm.maxnum.f16(half %a, half %b)1013 ret half %r1014}1015 1016; CHECK-LABEL: test_copysign(1017; CHECK-DAG: ld.param.b16 [[AH:%rs[0-9]+]], [test_copysign_param_0];1018; CHECK-DAG: ld.param.b16 [[BH:%rs[0-9]+]], [test_copysign_param_1];1019; CHECK-DAG: and.b16 [[AX:%rs[0-9]+]], [[AH]], 32767;1020; CHECK-DAG: and.b16 [[BX:%rs[0-9]+]], [[BH]], -32768;1021; CHECK: or.b16 [[RX:%rs[0-9]+]], [[AX]], [[BX]];1022; CHECK: st.param.b16 [func_retval0], [[RX]];1023; CHECK: ret;1024define half @test_copysign(half %a, half %b) #0 {1025 %r = call half @llvm.copysign.f16(half %a, half %b)1026 ret half %r1027}1028 1029; CHECK-LABEL: test_copysign_f32(1030; CHECK-DAG: ld.param.b16 [[AH:%rs[0-9]+]], [test_copysign_f32_param_0];1031; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_copysign_f32_param_1];1032; CHECK-DAG: and.b16 [[AX:%rs[0-9]+]], [[AH]], 32767;1033; CHECK-DAG: and.b32 [[BX0:%r[0-9]+]], [[B]], -2147483648;1034; CHECK-DAG: mov.b32 {tmp, [[BX2:%rs[0-9]+]]}, [[BX0]];1035; CHECK: or.b16 [[RX:%rs[0-9]+]], [[AX]], [[BX2]];1036; CHECK: st.param.b16 [func_retval0], [[RX]];1037; CHECK: ret;1038define half @test_copysign_f32(half %a, float %b) #0 {1039 %tb = fptrunc float %b to half1040 %r = call half @llvm.copysign.f16(half %a, half %tb)1041 ret half %r1042}1043 1044; CHECK-LABEL: test_copysign_f64(1045; CHECK-DAG: ld.param.b16 [[AH:%rs[0-9]+]], [test_copysign_f64_param_0];1046; CHECK-DAG: ld.param.b64 [[B:%rd[0-9]+]], [test_copysign_f64_param_1];1047; CHECK-DAG: and.b16 [[AX:%rs[0-9]+]], [[AH]], 32767;1048; CHECK-DAG: and.b64 [[BX0:%rd[0-9]+]], [[B]], -9223372036854775808;1049; CHECK-DAG: shr.u64 [[BX1:%rd[0-9]+]], [[BX0]], 48;1050; CHECK-DAG: cvt.u16.u64 [[BX2:%rs[0-9]+]], [[BX1]];1051; CHECK: or.b16 [[RX:%rs[0-9]+]], [[AX]], [[BX2]];1052; CHECK: st.param.b16 [func_retval0], [[RX]];1053; CHECK: ret;1054define half @test_copysign_f64(half %a, double %b) #0 {1055 %tb = fptrunc double %b to half1056 %r = call half @llvm.copysign.f16(half %a, half %tb)1057 ret half %r1058}1059 1060; CHECK-LABEL: test_copysign_extended(1061; CHECK-DAG: ld.param.b16 [[AH:%rs[0-9]+]], [test_copysign_extended_param_0];1062; CHECK-DAG: ld.param.b16 [[BH:%rs[0-9]+]], [test_copysign_extended_param_1];1063; CHECK-DAG: and.b16 [[AX:%rs[0-9]+]], [[AH]], 32767;1064; CHECK-DAG: and.b16 [[BX:%rs[0-9]+]], [[BH]], -32768;1065; CHECK: or.b16 [[RX:%rs[0-9]+]], [[AX]], [[BX]];1066; CHECK-NOFTZ: cvt.f32.f16 [[XR:%r[0-9]+]], [[RX]];1067; CHECK-F16-FTZ: cvt.ftz.f32.f16 [[XR:%r[0-9]+]], [[RX]];1068; CHECK: st.param.b32 [func_retval0], [[XR]];1069; CHECK: ret;1070define float @test_copysign_extended(half %a, half %b) #0 {1071 %r = call half @llvm.copysign.f16(half %a, half %b)1072 %xr = fpext half %r to float1073 ret float %xr1074}1075 1076; CHECK-LABEL: test_floor(1077; CHECK: ld.param.b16 [[A:%rs[0-9]+]], [test_floor_param_0];1078; CHECK: cvt.rmi.f16.f16 [[R:%rs[0-9]+]], [[A]];1079; CHECK: st.param.b16 [func_retval0], [[R]];1080; CHECK: ret;1081define half @test_floor(half %a) #0 {1082 %r = call half @llvm.floor.f16(half %a)1083 ret half %r1084}1085 1086; CHECK-LABEL: test_ceil(1087; CHECK: ld.param.b16 [[A:%rs[0-9]+]], [test_ceil_param_0];1088; CHECK: cvt.rpi.f16.f16 [[R:%rs[0-9]+]], [[A]];1089; CHECK: st.param.b16 [func_retval0], [[R]];1090; CHECK: ret;1091define half @test_ceil(half %a) #0 {1092 %r = call half @llvm.ceil.f16(half %a)1093 ret half %r1094}1095 1096; CHECK-LABEL: test_trunc(1097; CHECK: ld.param.b16 [[A:%rs[0-9]+]], [test_trunc_param_0];1098; CHECK: cvt.rzi.f16.f16 [[R:%rs[0-9]+]], [[A]];1099; CHECK: st.param.b16 [func_retval0], [[R]];1100; CHECK: ret;1101define half @test_trunc(half %a) #0 {1102 %r = call half @llvm.trunc.f16(half %a)1103 ret half %r1104}1105 1106; CHECK-LABEL: test_rint(1107; CHECK: ld.param.b16 [[A:%rs[0-9]+]], [test_rint_param_0];1108; CHECK: cvt.rni.f16.f16 [[R:%rs[0-9]+]], [[A]];1109; CHECK: st.param.b16 [func_retval0], [[R]];1110; CHECK: ret;1111define half @test_rint(half %a) #0 {1112 %r = call half @llvm.rint.f16(half %a)1113 ret half %r1114}1115 1116; CHECK-LABEL: test_nearbyint(1117; CHECK: ld.param.b16 [[A:%rs[0-9]+]], [test_nearbyint_param_0];1118; CHECK: cvt.rni.f16.f16 [[R:%rs[0-9]+]], [[A]];1119; CHECK: st.param.b16 [func_retval0], [[R]];1120; CHECK: ret;1121define half @test_nearbyint(half %a) #0 {1122 %r = call half @llvm.nearbyint.f16(half %a)1123 ret half %r1124}1125 1126; CHECK-LABEL: test_roundeven(1127; CHECK: ld.param.b16 [[A:%rs[0-9]+]], [test_roundeven_param_0];1128; CHECK: cvt.rni.f16.f16 [[R:%rs[0-9]+]], [[A]];1129; CHECK: st.param.b16 [func_retval0], [[R]];1130; CHECK: ret;1131define half @test_roundeven(half %a) #0 {1132 %r = call half @llvm.roundeven.f16(half %a)1133 ret half %r1134}1135 1136; CHECK-LABEL: test_round(1137; CHECK: ld.param.b16 {{.*}}, [test_round_param_0];1138; check the use of sign mask and 0.5 to implement round1139; CHECK: and.b32 [[R:%r[0-9]+]], {{.*}}, -2147483648;1140; CHECK: or.b32 {{.*}}, [[R]], 1056964608;1141; CHECK: st.param.b16 [func_retval0], {{.*}};1142; CHECK: ret;1143define half @test_round(half %a) #0 {1144 %r = call half @llvm.round.f16(half %a)1145 ret half %r1146}1147 1148; CHECK-LABEL: test_fmuladd(1149; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_fmuladd_param_0];1150; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_fmuladd_param_1];1151; CHECK-DAG: ld.param.b16 [[C:%rs[0-9]+]], [test_fmuladd_param_2];1152; CHECK-F16-NOFTZ: fma.rn.f16 [[R:%rs[0-9]+]], [[A]], [[B]], [[C]];1153; CHECK-F16-FTZ: fma.rn.ftz.f16 [[R:%rs[0-9]+]], [[A]], [[B]], [[C]];1154; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%r[0-9]+]], [[A]]1155; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%r[0-9]+]], [[B]]1156; CHECK-NOF16-DAG: cvt.f32.f16 [[C32:%r[0-9]+]], [[C]]1157; CHECK-NOF16-NEXT: fma.rn.f32 [[R32:%r[0-9]+]], [[A32]], [[B32]], [[C32]];1158; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%rs[0-9]+]], [[R32]]1159; CHECK: st.param.b16 [func_retval0], [[R]];1160; CHECK: ret;1161define half @test_fmuladd(half %a, half %b, half %c) #0 {1162 %r = call half @llvm.fmuladd.f16(half %a, half %b, half %c)1163 ret half %r1164}1165 1166; CHECK-LABEL: test_neg_f16(1167; CHECK-F16-NOFTZ: neg.f161168; CHECK-F16-FTZ: neg.ftz.f161169; CHECK-NOF16: xor.b16 %rs{{.*}}, %rs{{.*}}, -327681170define half @test_neg_f16(half noundef %arg) #0 {1171 %res = fneg half %arg1172 ret half %res1173}1174 1175; CHECK-LABEL: test_neg_f16x2(1176; CHECK-F16-NOFTZ: neg.f16x21177; CHECK-F16-FTZ: neg.ftz.f16x21178; CHECK-NOF16: xor.b16 %rs{{.*}}, %rs{{.*}}, -327681179; CHECK-NOF16: xor.b16 %rs{{.*}}, %rs{{.*}}, -327681180define <2 x half> @test_neg_f16x2(<2 x half> noundef %arg) #0 {1181 %res = fneg <2 x half> %arg1182 ret <2 x half> %res1183}1184 1185attributes #0 = { nounwind }1186