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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt < %s -passes=nvptx-lower-args,infer-alignment -S | FileCheck %s3 4target triple = "nvptx64-nvidia-cuda"5 6; ------------------------------------------------------------------------------7; Test that alignment can be inferred through llvm.nvvm.internal.addrspace.wrap.p101.p0 intrinsics8; thanks to the alignment attribute on the intrinsic9; ------------------------------------------------------------------------------10 11%struct.S1 = type { i32, i32, i32, i32 }12define ptx_kernel i32 @test_align8(ptr noundef readonly byval(%struct.S1) align 8 captures(none) %params) {13; CHECK-LABEL: define ptx_kernel i32 @test_align8(14; CHECK-SAME: ptr noundef readonly byval([[STRUCT_S1:%.*]]) align 8 captures(none) [[PARAMS:%.*]]) {15; CHECK-NEXT: [[ENTRY:.*:]]16; CHECK-NEXT: [[TMP0:%.*]] = call align 8 ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[PARAMS]])17; CHECK-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(101) [[TMP0]], align 818; CHECK-NEXT: ret i32 [[LOAD]]19;20entry:21 %load = load i32, ptr %params, align 422 ret i32 %load23}24 25define ptx_kernel i32 @test_align1(ptr noundef readonly byval(%struct.S1) align 1 captures(none) %params) {26; CHECK-LABEL: define ptx_kernel i32 @test_align1(27; CHECK-SAME: ptr noundef readonly byval([[STRUCT_S1:%.*]]) align 4 captures(none) [[PARAMS:%.*]]) {28; CHECK-NEXT: [[ENTRY:.*:]]29; CHECK-NEXT: [[TMP0:%.*]] = call align 1 ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[PARAMS]])30; CHECK-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(101) [[TMP0]], align 431; CHECK-NEXT: ret i32 [[LOAD]]32;33entry:34 %load = load i32, ptr %params, align 435 ret i32 %load36}37