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1; We run nvvm-reflect (and then optimize) this module twice, once with metadata2; that enables FTZ, and again with metadata that disables it.3 4; RUN: cat %s > %t.noftz5; RUN: echo '!0 = !{i32 4, !"nvvm-reflect-ftz", i32 0}' >> %t.noftz6; RUN: opt %t.noftz -S -mtriple=nvptx-nvidia-cuda -passes='nvvm-reflect,simplifycfg' \7; RUN: | FileCheck %s --check-prefix=USE_FTZ_0 --check-prefix=CHECK8 9; RUN: cat %s > %t.ftz10; RUN: echo '!0 = !{i32 4, !"nvvm-reflect-ftz", i32 1}' >> %t.ftz11; RUN: opt %t.ftz -S -mtriple=nvptx-nvidia-cuda -passes='nvvm-reflect,simplifycfg' \12; RUN: | FileCheck %s --check-prefix=USE_FTZ_1 --check-prefix=CHECK13 14@str = private unnamed_addr addrspace(4) constant [11 x i8] c"__CUDA_FTZ\00"15 16declare i32 @__nvvm_reflect(ptr)17declare ptr @llvm.nvvm.ptr.constant.to.gen.p0.p4(ptr addrspace(4))18 19; CHECK-LABEL: @foo20define float @foo(float %a, float %b) {21; CHECK-NOT: call i32 @__nvvm_reflect22 %ptr = tail call ptr @llvm.nvvm.ptr.constant.to.gen.p0.p4(ptr addrspace(4) @str)23 %reflect = tail call i32 @__nvvm_reflect(ptr %ptr)24 %cmp = icmp ugt i32 %reflect, 025 br i1 %cmp, label %use_mul, label %use_add26 27use_mul:28; USE_FTZ_1: fmul float %a, %b29; USE_FTZ_0-NOT: fadd float %a, %b30 %ret1 = fmul float %a, %b31 br label %exit32 33use_add:34; USE_FTZ_0: fadd float %a, %b35; USE_FTZ_1-NOT: fmul float %a, %b36 %ret2 = fadd float %a, %b37 br label %exit38 39exit:40 %ret = phi float [%ret1, %use_mul], [%ret2, %use_add]41 ret float %ret42}43 44declare i32 @llvm.nvvm.reflect(ptr)45 46; CHECK-LABEL: define i32 @intrinsic47define i32 @intrinsic() {48; CHECK-NOT: call i32 @llvm.nvvm.reflect49; USE_FTZ_0: ret i32 050; USE_FTZ_1: ret i32 151 %ptr = tail call ptr @llvm.nvvm.ptr.constant.to.gen.p0.p4(ptr addrspace(4) @str)52 %reflect = tail call i32 @llvm.nvvm.reflect(ptr %ptr)53 ret i32 %reflect54}55 56; CUDA-7.0 passes __nvvm_reflect argument slightly differently.57; Verify that it works, too58 59@"$str" = private addrspace(1) constant [11 x i8] c"__CUDA_FTZ\00"60 61; CHECK-LABEL: @bar62define float @bar(float %a, float %b) {63; CHECK-NOT: call i32 @__nvvm_reflect64 %reflect = call i32 @__nvvm_reflect(ptr addrspacecast (ptr addrspace(1) @"$str" to ptr))65 %cmp = icmp ne i32 %reflect, 066 br i1 %cmp, label %use_mul, label %use_add67 68use_mul:69; USE_FTZ_1: fmul float %a, %b70; USE_FTZ_0-NOT: fadd float %a, %b71 %ret1 = fmul float %a, %b72 br label %exit73 74use_add:75; USE_FTZ_0: fadd float %a, %b76; USE_FTZ_1-NOT: fmul float %a, %b77 %ret2 = fadd float %a, %b78 br label %exit79 80exit:81 %ret = phi float [%ret1, %use_mul], [%ret2, %use_add]82 ret float %ret83}84 85@str0 = private constant [11 x i8] c"__CUDA_FTZ\00"86 87; CHECK-LABEL: @baz88define float @baz(float %a, float %b) {89; CHECK-NOT: call i32 @__nvvm_reflect90 %reflect = call i32 @__nvvm_reflect(ptr @str0)91 %cmp = icmp ne i32 %reflect, 092 br i1 %cmp, label %use_mul, label %use_add93 94use_mul:95; USE_FTZ_1: fmul float %a, %b96; USE_FTZ_0-NOT: fadd float %a, %b97 %ret1 = fmul float %a, %b98 br label %exit99 100use_add:101; USE_FTZ_0: fadd float %a, %b102; USE_FTZ_1-NOT: fmul float %a, %b103 %ret2 = fadd float %a, %b104 br label %exit105 106exit:107 %ret = phi float [%ret1, %use_mul], [%ret2, %use_add]108 ret float %ret109}110 111!llvm.module.flags = !{!0}112; A module flag is added to the end of this file by the RUN lines at the top.113