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1; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_20 | FileCheck %s2; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mcpu=sm_20 | %ptxas-verify %}3 4target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"5target triple = "nvptx64-nvidia-cuda"6 7; Function Attrs: nounwind8; CHECK: .func kernelgen_memcpy9define ptx_device void @kernelgen_memcpy(ptr nocapture %dst) #0 {10entry:11 br i1 undef, label %for.end, label %vector.body12 13vector.body: ; preds = %vector.body, %entry14 %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ]15 %scevgep9 = getelementptr i8, ptr %dst, i64 %index16 store <4 x i8> undef, ptr %scevgep9, align 117 %index.next = add i64 %index, 418 %0 = icmp eq i64 undef, %index.next19 br i1 %0, label %middle.block, label %vector.body20 21middle.block: ; preds = %vector.body22 br i1 undef, label %for.end, label %for.body.preheader123 24for.body.preheader1: ; preds = %middle.block25 br label %for.body26 27for.body: ; preds = %for.body, %for.body.preheader128 %lsr.iv3 = phi ptr [ %dst, %for.body.preheader1 ], [ %scevgep4, %for.body ]29 store i8 undef, ptr %lsr.iv3, align 130 %scevgep4 = getelementptr i8, ptr %lsr.iv3, i64 131 br label %for.body32 33for.end: ; preds = %middle.block, %entry34 ret void35}36 37attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }38