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1; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_30 | FileCheck %s2; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mcpu=sm_30 | %ptxas-verify %}3 4declare i32 @llvm.nvvm.shfl.down.i32(i32, i32, i32)5declare float @llvm.nvvm.shfl.down.f32(float, i32, i32)6declare i32 @llvm.nvvm.shfl.up.i32(i32, i32, i32)7declare float @llvm.nvvm.shfl.up.f32(float, i32, i32)8declare i32 @llvm.nvvm.shfl.bfly.i32(i32, i32, i32)9declare float @llvm.nvvm.shfl.bfly.f32(float, i32, i32)10declare i32 @llvm.nvvm.shfl.idx.i32(i32, i32, i32)11declare float @llvm.nvvm.shfl.idx.f32(float, i32, i32)12 13; Try all four permutations of register and immediate parameters with14; shfl.down.15 16; CHECK-LABEL: .func{{.*}}shfl_down117define i32 @shfl_down1(i32 %in) {18 ; CHECK: ld.param.b32 [[IN:%r[0-9]+]]19 ; CHECK: shfl.down.b32 [[OUT:%r[0-9]+]], [[IN]], 1, 2;20 ; CHECK: st.param.{{.}}32 {{.*}}, [[OUT]]21 %val = call i32 @llvm.nvvm.shfl.down.i32(i32 %in, i32 1, i32 2)22 ret i32 %val23}24 25; CHECK-LABEL: .func{{.*}}shfl_down226define i32 @shfl_down2(i32 %in, i32 %width) {27 ; CHECK: ld.param.b32 [[IN1:%r[0-9]+]]28 ; CHECK: ld.param.b32 [[IN2:%r[0-9]+]]29 ; CHECK: shfl.down.{{.}}32 %r{{[0-9]+}}, [[IN1]], [[IN2]], 3;30 %val = call i32 @llvm.nvvm.shfl.down.i32(i32 %in, i32 %width, i32 3)31 ret i32 %val32}33 34; CHECK-LABEL: .func{{.*}}shfl_down335define i32 @shfl_down3(i32 %in, i32 %mask) {36 ; CHECK: ld.param.b32 [[IN1:%r[0-9]+]]37 ; CHECK: ld.param.b32 [[IN2:%r[0-9]+]]38 ; CHECK: shfl.down.{{.}}32 %r{{[0-9]+}}, [[IN1]], 4, [[IN2]];39 %val = call i32 @llvm.nvvm.shfl.down.i32(i32 %in, i32 4, i32 %mask)40 ret i32 %val41}42 43; CHECK-LABEL: .func{{.*}}shfl_down444define i32 @shfl_down4(i32 %in, i32 %width, i32 %mask) {45 ; CHECK: ld.param.b32 [[IN1:%r[0-9]+]]46 ; CHECK: ld.param.b32 [[IN2:%r[0-9]+]]47 ; CHECK: ld.param.b32 [[IN3:%r[0-9]+]]48 ; CHECK: shfl.down.{{.}}32 %r{{[0-9]+}}, [[IN1]], [[IN2]], [[IN3]];49 %val = call i32 @llvm.nvvm.shfl.down.i32(i32 %in, i32 %width, i32 %mask)50 ret i32 %val51}52 53; Try shfl.down with floating-point params.54; CHECK-LABEL: .func{{.*}}shfl_down_float55define float @shfl_down_float(float %in) {56 ; CHECK: ld.param.b32 [[IN:%r[0-9]+]]57 ; CHECK: shfl.down.b32 [[OUT:%r[0-9]+]], [[IN]], 5, 6;58 ; CHECK: st.param.{{.}}32 {{.*}}, [[OUT]]59 %out = call float @llvm.nvvm.shfl.down.f32(float %in, i32 5, i32 6)60 ret float %out61}62 63; Try the rest of the shfl modes. Hopefully they're declared in such a way64; that if shfl.down works correctly, they also work correctly.65define void @shfl_rest(i32 %in_i32, float %in_float, ptr %out_i32, ptr %out_float) {66 ; CHECK: shfl.up.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, 1, 2;67 %up_i32 = call i32 @llvm.nvvm.shfl.up.i32(i32 %in_i32, i32 1, i32 2)68 store i32 %up_i32, ptr %out_i3269 70 ; CHECK: shfl.up.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, 3, 4;71 %up_float = call float @llvm.nvvm.shfl.up.f32(float %in_float, i32 3, i32 4)72 store float %up_float, ptr %out_float73 74 ; CHECK: shfl.bfly.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, 5, 6;75 %bfly_i32 = call i32 @llvm.nvvm.shfl.bfly.i32(i32 %in_i32, i32 5, i32 6)76 store i32 %bfly_i32, ptr %out_i3277 78 ; CHECK: shfl.bfly.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, 7, 8;79 %bfly_float = call float @llvm.nvvm.shfl.bfly.f32(float %in_float, i32 7, i32 8)80 store float %bfly_float, ptr %out_float81 82 ; CHECK: shfl.idx.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, 9, 10;83 %idx_i32 = call i32 @llvm.nvvm.shfl.idx.i32(i32 %in_i32, i32 9, i32 10)84 store i32 %idx_i32, ptr %out_i3285 86 ; CHECK: shfl.idx.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, 11, 12;87 %idx_float = call float @llvm.nvvm.shfl.idx.f32(float %in_float, i32 11, i32 12)88 store float %idx_float, ptr %out_float89 90 ret void91}92