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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_20 | FileCheck %s3; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mcpu=sm_20 | %ptxas-verify %}4 5define void @foo1(<2 x float> %val, ptr %ptr) {6; CHECK-LABEL: foo1(7; CHECK: {8; CHECK-NEXT: .reg .b32 %r<3>;9; CHECK-NEXT: .reg .b64 %rd<2>;10; CHECK-EMPTY:11; CHECK-NEXT: // %bb.0:12; CHECK-NEXT: ld.param.v2.b32 {%r1, %r2}, [foo1_param_0];13; CHECK-NEXT: ld.param.b64 %rd1, [foo1_param_1];14; CHECK-NEXT: st.v2.b32 [%rd1], {%r1, %r2};15; CHECK-NEXT: ret;16 store <2 x float> %val, ptr %ptr17 ret void18}19 20define void @foo2(<4 x float> %val, ptr %ptr) {21; CHECK-LABEL: foo2(22; CHECK: {23; CHECK-NEXT: .reg .b32 %r<5>;24; CHECK-NEXT: .reg .b64 %rd<2>;25; CHECK-EMPTY:26; CHECK-NEXT: // %bb.0:27; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [foo2_param_0];28; CHECK-NEXT: ld.param.b64 %rd1, [foo2_param_1];29; CHECK-NEXT: st.v4.b32 [%rd1], {%r1, %r2, %r3, %r4};30; CHECK-NEXT: ret;31 store <4 x float> %val, ptr %ptr32 ret void33}34 35define void @foo3(<2 x i32> %val, ptr %ptr) {36; CHECK-LABEL: foo3(37; CHECK: {38; CHECK-NEXT: .reg .b32 %r<3>;39; CHECK-NEXT: .reg .b64 %rd<2>;40; CHECK-EMPTY:41; CHECK-NEXT: // %bb.0:42; CHECK-NEXT: ld.param.v2.b32 {%r1, %r2}, [foo3_param_0];43; CHECK-NEXT: ld.param.b64 %rd1, [foo3_param_1];44; CHECK-NEXT: st.v2.b32 [%rd1], {%r1, %r2};45; CHECK-NEXT: ret;46 store <2 x i32> %val, ptr %ptr47 ret void48}49 50define void @foo4(<4 x i32> %val, ptr %ptr) {51; CHECK-LABEL: foo4(52; CHECK: {53; CHECK-NEXT: .reg .b32 %r<5>;54; CHECK-NEXT: .reg .b64 %rd<2>;55; CHECK-EMPTY:56; CHECK-NEXT: // %bb.0:57; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [foo4_param_0];58; CHECK-NEXT: ld.param.b64 %rd1, [foo4_param_1];59; CHECK-NEXT: st.v4.b32 [%rd1], {%r1, %r2, %r3, %r4};60; CHECK-NEXT: ret;61 store <4 x i32> %val, ptr %ptr62 ret void63}64 65define void @v16i8(ptr %a, ptr %b) {66; CHECK-LABEL: v16i8(67; CHECK: {68; CHECK-NEXT: .reg .b32 %r<5>;69; CHECK-NEXT: .reg .b64 %rd<3>;70; CHECK-EMPTY:71; CHECK-NEXT: // %bb.0:72; CHECK-NEXT: ld.param.b64 %rd1, [v16i8_param_0];73; CHECK-NEXT: ld.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];74; CHECK-NEXT: ld.param.b64 %rd2, [v16i8_param_1];75; CHECK-NEXT: st.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};76; CHECK-NEXT: ret;77 %v = load <16 x i8>, ptr %a78 store <16 x i8> %v, ptr %b79 ret void80}81