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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -global-isel -o - \3; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s4 5;; Note that SETUEQ, SETOGE, SETOLE, SETONE, SETULT and SETUGT should be6;; expanded by DAG legalizer for floating-point types f32 and f64, so there are7;; no patterns defined in PPCInstrInfo.td file for these setcc patterns for now.8 9define i1 @fcmp_false(float %a, float %b) {10; CHECK-LABEL: fcmp_false:11; CHECK: # %bb.0:12; CHECK-NEXT: li r3, 013; CHECK-NEXT: blr14 %cmp = fcmp false float %a, %b15 ret i1 %cmp16}17 18define i1 @fcmp_oeq(float %a, float %b) {19; CHECK-LABEL: fcmp_oeq:20; CHECK: # %bb.0:21; CHECK-NEXT: fcmpu cr0, f1, f222; CHECK-NEXT: li r3, 023; CHECK-NEXT: li r4, 124; CHECK-NEXT: iseleq r3, r4, r325; CHECK-NEXT: blr26 %cmp = fcmp oeq float %a, %b27 ret i1 %cmp28}29 30define i1 @fcmp_ogt(float %a, float %b) {31; CHECK-LABEL: fcmp_ogt:32; CHECK: # %bb.0:33; CHECK-NEXT: fcmpu cr0, f1, f234; CHECK-NEXT: li r3, 035; CHECK-NEXT: li r4, 136; CHECK-NEXT: iselgt r3, r4, r337; CHECK-NEXT: blr38 %cmp = fcmp ogt float %a, %b39 ret i1 %cmp40}41 42define i1 @fcmp_olt(float %a, float %b) {43; CHECK-LABEL: fcmp_olt:44; CHECK: # %bb.0:45; CHECK-NEXT: fcmpu cr0, f1, f246; CHECK-NEXT: li r3, 047; CHECK-NEXT: li r4, 148; CHECK-NEXT: isellt r3, r4, r349; CHECK-NEXT: blr50 %cmp = fcmp olt float %a, %b51 ret i1 %cmp52}53 54define i1 @fcmp_ord(float %a, float %b) {55; CHECK-LABEL: fcmp_ord:56; CHECK: # %bb.0:57; CHECK-NEXT: fcmpu cr0, f1, f258; CHECK-NEXT: li r3, 059; CHECK-NEXT: li r4, 160; CHECK-NEXT: crnot 4*cr5+lt, un61; CHECK-NEXT: isel r3, r4, r3, 4*cr5+lt62; CHECK-NEXT: blr63 %cmp = fcmp ord float %a, %b64 ret i1 %cmp65}66 67define i1 @fcmp_uge(float %a, float %b) {68; CHECK-LABEL: fcmp_uge:69; CHECK: # %bb.0:70; CHECK-NEXT: fcmpu cr0, f1, f271; CHECK-NEXT: li r3, 072; CHECK-NEXT: li r4, 173; CHECK-NEXT: crnot 4*cr5+lt, lt74; CHECK-NEXT: isel r3, r4, r3, 4*cr5+lt75; CHECK-NEXT: blr76 %cmp = fcmp uge float %a, %b77 ret i1 %cmp78}79 80define i1 @fcmp_ule(float %a, float %b) {81; CHECK-LABEL: fcmp_ule:82; CHECK: # %bb.0:83; CHECK-NEXT: fcmpu cr0, f1, f284; CHECK-NEXT: li r3, 085; CHECK-NEXT: li r4, 186; CHECK-NEXT: crnot 4*cr5+lt, gt87; CHECK-NEXT: isel r3, r4, r3, 4*cr5+lt88; CHECK-NEXT: blr89 %cmp = fcmp ule float %a, %b90 ret i1 %cmp91}92 93define i1 @fcmp_une(float %a, float %b) {94; CHECK-LABEL: fcmp_une:95; CHECK: # %bb.0:96; CHECK-NEXT: fcmpu cr0, f1, f297; CHECK-NEXT: li r3, 098; CHECK-NEXT: li r4, 199; CHECK-NEXT: crnot 4*cr5+lt, eq100; CHECK-NEXT: isel r3, r4, r3, 4*cr5+lt101; CHECK-NEXT: blr102 %cmp = fcmp une float %a, %b103 ret i1 %cmp104}105 106define i1 @fcmp_uno(float %a, float %b) {107; CHECK-LABEL: fcmp_uno:108; CHECK: # %bb.0:109; CHECK-NEXT: fcmpu cr0, f1, f2110; CHECK-NEXT: li r3, 0111; CHECK-NEXT: li r4, 1112; CHECK-NEXT: isel r3, r4, r3, un113; CHECK-NEXT: blr114 %cmp = fcmp uno float %a, %b115 ret i1 %cmp116}117 118define i1 @fcmp_true(float %a, float %b) {119; CHECK-LABEL: fcmp_true:120; CHECK: # %bb.0:121; CHECK-NEXT: li r3, 1122; CHECK-NEXT: blr123 %cmp = fcmp true float %a, %b124 ret i1 %cmp125}126 127define i1 @fcmp_false_double(double %a, double %b) {128; CHECK-LABEL: fcmp_false_double:129; CHECK: # %bb.0:130; CHECK-NEXT: li r3, 0131; CHECK-NEXT: blr132 %cmp = fcmp false double %a, %b133 ret i1 %cmp134}135 136define i1 @fcmp_oeq_double(double %a, double %b) {137; CHECK-LABEL: fcmp_oeq_double:138; CHECK: # %bb.0:139; CHECK-NEXT: fcmpu cr0, f1, f2140; CHECK-NEXT: li r3, 0141; CHECK-NEXT: li r4, 1142; CHECK-NEXT: iseleq r3, r4, r3143; CHECK-NEXT: blr144 %cmp = fcmp oeq double %a, %b145 ret i1 %cmp146}147 148define i1 @fcmp_ogt_double(double %a, double %b) {149; CHECK-LABEL: fcmp_ogt_double:150; CHECK: # %bb.0:151; CHECK-NEXT: fcmpu cr0, f1, f2152; CHECK-NEXT: li r3, 0153; CHECK-NEXT: li r4, 1154; CHECK-NEXT: iselgt r3, r4, r3155; CHECK-NEXT: blr156 %cmp = fcmp ogt double %a, %b157 ret i1 %cmp158}159 160define i1 @fcmp_olt_double(double %a, double %b) {161; CHECK-LABEL: fcmp_olt_double:162; CHECK: # %bb.0:163; CHECK-NEXT: fcmpu cr0, f1, f2164; CHECK-NEXT: li r3, 0165; CHECK-NEXT: li r4, 1166; CHECK-NEXT: isellt r3, r4, r3167; CHECK-NEXT: blr168 %cmp = fcmp olt double %a, %b169 ret i1 %cmp170}171 172define i1 @fcmp_ord_double(double %a, double %b) {173; CHECK-LABEL: fcmp_ord_double:174; CHECK: # %bb.0:175; CHECK-NEXT: fcmpu cr0, f1, f2176; CHECK-NEXT: li r3, 0177; CHECK-NEXT: li r4, 1178; CHECK-NEXT: crnot 4*cr5+lt, un179; CHECK-NEXT: isel r3, r4, r3, 4*cr5+lt180; CHECK-NEXT: blr181 %cmp = fcmp ord double %a, %b182 ret i1 %cmp183}184 185define i1 @fcmp_uge_double(double %a, double %b) {186; CHECK-LABEL: fcmp_uge_double:187; CHECK: # %bb.0:188; CHECK-NEXT: fcmpu cr0, f1, f2189; CHECK-NEXT: li r3, 0190; CHECK-NEXT: li r4, 1191; CHECK-NEXT: crnot 4*cr5+lt, lt192; CHECK-NEXT: isel r3, r4, r3, 4*cr5+lt193; CHECK-NEXT: blr194 %cmp = fcmp uge double %a, %b195 ret i1 %cmp196}197 198define i1 @fcmp_ule_double(double %a, double %b) {199; CHECK-LABEL: fcmp_ule_double:200; CHECK: # %bb.0:201; CHECK-NEXT: fcmpu cr0, f1, f2202; CHECK-NEXT: li r3, 0203; CHECK-NEXT: li r4, 1204; CHECK-NEXT: crnot 4*cr5+lt, gt205; CHECK-NEXT: isel r3, r4, r3, 4*cr5+lt206; CHECK-NEXT: blr207 %cmp = fcmp ule double %a, %b208 ret i1 %cmp209}210 211define i1 @fcmp_une_double(double %a, double %b) {212; CHECK-LABEL: fcmp_une_double:213; CHECK: # %bb.0:214; CHECK-NEXT: fcmpu cr0, f1, f2215; CHECK-NEXT: li r3, 0216; CHECK-NEXT: li r4, 1217; CHECK-NEXT: crnot 4*cr5+lt, eq218; CHECK-NEXT: isel r3, r4, r3, 4*cr5+lt219; CHECK-NEXT: blr220 %cmp = fcmp une double %a, %b221 ret i1 %cmp222}223 224define i1 @fcmp_uno_double(double %a, double %b) {225; CHECK-LABEL: fcmp_uno_double:226; CHECK: # %bb.0:227; CHECK-NEXT: fcmpu cr0, f1, f2228; CHECK-NEXT: li r3, 0229; CHECK-NEXT: li r4, 1230; CHECK-NEXT: isel r3, r4, r3, un231; CHECK-NEXT: blr232 %cmp = fcmp uno double %a, %b233 ret i1 %cmp234}235 236define i1 @fcmp_true_double(double %a, double %b) {237; CHECK-LABEL: fcmp_true_double:238; CHECK: # %bb.0:239; CHECK-NEXT: li r3, 1240; CHECK-NEXT: blr241 %cmp = fcmp true double %a, %b242 ret i1 %cmp243}244