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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -global-isel -o - \3; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s4 5define float @float_add(float %a, float %b) {6; CHECK-LABEL: float_add:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: xsaddsp f1, f1, f29; CHECK-NEXT: blr10entry:11 %add = fadd float %a, %b12 ret float %add13}14 15define double @double_add(double %a, double %b) {16; CHECK-LABEL: double_add:17; CHECK: # %bb.0: # %entry18; CHECK-NEXT: xsadddp f1, f1, f219; CHECK-NEXT: blr20entry:21 %add = fadd double %a, %b22 ret double %add23}24 25define float @float_sub(float %a, float %b) {26; CHECK-LABEL: float_sub:27; CHECK: # %bb.0: # %entry28; CHECK-NEXT: xssubsp f1, f1, f229; CHECK-NEXT: blr30entry:31 %sub = fsub float %a, %b32 ret float %sub33}34 35define float @float_mul(float %a, float %b) {36; CHECK-LABEL: float_mul:37; CHECK: # %bb.0: # %entry38; CHECK-NEXT: xsmulsp f1, f1, f239; CHECK-NEXT: blr40entry:41 %mul = fmul float %a, %b42 ret float %mul43}44 45define float @float_div(float %a, float %b) {46; CHECK-LABEL: float_div:47; CHECK: # %bb.0: # %entry48; CHECK-NEXT: xsdivsp f1, f1, f249; CHECK-NEXT: blr50entry:51 %div = fdiv float %a, %b52 ret float %div53}54 55define <4 x float> @test_fadd_v4f32(<4 x float> %a, <4 x float> %b) {56; CHECK-LABEL: test_fadd_v4f32:57; CHECK: # %bb.0:58; CHECK-NEXT: xvaddsp v2, v2, v359; CHECK-NEXT: blr60 %res = fadd <4 x float> %a, %b61 ret <4 x float> %res62}63 64define <2 x double> @test_fadd_v2f64(<2 x double> %a, <2 x double> %b) {65; CHECK-LABEL: test_fadd_v2f64:66; CHECK: # %bb.0:67; CHECK-NEXT: xvadddp v2, v2, v368; CHECK-NEXT: blr69 %res = fadd <2 x double> %a, %b70 ret <2 x double> %res71}72 73define <4 x float> @test_fsub_v4f32(<4 x float> %a, <4 x float> %b) {74; CHECK-LABEL: test_fsub_v4f32:75; CHECK: # %bb.0:76; CHECK-NEXT: xvsubsp v2, v2, v377; CHECK-NEXT: blr78 %res = fsub <4 x float> %a, %b79 ret <4 x float> %res80}81 82define <2 x double> @test_fsub_v2f64(<2 x double> %a, <2 x double> %b) {83; CHECK-LABEL: test_fsub_v2f64:84; CHECK: # %bb.0:85; CHECK-NEXT: xvsubdp v2, v2, v386; CHECK-NEXT: blr87 %res = fsub <2 x double> %a, %b88 ret <2 x double> %res89}90 91define <4 x float> @test_fmul_v4f32(<4 x float> %a, <4 x float> %b) {92; CHECK-LABEL: test_fmul_v4f32:93; CHECK: # %bb.0:94; CHECK-NEXT: xvmulsp v2, v2, v395; CHECK-NEXT: blr96 %res = fmul <4 x float> %a, %b97 ret <4 x float> %res98}99 100define <2 x double> @test_fmul_v2f64(<2 x double> %a, <2 x double> %b) {101; CHECK-LABEL: test_fmul_v2f64:102; CHECK: # %bb.0:103; CHECK-NEXT: xvmuldp v2, v2, v3104; CHECK-NEXT: blr105 %res = fmul <2 x double> %a, %b106 ret <2 x double> %res107}108 109define <4 x float> @test_fdiv_v4f32(<4 x float> %a, <4 x float> %b) {110; CHECK-LABEL: test_fdiv_v4f32:111; CHECK: # %bb.0:112; CHECK-NEXT: xvdivsp v2, v2, v3113; CHECK-NEXT: blr114 %res = fdiv <4 x float> %a, %b115 ret <4 x float> %res116}117 118define <2 x double> @test_fdiv_v2f64(<2 x double> %a, <2 x double> %b) {119; CHECK-LABEL: test_fdiv_v2f64:120; CHECK: # %bb.0:121; CHECK-NEXT: xvdivdp v2, v2, v3122; CHECK-NEXT: blr123 %res = fdiv <2 x double> %a, %b124 ret <2 x double> %res125}126