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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -global-isel \3; RUN: -verify-machineinstrs -stop-after=irtranslator < %s | FileCheck %s4 5; Pass up to twelve vector arguments in registers.6define void @test_vec1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d, <4 x i32> %e, <4 x i32> %f, <4 x i32> %g, <4 x i32> %h, <4 x i32> %i, <4 x i32> %j, <4 x i32> %k, <4 x i32> %l) {7 ; CHECK-LABEL: name: test_vec18 ; CHECK: bb.1.entry:9 ; CHECK-NEXT: liveins: $v2, $v3, $v4, $v5, $v6, $v7, $v8, $v9, $v10, $v11, $v12, $v1310 ; CHECK-NEXT: {{ $}}11 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $v212 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $v313 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $v414 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $v515 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<4 x s32>) = COPY $v616 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<4 x s32>) = COPY $v717 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<4 x s32>) = COPY $v818 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<4 x s32>) = COPY $v919 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(<4 x s32>) = COPY $v1020 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(<4 x s32>) = COPY $v1121 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(<4 x s32>) = COPY $v1222 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(<4 x s32>) = COPY $v1323 ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm24entry:25 ret void26}27 28define void @test_vec2(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i64> %d, <2 x i64> %e, <2 x i64> %f, <2 x i64> %g, <2 x i64> %h, <2 x i64> %i, <2 x i64> %j, <2 x i64> %k, <2 x i64> %l) {29 ; CHECK-LABEL: name: test_vec230 ; CHECK: bb.1.entry:31 ; CHECK-NEXT: liveins: $v2, $v3, $v4, $v5, $v6, $v7, $v8, $v9, $v10, $v11, $v12, $v1332 ; CHECK-NEXT: {{ $}}33 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $v234 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $v335 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $v436 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $v537 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<2 x s64>) = COPY $v638 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<2 x s64>) = COPY $v739 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<2 x s64>) = COPY $v840 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<2 x s64>) = COPY $v941 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(<2 x s64>) = COPY $v1042 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(<2 x s64>) = COPY $v1143 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(<2 x s64>) = COPY $v1244 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(<2 x s64>) = COPY $v1345 ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm46entry:47 ret void48}49 50define void @test_vec3(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d, <8 x i16> %e, <8 x i16> %f, <8 x i16> %g, <8 x i16> %h, <8 x i16> %i, <8 x i16> %j, <8 x i16> %k, <8 x i16> %l) {51 ; CHECK-LABEL: name: test_vec352 ; CHECK: bb.1.entry:53 ; CHECK-NEXT: liveins: $v2, $v3, $v4, $v5, $v6, $v7, $v8, $v9, $v10, $v11, $v12, $v1354 ; CHECK-NEXT: {{ $}}55 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $v256 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $v357 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<8 x s16>) = COPY $v458 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<8 x s16>) = COPY $v559 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<8 x s16>) = COPY $v660 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<8 x s16>) = COPY $v761 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<8 x s16>) = COPY $v862 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<8 x s16>) = COPY $v963 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(<8 x s16>) = COPY $v1064 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(<8 x s16>) = COPY $v1165 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(<8 x s16>) = COPY $v1266 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(<8 x s16>) = COPY $v1367 ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm68entry:69 ret void70}71 72define void @test_vec4(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d, <16 x i8> %e, <16 x i8> %f, <16 x i8> %g, <16 x i8> %h, <16 x i8> %i, <16 x i8> %j, <16 x i8> %k, <16 x i8> %l) {73 ; CHECK-LABEL: name: test_vec474 ; CHECK: bb.1.entry:75 ; CHECK-NEXT: liveins: $v2, $v3, $v4, $v5, $v6, $v7, $v8, $v9, $v10, $v11, $v12, $v1376 ; CHECK-NEXT: {{ $}}77 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $v278 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $v379 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY $v480 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<16 x s8>) = COPY $v581 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<16 x s8>) = COPY $v682 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<16 x s8>) = COPY $v783 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<16 x s8>) = COPY $v884 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<16 x s8>) = COPY $v985 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(<16 x s8>) = COPY $v1086 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(<16 x s8>) = COPY $v1187 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(<16 x s8>) = COPY $v1288 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(<16 x s8>) = COPY $v1389 ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm90entry:91 ret void92}93 94define void @test_vec5(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, <4 x float> %e, <4 x float> %f, <4 x float> %g, <4 x float> %h, <4 x float> %i, <4 x float> %j, <4 x float> %k, <4 x float> %l) {95 ; CHECK-LABEL: name: test_vec596 ; CHECK: bb.1.entry:97 ; CHECK-NEXT: liveins: $v2, $v3, $v4, $v5, $v6, $v7, $v8, $v9, $v10, $v11, $v12, $v1398 ; CHECK-NEXT: {{ $}}99 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $v2100 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $v3101 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $v4102 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $v5103 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<4 x s32>) = COPY $v6104 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<4 x s32>) = COPY $v7105 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<4 x s32>) = COPY $v8106 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<4 x s32>) = COPY $v9107 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(<4 x s32>) = COPY $v10108 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(<4 x s32>) = COPY $v11109 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(<4 x s32>) = COPY $v12110 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(<4 x s32>) = COPY $v13111 ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm112entry:113 ret void114}115 116define void @test_vec6(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d, <2 x double> %e, <2 x double> %f, <2 x double> %g, <2 x double> %h, <2 x double> %i, <2 x double> %j, <2 x double> %k, <2 x double> %l) {117 ; CHECK-LABEL: name: test_vec6118 ; CHECK: bb.1.entry:119 ; CHECK-NEXT: liveins: $v2, $v3, $v4, $v5, $v6, $v7, $v8, $v9, $v10, $v11, $v12, $v13120 ; CHECK-NEXT: {{ $}}121 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $v2122 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $v3123 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $v4124 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $v5125 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<2 x s64>) = COPY $v6126 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<2 x s64>) = COPY $v7127 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<2 x s64>) = COPY $v8128 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<2 x s64>) = COPY $v9129 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(<2 x s64>) = COPY $v10130 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(<2 x s64>) = COPY $v11131 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(<2 x s64>) = COPY $v12132 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(<2 x s64>) = COPY $v13133 ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm134entry:135 ret void136}137 138define void @test_vec7(<1 x i128> %a, <1 x i128> %b, <1 x i128> %c, <1 x i128> %d, <1 x i128> %e, <1 x i128> %f, <1 x i128> %g, <1 x i128> %h, <1 x i128> %i, <1 x i128> %j, <1 x i128> %k, <1 x i128> %l) {139 ; CHECK-LABEL: name: test_vec7140 ; CHECK: bb.1.entry:141 ; CHECK-NEXT: liveins: $v2, $v3, $v4, $v5, $v6, $v7, $v8, $v9, $v10, $v11, $v12, $v13142 ; CHECK-NEXT: {{ $}}143 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $v2144 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s128) = COPY $v3145 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY $v4146 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s128) = COPY $v5147 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s128) = COPY $v6148 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s128) = COPY $v7149 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s128) = COPY $v8150 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s128) = COPY $v9151 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(s128) = COPY $v10152 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s128) = COPY $v11153 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(s128) = COPY $v12154 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(s128) = COPY $v13155 ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm156entry:157 ret void158}159 160