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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -global-isel -o - \3; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs < %s | FileCheck %s4 5define i64 @load_i64(ptr %p) {6; CHECK-LABEL: load_i64:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: ld r3, 0(r3)9; CHECK-NEXT: blr10entry:11 %ret = load i64, ptr %p, align 812 ret i64 %ret13}14 15define i64 @load2_i64(ptr %p, i64 %a) {16; CHECK-LABEL: load2_i64:17; CHECK: # %bb.0: # %entry18; CHECK-NEXT: ld r3, 0(r3)19; CHECK-NEXT: add r3, r3, r420; CHECK-NEXT: blr21entry:22 %load = load i64, ptr %p, align 823 %ret = add i64 %load, %a24 ret i64 %ret25}26 27define float @load3_i64(ptr %p) {28; CHECK-LABEL: load3_i64:29; CHECK: # %bb.0: # %entry30; CHECK-NEXT: ld r3, 0(r3)31; CHECK-NEXT: mtfprd f0, r332; CHECK-NEXT: xscvsxdsp f1, f033; CHECK-NEXT: blr34entry:35 %load = load i64, ptr %p, align 836 %ret = sitofp i64 %load to float37 ret float %ret38}39 40define double @load4_i64(ptr %p) {41; CHECK-LABEL: load4_i64:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: ld r3, 0(r3)44; CHECK-NEXT: mtfprd f0, r345; CHECK-NEXT: xscvsxddp f1, f046; CHECK-NEXT: blr47entry:48 %load = load i64, ptr %p, align 849 %ret = sitofp i64 %load to double50 ret double %ret51}52 53define float @load5_i64(ptr %p) {54; CHECK-LABEL: load5_i64:55; CHECK: # %bb.0: # %entry56; CHECK-NEXT: ld r3, 0(r3)57; CHECK-NEXT: mtfprd f0, r358; CHECK-NEXT: xscvuxdsp f1, f059; CHECK-NEXT: blr60entry:61 %load = load i64, ptr %p, align 862 %ret = uitofp i64 %load to float63 ret float %ret64}65 66define double @load6_i64(ptr %p) {67; CHECK-LABEL: load6_i64:68; CHECK: # %bb.0: # %entry69; CHECK-NEXT: ld r3, 0(r3)70; CHECK-NEXT: mtfprd f0, r371; CHECK-NEXT: xscvuxddp f1, f072; CHECK-NEXT: blr73entry:74 %load = load i64, ptr %p, align 875 %ret = uitofp i64 %load to double76 ret double %ret77}78 79define double @load_f64(ptr %p) {80; CHECK-LABEL: load_f64:81; CHECK: # %bb.0: # %entry82; CHECK-NEXT: lfd f1, 0(r3)83; CHECK-NEXT: blr84entry:85 %ret = load double, ptr %p, align 886 ret double %ret87}88 89define double @load2_f64(ptr %p, double %a) {90; CHECK-LABEL: load2_f64:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: lfd f0, 0(r3)93; CHECK-NEXT: xsadddp f1, f0, f194; CHECK-NEXT: blr95entry:96 %load = load double, ptr %p, align 897 %ret = fadd double %load, %a98 ret double %ret99}100 101define i64 @load3_f64(ptr %p) {102; CHECK-LABEL: load3_f64:103; CHECK: # %bb.0: # %entry104; CHECK-NEXT: lfd f0, 0(r3)105; CHECK-NEXT: xscvdpsxds f0, f0106; CHECK-NEXT: mffprd r3, f0107; CHECK-NEXT: blr108entry:109 %load = load double, ptr %p, align 8110 %ret = fptosi double %load to i64111 ret i64 %ret112}113 114define i64 @load4_f64(ptr %p) {115; CHECK-LABEL: load4_f64:116; CHECK: # %bb.0: # %entry117; CHECK-NEXT: lfd f0, 0(r3)118; CHECK-NEXT: xscvdpuxds f0, f0119; CHECK-NEXT: mffprd r3, f0120; CHECK-NEXT: blr121entry:122 %load = load double, ptr %p, align 8123 %ret = fptoui double %load to i64124 ret i64 %ret125}126 127define void @store_i64(ptr %p) {128; CHECK-LABEL: store_i64:129; CHECK: # %bb.0: # %entry130; CHECK-NEXT: li r4, 100131; CHECK-NEXT: std r4, 0(r3)132; CHECK-NEXT: blr133entry:134 store i64 100, ptr %p, align 8135 ret void136}137 138define void @store2_i64(ptr %p, i64 %a, i64 %b) {139; CHECK-LABEL: store2_i64:140; CHECK: # %bb.0: # %entry141; CHECK-NEXT: add r4, r4, r5142; CHECK-NEXT: std r4, 0(r3)143; CHECK-NEXT: blr144entry:145 %add = add i64 %a, %b146 store i64 %add, ptr %p, align 8147 ret void148}149 150define void @store3_i64(ptr %p, float %a) {151; CHECK-LABEL: store3_i64:152; CHECK: # %bb.0: # %entry153; CHECK-NEXT: xscvdpsxds f0, f1154; CHECK-NEXT: mffprd r4, f0155; CHECK-NEXT: std r4, 0(r3)156; CHECK-NEXT: blr157entry:158 %conv = fptosi float %a to i64159 store i64 %conv, ptr %p, align 8160 ret void161}162 163define void @store4_i64(ptr %p, double %a) {164; CHECK-LABEL: store4_i64:165; CHECK: # %bb.0: # %entry166; CHECK-NEXT: xscvdpsxds f0, f1167; CHECK-NEXT: mffprd r4, f0168; CHECK-NEXT: std r4, 0(r3)169; CHECK-NEXT: blr170entry:171 %conv = fptosi double %a to i64172 store i64 %conv, ptr %p, align 8173 ret void174}175 176define void @store5_i64(ptr %p, float %a) {177; CHECK-LABEL: store5_i64:178; CHECK: # %bb.0: # %entry179; CHECK-NEXT: xscvdpuxds f0, f1180; CHECK-NEXT: mffprd r4, f0181; CHECK-NEXT: std r4, 0(r3)182; CHECK-NEXT: blr183entry:184 %conv = fptoui float %a to i64185 store i64 %conv, ptr %p, align 8186 ret void187}188 189define void @store6_i64(ptr %p, double %a) {190; CHECK-LABEL: store6_i64:191; CHECK: # %bb.0: # %entry192; CHECK-NEXT: xscvdpuxds f0, f1193; CHECK-NEXT: mffprd r4, f0194; CHECK-NEXT: std r4, 0(r3)195; CHECK-NEXT: blr196entry:197 %conv = fptoui double %a to i64198 store i64 %conv, ptr %p, align 8199 ret void200}201 202define void @store_f64(ptr %p, double %a) {203; CHECK-LABEL: store_f64:204; CHECK: # %bb.0: # %entry205; CHECK-NEXT: stfd f1, 0(r3)206; CHECK-NEXT: blr207entry:208 store double %a, ptr %p, align 8209 ret void210}211 212define void @store2_f64(ptr %p, double %a, double %b) {213; CHECK-LABEL: store2_f64:214; CHECK: # %bb.0: # %entry215; CHECK-NEXT: xsadddp f0, f1, f2216; CHECK-NEXT: stfd f0, 0(r3)217; CHECK-NEXT: blr218entry:219 %fadd = fadd double %a, %b220 store double %fadd, ptr %p, align 8221 ret void222}223 224define void @store3_f64(ptr %p, i64 %a) {225; CHECK-LABEL: store3_f64:226; CHECK: # %bb.0: # %entry227; CHECK-NEXT: mtfprd f0, r4228; CHECK-NEXT: xscvsxddp f0, f0229; CHECK-NEXT: stfd f0, 0(r3)230; CHECK-NEXT: blr231entry:232 %conv = sitofp i64 %a to double233 store double %conv, ptr %p, align 8234 ret void235}236 237define void @store4_f64(ptr %p, i64 %a) {238; CHECK-LABEL: store4_f64:239; CHECK: # %bb.0: # %entry240; CHECK-NEXT: mtfprd f0, r4241; CHECK-NEXT: xscvuxddp f0, f0242; CHECK-NEXT: stfd f0, 0(r3)243; CHECK-NEXT: blr244entry:245 %conv = uitofp i64 %a to double246 store double %conv, ptr %p, align 8247 ret void248}249