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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple ppc64le-linux -ppc-asm-full-reg-names -global-isel -o - < %s \3; RUN: | FileCheck %s4 5; Function Attrs: nounwind readnone6define i64 @cn15bit1() #0 {7; CHECK-LABEL: cn15bit1:8; CHECK: # %bb.0: # %entry9; CHECK-NEXT: li r3, 3276710; CHECK-NEXT: blr11entry:12 ret i64 3276713 14}15 16; Function Attrs: nounwind readnone17define i64 @cn15bit2() #0 {18; CHECK-LABEL: cn15bit2:19; CHECK: # %bb.0: # %entry20; CHECK-NEXT: li r3, -3276721; CHECK-NEXT: blr22entry:23 ret i64 -3276724 25}26 27 28; Function Attrs: nounwind readnone29define i64 @cn1() #0 {30; CHECK-LABEL: cn1:31; CHECK: # %bb.0: # %entry32; CHECK-NEXT: li r3, -133; CHECK-NEXT: rldic r3, r3, 0, 1634; CHECK-NEXT: blr35entry:36 ret i64 28147497671065537 38}39 40; Function Attrs: nounwind readnone41define i64 @cnb() #0 {42; CHECK-LABEL: cnb:43; CHECK: # %bb.0: # %entry44; CHECK-NEXT: li r3, -8145; CHECK-NEXT: rldic r3, r3, 0, 1646; CHECK-NEXT: blr47entry:48 ret i64 28147497671057549 50}51 52; Function Attrs: nounwind readnone53define i64 @f2(i64 %x) #0 {54; CHECK-LABEL: f2:55; CHECK: # %bb.0: # %entry56; CHECK-NEXT: li r3, -157; CHECK-NEXT: rldic r3, r3, 36, 058; CHECK-NEXT: blr59entry:60 ret i64 -6871947673661 62}63 64; Function Attrs: nounwind readnone65define i64 @f2a(i64 %x) #0 {66; CHECK-LABEL: f2a:67; CHECK: # %bb.0: # %entry68; CHECK-NEXT: li r3, -33769; CHECK-NEXT: rldic r3, r3, 30, 070; CHECK-NEXT: blr71entry:72 ret i64 -36185099468873 74}75 76; Function Attrs: nounwind readnone77define i64 @f2n(i64 %x) #0 {78; CHECK-LABEL: f2n:79; CHECK: # %bb.0: # %entry80; CHECK-NEXT: li r3, -181; CHECK-NEXT: rldic r3, r3, 0, 2882; CHECK-NEXT: blr83entry:84 ret i64 6871947673585 86}87 88; Function Attrs: nounwind readnone89define i64 @f3(i64 %x) #0 {90; CHECK-LABEL: f3:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: li r3, -193; CHECK-NEXT: rldic r3, r3, 0, 3194; CHECK-NEXT: blr95entry:96 ret i64 858993459197 98}99 100; Function Attrs: nounwind readnone101define i64 @cn2n() #0 {102; CHECK-LABEL: cn2n:103; CHECK: # %bb.0: # %entry104; CHECK-NEXT: lis r3, -5121105; CHECK-NEXT: ori r3, r3, 65534106; CHECK-NEXT: rotldi r3, r3, 22107; CHECK-NEXT: blr108entry:109 ret i64 -1407374887747585110 111}112 113define i64 @uint32_1() #0 {114; CHECK-LABEL: uint32_1:115; CHECK: # %bb.0: # %entry116; CHECK-NEXT: li r3, 18176117; CHECK-NEXT: oris r3, r3, 59509118; CHECK-NEXT: blr119entry:120 ret i64 3900000000121 122}123 124define i32 @uint32_1_i32() #0 {125; CHECK-LABEL: uint32_1_i32:126; CHECK: # %bb.0: # %entry127; CHECK-NEXT: lis r3, -6027128; CHECK-NEXT: ori r3, r3, 18176129; CHECK-NEXT: blr130entry:131 ret i32 -394967296132 133}134 135define i64 @uint32_2() #0 {136; CHECK-LABEL: uint32_2:137; CHECK: # %bb.0: # %entry138; CHECK-NEXT: li r3, -1139; CHECK-NEXT: rldic r3, r3, 0, 32140; CHECK-NEXT: blr141entry:142 ret i64 4294967295143 144}145 146define i32 @uint32_2_i32() #0 {147; CHECK-LABEL: uint32_2_i32:148; CHECK: # %bb.0: # %entry149; CHECK-NEXT: li r3, -1150; CHECK-NEXT: blr151entry:152 ret i32 -1153 154}155 156define i64 @uint32_3() #0 {157; CHECK-LABEL: uint32_3:158; CHECK: # %bb.0: # %entry159; CHECK-NEXT: li r3, 1160; CHECK-NEXT: rldic r3, r3, 31, 32161; CHECK-NEXT: blr162entry:163 ret i64 2147483648164 165}166 167define i64 @uint32_4() #0 {168; CHECK-LABEL: uint32_4:169; CHECK: # %bb.0: # %entry170; CHECK-NEXT: lis r3, -6027171; CHECK-NEXT: ori r3, r3, 18177172; CHECK-NEXT: rldic r3, r3, 5, 27173; CHECK-NEXT: blr174entry:175 ret i64 124800000032176 177}178 179define i64 @cn_ones_1() #0 {180; CHECK-LABEL: cn_ones_1:181; CHECK: # %bb.0: # %entry182; CHECK-NEXT: li r3, -25633183; CHECK-NEXT: rldicl r3, r3, 18, 30184; CHECK-NEXT: blr185entry:186 ret i64 10460594175187 188}189 190define i64 @cn_ones_2() #0 {191; CHECK-LABEL: cn_ones_2:192; CHECK: # %bb.0: # %entry193; CHECK-NEXT: lis r3, -25638194; CHECK-NEXT: ori r3, r3, 24575195; CHECK-NEXT: rldicl r3, r3, 2, 30196; CHECK-NEXT: blr197entry:198 ret i64 10459119615199 200}201 202define i64 @imm1() #0 {203; CHECK-LABEL: imm1:204; CHECK: # %bb.0: # %entry205; CHECK-NEXT: li r3, 8465206; CHECK-NEXT: rldic r3, r3, 28, 22207; CHECK-NEXT: blr208entry:209 ret i64 2272306135040 ;0x21110000000210}211 212define i64 @imm2() #0 {213; CHECK-LABEL: imm2:214; CHECK: # %bb.0: # %entry215; CHECK-NEXT: li r3, -28536216; CHECK-NEXT: rldicl r3, r3, 1, 32217; CHECK-NEXT: blr218entry:219 ret i64 4294910225 ;0xFFFF2111220}221 222define i64 @imm3() #0 {223; CHECK-LABEL: imm3:224; CHECK: # %bb.0: # %entry225; CHECK-NEXT: li r3, -32495226; CHECK-NEXT: rldic r3, r3, 0, 32227; CHECK-NEXT: blr228entry:229 ret i64 4294934801 ;0xFFFF8111230}231 232define i64 @imm4() #0 {233; CHECK-LABEL: imm4:234; CHECK: # %bb.0: # %entry235; CHECK-NEXT: lis r3, 33236; CHECK-NEXT: ori r3, r3, 4352237; CHECK-NEXT: rldimi r3, r3, 32, 0238; CHECK-NEXT: blr239entry:240 ret i64 9307365931290880 ;0x21110000211100241}242 243define i64 @imm5() #0 {244; CHECK-LABEL: imm5:245; CHECK: # %bb.0: # %entry246; CHECK-NEXT: li r3, 28685247; CHECK-NEXT: rotldi r3, r3, 52248; CHECK-NEXT: blr249entry:250 ret i64 58546795155816455 ;0xd0000000000007251}252 253define i64 @imm6() #0 {254; CHECK-LABEL: imm6:255; CHECK: # %bb.0: # %entry256; CHECK-NEXT: lis r3, -1257; CHECK-NEXT: ori r3, r3, 28674258; CHECK-NEXT: rotldi r3, r3, 52259; CHECK-NEXT: blr260entry:261 ret i64 13510798882111479 ;0x2ffffffffffff7262}263 264define i64 @imm7() #0 {265; CHECK-LABEL: imm7:266; CHECK: # %bb.0: # %entry267; CHECK-NEXT: li r3, -3823268; CHECK-NEXT: rldic r3, r3, 28, 20269; CHECK-NEXT: blr270entry:271 ret i64 16565957296128 ;0xf1110000000272}273 274define i64 @imm8() #0 {275; CHECK-LABEL: imm8:276; CHECK: # %bb.0: # %entry277; CHECK-NEXT: li r3, -7919278; CHECK-NEXT: rldic r3, r3, 22, 22279; CHECK-NEXT: blr280entry:281 ret i64 4364831817728 ;0x3f844400000282}283 284define i64 @imm9() #0 {285; CHECK-LABEL: imm9:286; CHECK: # %bb.0: # %entry287; CHECK-NEXT: lis r3, -1288; CHECK-NEXT: ori r3, r3, 28674289; CHECK-NEXT: rotldi r3, r3, 52290; CHECK-NEXT: blr291entry:292 ret i64 13510798882111479 ;0x2ffffffffffff7293}294 295define i64 @imm10() #0 {296; CHECK-LABEL: imm10:297; CHECK: # %bb.0: # %entry298; CHECK-NEXT: li r3, -3823299; CHECK-NEXT: rldic r3, r3, 28, 20300; CHECK-NEXT: blr301entry:302 ret i64 16565957296128 ;0xf1110000000303}304 305define i64 @imm11() #0 {306; CHECK-LABEL: imm11:307; CHECK: # %bb.0: # %entry308; CHECK-NEXT: li r3, -7919309; CHECK-NEXT: rldic r3, r3, 22, 22310; CHECK-NEXT: blr311entry:312 ret i64 4364831817728 ;0x3f844400000313}314 315define i64 @imm12() #0 {316; CHECK-LABEL: imm12:317; CHECK: # %bb.0: # %entry318; CHECK-NEXT: lis r3, -29319; CHECK-NEXT: ori r3, r3, 64577320; CHECK-NEXT: rldic r3, r3, 12, 20321; CHECK-NEXT: blr322entry:323 ret i64 17584665923584 ;0xffe3fc41000324}325 326define i64 @imm13() #0 {327; CHECK-LABEL: imm13:328; CHECK: # %bb.0: # %entry329; CHECK-NEXT: li r3, -24847330; CHECK-NEXT: rldicl r3, r3, 21, 27331; CHECK-NEXT: blr332entry:333 ret i64 85333114879 ;0x13de3fffff334}335 336define i64 @imm13_2() #0 {337; CHECK-LABEL: imm13_2:338; CHECK: # %bb.0: # %entry339; CHECK-NEXT: li r3, -12424340; CHECK-NEXT: rldicl r3, r3, 22, 26341; CHECK-NEXT: blr342entry:343 ret i64 222772068351 ;0x33de3fffff344}345 346define i64 @imm14() #0 {347; CHECK-LABEL: imm14:348; CHECK: # %bb.0: # %entry349; CHECK-NEXT: li r3, -3960350; CHECK-NEXT: rldicl r3, r3, 21, 24351; CHECK-NEXT: blr352entry:353 ret i64 1091209003007 ;0xfe111fffff354}355 356define i64 @imm15() #0 {357; CHECK-LABEL: imm15:358; CHECK: # %bb.0: # %entry359; CHECK-NEXT: li r3, -8065360; CHECK-NEXT: rldic r3, r3, 24, 0361; CHECK-NEXT: blr362entry:363 ret i64 -135308247040364}365 366define i64 @imm16() #0 {367; CHECK-LABEL: imm16:368; CHECK: # %bb.0: # %entry369; CHECK-NEXT: lis r3, -16392370; CHECK-NEXT: ori r3, r3, 57217371; CHECK-NEXT: rldic r3, r3, 16, 0372; CHECK-NEXT: blr373entry:374 ret i64 -70399354142720375}376 377define i64 @imm17() #0 {378; CHECK-LABEL: imm17:379; CHECK: # %bb.0: # %entry380; CHECK-NEXT: lis r3, 20344381; CHECK-NEXT: ori r3, r3, 32847382; CHECK-NEXT: rotldi r3, r3, 49383; CHECK-NEXT: blr384entry:385 ret i64 44473046320324337 ;0x9e000000009ef1386}387 388define i64 @imm18() #0 {389; CHECK-LABEL: imm18:390; CHECK: # %bb.0: # %entry391; CHECK-NEXT: li r3, 1392; CHECK-NEXT: rldic r3, r3, 33, 30393; CHECK-NEXT: oris r3, r3, 39436394; CHECK-NEXT: ori r3, r3, 61633395; CHECK-NEXT: blr396entry:397 ret i64 11174473921398}399 400attributes #0 = { nounwind readnone }401