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1; RUN: llc --debugify-and-strip-all-safe=0 -mtriple=powerpc64-- -O3 \2; RUN: -debug-pass=Structure < %s -o /dev/null 2>&1 | \3; RUN: grep -v "Verify generated machine code" | FileCheck %s4 5; REQUIRES: asserts6; CHECK-LABEL: Pass Arguments:7; CHECK-NEXT: Target Library Information8; CHECK-NEXT: Target Pass Configuration9; CHECK-NEXT: Machine Module Information10; CHECK-NEXT: Target Transform Information11; CHECK-NEXT: Assumption Cache Tracker12; CHECK-NEXT: Type-Based Alias Analysis13; CHECK-NEXT: Scoped NoAlias Alias Analysis14; CHECK-NEXT: Profile summary info15; CHECK-NEXT: Create Garbage Collector Module Metadata16; CHECK-NEXT: Machine Branch Probability Analysis17; CHECK-NEXT: Default Regalloc Eviction Advisor18; CHECK-NEXT: Default Regalloc Priority Advisor19; CHECK-NEXT: ModulePass Manager20; CHECK-NEXT: Pre-ISel Intrinsic Lowering21; CHECK-NEXT: FunctionPass Manager22; CHECK-NEXT: Expand large div/rem23; CHECK-NEXT: Expand fp24; CHECK-NEXT: Convert i1 constants to i32/i64 if they are returned25; CHECK-NEXT: Expand Atomic instructions26; CHECK-NEXT: PPC Lower MASS Entries27; CHECK-NEXT: FunctionPass Manager28; CHECK-NEXT: Dominator Tree Construction29; CHECK-NEXT: Natural Loop Information30; CHECK-NEXT: Split GEPs to a variadic base and a constant offset for better CSE31; CHECK-NEXT: Early CSE32; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)33; CHECK-NEXT: Function Alias Analysis Results34; CHECK-NEXT: Memory SSA35; CHECK-NEXT: Canonicalize natural loops36; CHECK-NEXT: LCSSA Verifier37; CHECK-NEXT: Loop-Closed SSA Form Pass38; CHECK-NEXT: Scalar Evolution Analysis39; CHECK-NEXT: Lazy Branch Probability Analysis40; CHECK-NEXT: Lazy Block Frequency Analysis41; CHECK-NEXT: Loop Pass Manager42; CHECK-NEXT: Loop Invariant Code Motion43; CHECK-NEXT: Module Verifier44; CHECK-NEXT: Loop Pass Manager45; CHECK-NEXT: Canonicalize Freeze Instructions in Loops46; CHECK-NEXT: Induction Variable Users47; CHECK-NEXT: Loop Strength Reduction48; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)49; CHECK-NEXT: Function Alias Analysis Results50; CHECK-NEXT: Merge contiguous icmps into a memcmp51; CHECK-NEXT: Natural Loop Information52; CHECK-NEXT: Lazy Branch Probability Analysis53; CHECK-NEXT: Lazy Block Frequency Analysis54; CHECK-NEXT: Expand memcmp() to load/stores55; CHECK-NEXT: Lower Garbage Collection Instructions56; CHECK-NEXT: Shadow Stack GC Lowering57; CHECK-NEXT: Remove unreachable blocks from the CFG58; CHECK-NEXT: Natural Loop Information59; CHECK-NEXT: Post-Dominator Tree Construction60; CHECK-NEXT: Branch Probability Analysis61; CHECK-NEXT: Block Frequency Analysis62; CHECK-NEXT: Constant Hoisting63; CHECK-NEXT: Replace intrinsics with calls to vector library64; CHECK-NEXT: Lazy Branch Probability Analysis65; CHECK-NEXT: Lazy Block Frequency Analysis66; CHECK-NEXT: Optimization Remark Emitter67; CHECK-NEXT: Partially inline calls to library functions68; CHECK-NEXT: Instrument function entry/exit with calls to e.g. mcount() (post inlining)69; CHECK-NEXT: Scalarize Masked Memory Intrinsics70; CHECK-NEXT: Expand reduction intrinsics71; CHECK-NEXT: Natural Loop Information72; CHECK-NEXT: CodeGen Prepare73; CHECK-NEXT: Dominator Tree Construction74; CHECK-NEXT: Exception handling preparation75; CHECK-NEXT: Merge internal globals76; CHECK-NEXT: Natural Loop Information77; CHECK-NEXT: Scalar Evolution Analysis78; CHECK-NEXT: Prepare loop for ppc preferred instruction forms79; CHECK-NEXT: Scalar Evolution Analysis80; CHECK-NEXT: Lazy Branch Probability Analysis81; CHECK-NEXT: Lazy Block Frequency Analysis82; CHECK-NEXT: Optimization Remark Emitter83; CHECK-NEXT: Hardware Loop Insertion84; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)85; CHECK-NEXT: Function Alias Analysis Results86; CHECK-NEXT: ObjC ARC contraction87; CHECK-NEXT: Prepare callbr88; CHECK-NEXT: Safe Stack instrumentation pass89; CHECK-NEXT: Insert stack protectors90; CHECK-NEXT: Module Verifier91; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)92; CHECK-NEXT: Function Alias Analysis Results93; CHECK-NEXT: Natural Loop Information94; CHECK-NEXT: Post-Dominator Tree Construction95; CHECK-NEXT: Branch Probability Analysis96; CHECK-NEXT: Assignment Tracking Analysis97; CHECK-NEXT: Lazy Branch Probability Analysis98; CHECK-NEXT: Lazy Block Frequency Analysis99; CHECK-NEXT: PowerPC DAG->DAG Pattern Instruction Selection100; CHECK-NEXT: MachineDominator Tree Construction101; CHECK-NEXT: PowerPC CTR Loops Verify102; CHECK-NEXT: PowerPC VSX Copy Legalization103; CHECK-NEXT: Finalize ISel and expand pseudo-instructions104; CHECK-NEXT: MachineDominator Tree Construction105; CHECK-NEXT: Machine Natural Loop Construction106; CHECK-NEXT: PowerPC CTR loops generation107; CHECK-NEXT: Lazy Machine Block Frequency Analysis108; CHECK-NEXT: Early Tail Duplication109; CHECK-NEXT: Optimize machine instruction PHIs110; CHECK-NEXT: Slot index numbering111; CHECK-NEXT: Merge disjoint stack slots112; CHECK-NEXT: Local Stack Slot Allocation113; CHECK-NEXT: Remove dead machine instructions114; CHECK-NEXT: MachineDominator Tree Construction115; CHECK-NEXT: Machine Natural Loop Construction116; CHECK-NEXT: Machine Trace Metrics117; CHECK-NEXT: Early If-Conversion118; CHECK-NEXT: Lazy Machine Block Frequency Analysis119; CHECK-NEXT: Machine InstCombiner120; CHECK-NEXT: Machine Block Frequency Analysis121; CHECK-NEXT: Early Machine Loop Invariant Code Motion122; CHECK-NEXT: MachineDominator Tree Construction123; CHECK-NEXT: Machine Block Frequency Analysis124; CHECK-NEXT: Machine Common Subexpression Elimination125; CHECK-NEXT: MachinePostDominator Tree Construction126; CHECK-NEXT: Machine Cycle Info Analysis127; CHECK-NEXT: Machine code sinking128; CHECK-NEXT: Peephole Optimizations129; CHECK-NEXT: Remove dead machine instructions130; CHECK-NEXT: MachineDominator Tree Construction131; CHECK-NEXT: PowerPC Reduce CR logical Operation132; CHECK-NEXT: Remove unreachable machine basic blocks133; CHECK-NEXT: Live Variable Analysis134; CHECK-NEXT: MachineDominator Tree Construction135; CHECK-NEXT: MachinePostDominator Tree Construction136; CHECK-NEXT: Machine Natural Loop Construction137; CHECK-NEXT: Machine Block Frequency Analysis138; CHECK-NEXT: PowerPC MI Peephole Optimization139; CHECK-NEXT: Remove dead machine instructions140; CHECK-NEXT: Remove unreachable machine basic blocks141; CHECK-NEXT: Live Variable Analysis142; CHECK-NEXT: Slot index numbering143; CHECK-NEXT: Live Interval Analysis144; CHECK-NEXT: PowerPC TLS Dynamic Call Fixup145; CHECK-NEXT: PowerPC TOC Register Dependencies146; CHECK-NEXT: MachineDominator Tree Construction147; CHECK-NEXT: Machine Natural Loop Construction148; CHECK-NEXT: Slot index numbering149; CHECK-NEXT: Live Interval Analysis150; CHECK-NEXT: Lazy Machine Block Frequency Analysis151; CHECK-NEXT: Machine Optimization Remark Emitter152; CHECK-NEXT: Modulo Software Pipelining153; CHECK-NEXT: Detect Dead Lanes154; CHECK-NEXT: Init Undef Pass155; CHECK-NEXT: Process Implicit Definitions156; CHECK-NEXT: Remove unreachable machine basic blocks157; CHECK-NEXT: Live Variable Analysis158; CHECK-NEXT: MachineDominator Tree Construction159; CHECK-NEXT: Machine Natural Loop Construction160; CHECK-NEXT: Eliminate PHI nodes for register allocation161; CHECK-NEXT: Two-Address instruction pass162; CHECK-NEXT: Slot index numbering163; CHECK-NEXT: Live Interval Analysis164; CHECK-NEXT: Register Coalescer165; CHECK-NEXT: Rename Disconnected Subregister Components166; CHECK-NEXT: Machine Instruction Scheduler167; CHECK-NEXT: PowerPC VSX FMA Mutation168; CHECK-NEXT: Machine Natural Loop Construction169; CHECK-NEXT: Machine Block Frequency Analysis170; CHECK-NEXT: Debug Variable Analysis171; CHECK-NEXT: Live Stack Slot Analysis172; CHECK-NEXT: Virtual Register Map173; CHECK-NEXT: Live Register Matrix174; CHECK-NEXT: Bundle Machine CFG Edges175; CHECK-NEXT: Spill Code Placement Analysis176; CHECK-NEXT: Lazy Machine Block Frequency Analysis177; CHECK-NEXT: Machine Optimization Remark Emitter178; CHECK-NEXT: Greedy Register Allocator179; CHECK-NEXT: Virtual Register Rewriter180; CHECK-NEXT: Register Allocation Pass Scoring181; CHECK-NEXT: Stack Slot Coloring182; CHECK-NEXT: Machine Copy Propagation Pass183; CHECK-NEXT: Machine Loop Invariant Code Motion184; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis185; CHECK-NEXT: Fixup Statepoint Caller Saved186; CHECK-NEXT: PostRA Machine Sink187; CHECK-NEXT: Machine Block Frequency Analysis188; CHECK-NEXT: MachineDominator Tree Construction189; CHECK-NEXT: MachinePostDominator Tree Construction190; CHECK-NEXT: Lazy Machine Block Frequency Analysis191; CHECK-NEXT: Machine Optimization Remark Emitter192; CHECK-NEXT: Shrink Wrapping analysis193; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization194; CHECK-NEXT: Machine Late Instructions Cleanup Pass195; CHECK-NEXT: Control Flow Optimizer196; CHECK-NEXT: Lazy Machine Block Frequency Analysis197; CHECK-NEXT: Tail Duplication198; CHECK-NEXT: Machine Copy Propagation Pass199; CHECK-NEXT: Post-RA pseudo instruction expansion pass200; CHECK-NEXT: MachineDominator Tree Construction201; CHECK-NEXT: Machine Natural Loop Construction202; CHECK-NEXT: Machine Block Frequency Analysis203; CHECK-NEXT: If Converter204; CHECK-NEXT: MachineDominator Tree Construction205; CHECK-NEXT: Machine Natural Loop Construction206; CHECK-NEXT: PostRA Machine Instruction Scheduler207; CHECK-NEXT: Analyze Machine Code For Garbage Collection208; CHECK-NEXT: Machine Block Frequency Analysis209; CHECK-NEXT: MachinePostDominator Tree Construction210; CHECK-NEXT: Branch Probability Basic Block Placement211; CHECK-NEXT: Insert fentry calls212; CHECK-NEXT: Insert XRay ops213; CHECK-NEXT: Implement the 'patchable-function' attribute214; CHECK-NEXT: PowerPC Pre-Emit Peephole215; CHECK-NEXT: PowerPC Early-Return Creation216; CHECK-NEXT: Contiguously Lay Out Funclets217; CHECK-NEXT: Remove Loads Into Fake Uses218; CHECK-NEXT: StackMap Liveness Analysis219; CHECK-NEXT: Live DEBUG_VALUE analysis220; CHECK-NEXT: Machine Sanitizer Binary Metadata221; CHECK-NEXT: Lazy Machine Block Frequency Analysis222; CHECK-NEXT: Machine Optimization Remark Emitter223; CHECK-NEXT: Stack Frame Layout Analysis224; CHECK-NEXT: PowerPC Expand Atomic225; CHECK-NEXT: PowerPC Branch Selector226; CHECK-NEXT: Lazy Machine Block Frequency Analysis227; CHECK-NEXT: Machine Optimization Remark Emitter228; CHECK-NEXT: Linux PPC Assembly Printer229; CHECK-NEXT: Free MachineFunction230 231define void @f() {232 ret void233}234