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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 62; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s4 5; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr9 -mtriple=powerpc64-ibm-aix \6; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s7 8; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr9 -mtriple=powerpc-ibm-aix \9; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s10 11; Optimized version which `xxleqv` and `vsubu` to generate vector of -1s to leverage the identity A - (-1) = A + 1.12 13; Function for the vector type v2i64 `a + {1, 1}`14define <2 x i64> @test_v2i64(<2 x i64> %a) {15; CHECK-LABEL: test_v2i64:16; CHECK: # %bb.0: # %entry17; CHECK-NEXT: xxleqv v3, v3, v318; CHECK-NEXT: vsubudm v2, v2, v319; CHECK-NEXT: blr20entry:21 %add = add <2 x i64> %a, splat (i64 1)22 ret <2 x i64> %add23}24 25; Function for the vector type v4i32 `a + {1, 1, 1, 1}`26define <4 x i32> @test_v4i32(<4 x i32> %a) {27; CHECK-LABEL: test_v4i32:28; CHECK: # %bb.0: # %entry29; CHECK-NEXT: xxleqv v3, v3, v330; CHECK-NEXT: vsubuwm v2, v2, v331; CHECK-NEXT: blr32entry:33 %add = add <4 x i32> %a, splat (i32 1)34 ret <4 x i32> %add35}36 37; Function for the vector type v8i16 `a + {1, 1, 1, 1, 1, 1, 1, 1}`38define <8 x i16> @test_v8i16(<8 x i16> %a) {39; CHECK-LABEL: test_v8i16:40; CHECK: # %bb.0: # %entry41; CHECK-NEXT: xxleqv v3, v3, v342; CHECK-NEXT: vsubuhm v2, v2, v343; CHECK-NEXT: blr44entry:45 %add = add <8 x i16> %a, splat (i16 1)46 ret <8 x i16> %add47}48 49; Function for the vector type v16i8 `a + {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}`50define <16 x i8> @test_16i8(<16 x i8> %a) {51; CHECK-LABEL: test_16i8:52; CHECK: # %bb.0: # %entry53; CHECK-NEXT: xxleqv v3, v3, v354; CHECK-NEXT: vsububm v2, v2, v355; CHECK-NEXT: blr56entry:57 %add = add <16 x i8> %a, splat (i8 1)58 ret <16 x i8> %add59}60