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1; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \2; RUN: -ppc-asm-full-reg-names -mcpu=pwr9 < %s | FileCheck %s3; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \4; RUN: -ppc-asm-full-reg-names -mcpu=pwr9 < %s | FileCheck %s5 6define i64 @addze1(i64 %X, i64 %Z) {7; CHECK-LABEL: addze1:8; CHECK: # %bb.0:9; CHECK-NEXT: addic [[REG1:r[0-9]+]], [[REG1]], -110; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]11; CHECK-NEXT: blr12 %cmp = icmp ne i64 %Z, 013 %conv1 = zext i1 %cmp to i6414 %add = add nsw i64 %conv1, %X15 ret i64 %add16}17 18define i64 @addze2(i64 %X, i64 %Z) {19; CHECK-LABEL: addze2:20; CHECK: # %bb.0:21; CHECK-NEXT: subfic [[REG1:r[0-9]+]], [[REG1]], 022; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]23; CHECK-NEXT: blr24 %cmp = icmp eq i64 %Z, 025 %conv1 = zext i1 %cmp to i6426 %add = add nsw i64 %conv1, %X27 ret i64 %add28}29 30define i64 @addze3(i64 %X, i64 %Z) {31; CHECK-LABEL: addze3:32; CHECK: # %bb.0:33; CHECK-NEXT: addi [[REG1:r[0-9]+]], [[REG1]], -3276834; CHECK-NEXT: addic [[REG1]], [[REG1]], -135; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]36; CHECK-NEXT: blr37 %cmp = icmp ne i64 %Z, 3276838 %conv1 = zext i1 %cmp to i6439 %add = add nsw i64 %conv1, %X40 ret i64 %add41}42 43define i64 @addze4(i64 %X, i64 %Z) {44; CHECK-LABEL: addze4:45; CHECK: # %bb.0:46; CHECK-NEXT: addi [[REG1:r[0-9]+]], [[REG1]], -3276847; CHECK-NEXT: subfic [[REG1]], [[REG1]], 048; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]49; CHECK-NEXT: blr50 %cmp = icmp eq i64 %Z, 3276851 %conv1 = zext i1 %cmp to i6452 %add = add nsw i64 %conv1, %X53 ret i64 %add54}55 56define i64 @addze5(i64 %X, i64 %Z) {57; CHECK-LABEL: addze5:58; CHECK: # %bb.0:59; CHECK-NEXT: addi [[REG1:r[0-9]+]], [[REG1]], 3276760; CHECK-NEXT: addic [[REG1]], [[REG1]], -161; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]62; CHECK-NEXT: blr63 %cmp = icmp ne i64 %Z, -3276764 %conv1 = zext i1 %cmp to i6465 %add = add nsw i64 %conv1, %X66 ret i64 %add67}68 69define i64 @addze6(i64 %X, i64 %Z) {70; CHECK-LABEL: addze6:71; CHECK: # %bb.0:72; CHECK-NEXT: addi [[REG1:r[0-9]+]], [[REG1]], 3276773; CHECK-NEXT: subfic [[REG1]], [[REG1]], 074; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]75; CHECK-NEXT: blr76 %cmp = icmp eq i64 %Z, -3276777 %conv1 = zext i1 %cmp to i6478 %add = add nsw i64 %conv1, %X79 ret i64 %add80}81 82; element is out of range83define i64 @test1(i64 %X, i64 %Z) {84; CHECK-LABEL: test1:85; CHECK: # %bb.0:86; CHECK-NEXT: li [[REG1:r[0-9]+]], -3276887; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1]]88; CHECK-NEXT: addic [[REG1]], [[REG2]], -189; CHECK-NEXT: subfe [[REG2]], [[REG1]], [[REG2]]90; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]91; CHECK-NEXT: blr92 %cmp = icmp ne i64 %Z, -3276893 %conv1 = zext i1 %cmp to i6494 %add = add nsw i64 %conv1, %X95 ret i64 %add96}97 98define i64 @test2(i64 %X, i64 %Z) {99; CHECK-LABEL: test2:100; CHECK: # %bb.0:101; CHECK-NEXT: li [[REG1:r[0-9]+]], -32768102; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1]]103; CHECK-NEXT: cntlzd [[REG2]], [[REG2]]104; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63105; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]106; CHECK-NEXT: blr107 %cmp = icmp eq i64 %Z, -32768108 %conv1 = zext i1 %cmp to i64109 %add = add nsw i64 %conv1, %X110 ret i64 %add111}112 113define i64 @test3(i64 %X, i64 %Z) {114; CHECK-LABEL: test3:115; CHECK: # %bb.0:116; CHECK-NEXT: li [[REG1:r[0-9]+]], 0117; CHECK-NEXT: ori [[REG1]], [[REG1]], 32769118; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1]]119; CHECK-NEXT: addic [[REG1]], [[REG2]], -1120; CHECK-NEXT: subfe [[REG2]], [[REG1]], [[REG2]]121; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]122; CHECK-NEXT: blr123 %cmp = icmp ne i64 %Z, 32769124 %conv1 = zext i1 %cmp to i64125 %add = add nsw i64 %conv1, %X126 ret i64 %add127}128 129define i64 @test4(i64 %X, i64 %Z) {130; CHECK-LABEL: test4:131; CHECK: # %bb.0:132; CHECK-NEXT: li [[REG1:r[0-9]+]], 0133; CHECK-NEXT: ori [[REG1]], [[REG1]], 32769134; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1]]135; CHECK-NEXT: cntlzd [[REG2]], [[REG2]]136; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63137; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]138; CHECK-NEXT: blr139 %cmp = icmp eq i64 %Z, 32769140 %conv1 = zext i1 %cmp to i64141 %add = add nsw i64 %conv1, %X142 ret i64 %add143}144 145; comparison of two registers146define i64 @test5(i64 %X, i64 %Y, i64 %Z) {147; CHECK-LABEL: test5:148; CHECK: # %bb.0:149; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1:r[0-9]+]]150; CHECK-NEXT: addic [[REG1]], [[REG2]], -1151; CHECK-NEXT: subfe [[REG2]], [[REG1]], [[REG2]]152; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]153; CHECK-NEXT: blr154 %cmp = icmp ne i64 %Y, %Z155 %conv1 = zext i1 %cmp to i64156 %add = add nsw i64 %conv1, %X157 ret i64 %add158}159 160define i64 @test6(i64 %X, i64 %Y, i64 %Z) {161; CHECK-LABEL: test6:162; CHECK: # %bb.0:163; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1:r[0-9]+]]164; CHECK-NEXT: cntlzd [[REG2]], [[REG2]]165; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63166; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]167; CHECK-NEXT: blr168 %cmp = icmp eq i64 %Y, %Z169 %conv1 = zext i1 %cmp to i64170 %add = add nsw i64 %conv1, %X171 ret i64 %add172}173