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1; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -xcoff-traceback-table=false \2; RUN: -vec-extabi -mtriple powerpc-ibm-aix-xcoff < %s | \3; RUN: FileCheck --check-prefixes=ASM32,ASM %s4 5; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -xcoff-traceback-table=false \6; RUN: -vec-extabi -mtriple powerpc64-ibm-aix-xcoff < %s | \7; RUN: FileCheck --check-prefixes=ASM64,ASM %s8 9define dso_local <4 x i32> @vec_callee(<4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3, <4 x i32> %vec4, <4 x i32> %vec5, <4 x i32> %vec6, <4 x i32> %vec7, <4 x i32> %vec8, <4 x i32> %vec9, <4 x i32> %vec10, <4 x i32> %vec11, <4 x i32> %vec12) {10entry:11 %add = add <4 x i32> %vec1, %vec212 %add1 = add <4 x i32> %add, %vec313 %add2 = add <4 x i32> %add1, %vec414 %add3 = add <4 x i32> %add2, %vec515 %add4 = add <4 x i32> %add3, %vec616 %add5 = add <4 x i32> %add4, %vec717 %add6 = add <4 x i32> %add5, %vec818 %add7 = add <4 x i32> %add6, %vec919 %add8 = add <4 x i32> %add7, %vec1020 %add9 = add <4 x i32> %add8, %vec1121 %add10 = add <4 x i32> %add9, %vec1222 ret <4 x i32> %add1023}24 25; ASM-LABEL: .vec_callee:26 27; ASM: %entry28; ASM-DAG: vadduwm 2, 2, 329; ASM-DAG: vadduwm 2, 2, 430; ASM-DAG: vadduwm 2, 2, 531; ASM-DAG: vadduwm 2, 2, 632; ASM-DAG: vadduwm 2, 2, 733; ASM-DAG: vadduwm 2, 2, 834; ASM-DAG: vadduwm 2, 2, 935; ASM-DAG: vadduwm 2, 2, 1036; ASM-DAG: vadduwm 2, 2, 1137; ASM-DAG: vadduwm 2, 2, 1238; ASM-DAG: vadduwm 2, 2, 1339; ASM: blr40 41define dso_local i32 @vec_caller() {42entry:43 %call = call <4 x i32> @vec_callee(<4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> <i32 9, i32 10, i32 11, i32 12>, <4 x i32> <i32 13, i32 14, i32 15, i32 16>, <4 x i32> <i32 17, i32 18, i32 19, i32 20>, <4 x i32> <i32 21, i32 22, i32 23, i32 24>, <4 x i32> <i32 25, i32 26, i32 27, i32 28>, <4 x i32> <i32 29, i32 30, i32 31, i32 32>, <4 x i32> <i32 33, i32 34, i32 35, i32 36>, <4 x i32> <i32 37, i32 38, i32 39, i32 40>, <4 x i32> <i32 41, i32 42, i32 43, i32 44>, <4 x i32> <i32 45, i32 46, i32 47, i32 48>)44 ret i32 045}46 47; ASM-LABEL: .vec_caller:48; ASM32: # %bb.0: # %entry49; ASM32-DAG: mflr 050; ASM32-DAG: stwu 1, -64(1)51; ASM32-DAG: lwz [[REG1:[0-9]+]], L..C0(2)52; ASM32-DAG: lxvw4x 34, 0, [[REG1]]53; ASM32-DAG: lwz [[REG2:[0-9]+]], L..C1(2)54; ASM32-DAG: lxvw4x 35, 0, [[REG2]]55; ASM32-DAG: lwz [[REG3:[0-9]+]], L..C2(2)56; ASM32-DAG: lxvw4x 36, 0, [[REG3]]57; ASM32-DAG: lwz [[REG4:[0-9]+]], L..C3(2)58; ASM32-DAG: lxvw4x 37, 0, [[REG4]]59; ASM32-DAG: lwz [[REG5:[0-9]+]], L..C4(2)60; ASM32-DAG: lxvw4x 38, 0, [[REG5]]61; ASM32-DAG: lwz [[REG6:[0-9]+]], L..C5(2)62; ASM32-DAG: lxvw4x 39, 0, [[REG6]]63; ASM32-DAG: lwz [[REG7:[0-9]+]], L..C6(2)64; ASM32-DAG: lxvw4x 40, 0, [[REG7]]65; ASM32-DAG: lwz [[REG8:[0-9]+]], L..C7(2)66; ASM32-DAG: lxvw4x 41, 0, [[REG8]]67; ASM32-DAG: lwz [[REG9:[0-9]+]], L..C8(2)68; ASM32-DAG: lxvw4x 42, 0, [[REG9]]69; ASM32-DAG: lwz [[REG10:[0-9]+]], L..C9(2)70; ASM32-DAG: lxvw4x 43, 0, [[REG10]]71; ASM32-DAG: lwz [[REG11:[0-9]+]], L..C10(2)72; ASM32-DAG: lxvw4x 44, 0, [[REG11]]73; ASM32-DAG: lwz [[REG12:[0-9]+]], L..C11(2)74; ASM32-DAG: lxvw4x 45, 0, [[REG12]]75; ASM32-DAG: stw 0, 72(1)76; ASM32-DAG: bl .vec_callee77; ASM32-DAG: li 3, 078; ASM32-DAG: addi 1, 1, 6479; ASM32-DAG: lwz 0, 8(1)80; ASM32-DAG: mtlr 081; ASM32: blr82 83; ASM64: # %entry84; ASM64-DAG: stdu 1, -112(1)85; ASM64-DAG: ld [[REG1:[0-9]+]], L..C0(2)86; ASM64-DAG: lxvw4x 34, 0, [[REG1]]87; ASM64-DAG: ld [[REG2:[0-9]+]], L..C1(2)88; ASM64-DAG: lxvw4x 35, 0, [[REG2]]89; ASM64-DAG: ld [[REG3:[0-9]+]], L..C2(2)90; ASM64-DAG: lxvw4x 36, 0, [[REG3]]91; ASM64-DAG: ld [[REG4:[0-9]+]], L..C3(2)92; ASM64-DAG: lxvw4x 37, 0, [[REG4]]93; ASM64-DAG: ld [[REG5:[0-9]+]], L..C4(2)94; ASM64-DAG: lxvw4x 38, 0, [[REG5]]95; ASM64-DAG: ld [[REG6:[0-9]+]], L..C5(2)96; ASM64-DAG: lxvw4x 39, 0, [[REG6]]97; ASM64-DAG: ld [[REG7:[0-9]+]], L..C6(2)98; ASM64-DAG: lxvw4x 40, 0, [[REG7]]99; ASM64-DAG: ld [[REG8:[0-9]+]], L..C7(2)100; ASM64-DAG: lxvw4x 41, 0, [[REG8]]101; ASM64-DAG: ld [[REG9:[0-9]+]], L..C8(2)102; ASM64-DAG: lxvw4x 42, 0, [[REG9]]103; ASM64-DAG: ld [[REG10:[0-9]+]], L..C9(2)104; ASM64-DAG: lxvw4x 43, 0, [[REG10]]105; ASM64-DAG: ld [[REG11:[0-9]+]], L..C10(2)106; ASM64-DAG: lxvw4x 44, 0, [[REG11]]107; ASM64-DAG: ld [[REG12:[0-9]+]], L..C11(2)108; ASM64-DAG: lxvw4x 45, 0, [[REG12]]109; ASM64-DAG: std 0, 128(1)110; ASM64-DAG: bl .vec_callee111; ASM64-DAG: li 3, 0112; ASM64-DAG: addi 1, 1, 112113; ASM64-DAG: ld 0, 16(1)114; ASM64-DAG: mtlr 0115; ASM64: blr116