167 lines · plain
1; RUN: llc --verify-machineinstrs -mtriple powerpc-ibm-aix --code-model=small < \2; RUN: %s | FileCheck --check-prefixes=CHECK,CHECK32,CHECK-SMALL,CHECK-SMALL32 %s3 4; RUN: llc --verify-machineinstrs -mtriple powerpc-ibm-aix --code-model=large < \5; RUN: %s | FileCheck --check-prefixes=CHECK,CHECK32,CHECK-LARGE,CHECK-LARGE32 %s6 7; RUN: llc --verify-machineinstrs -mtriple powerpc64-ibm-aix --code-model=small < \8; RUN: %s | FileCheck --check-prefixes=CHECK,CHECK64,CHECK-SMALL,CHECK-SMALL64 %s9 10; RUN: llc --verify-machineinstrs -mtriple powerpc64-ibm-aix --code-model=large < \11; RUN: %s | FileCheck --check-prefixes=CHECK,CHECK64,CHECK-LARGE,CHECK-LARGE64 %s12 13@a = external dso_local global i32, code_model "small", align 414@b = external dso_local global i32, code_model "large", align 415@c = dso_local global i32 55, code_model "small", align 416@d = dso_local global i32 41, code_model "large", align 417@e = external dso_local global i32, align 418@f = dso_local global i32 2748, align 419 20@large_aliasee = global i32 10, code_model "large", align 421@small_aliasee = global i32 171, code_model "small", align 422@normal_aliasee = global i32 2748, align 423 24@al = alias i32, ptr @large_aliasee25@as = alias i32, ptr @small_aliasee26@an = alias i32, ptr @normal_aliasee27 28define i32 @A() local_unnamed_addr {29entry:30 %0 = load i32, ptr @a, align 431 ret i32 %032}33; CHECK32: lwz [[SCRATCH:[0-9]+]], L..C[[TL_A:[0-9]+]](2) # @a34; CHECK64: ld [[SCRATCH:[0-9]+]], L..C[[TL_A:[0-9]+]](2) # @a35; CHECK: lwz 3, 0([[SCRATCH]])36; CHECK: blr37 38define i32 @B() local_unnamed_addr {39entry:40 %0 = load i32, ptr @b, align 441 ret i32 %042}43; CHECK: addis [[HI:[0-9]+]], L..C[[TL_B:[0-9]+]]@u(2)44; CHECK32: lwz [[ADDR:[0-9]+]], L..C[[TL_B]]@l([[HI]])45; CHECK64: ld [[ADDR:[0-9]+]], L..C[[TL_B]]@l([[HI]])46; CHECK: lwz 3, 0([[ADDR]])47; CHECK: blr48 49define i32 @C() local_unnamed_addr {50entry:51 %0 = load i32, ptr @c, align 452 ret i32 %053}54; CHECK32: lwz [[SCRATCH:[0-9]+]], L..C[[TL_C:[0-9]+]](2) # @c55; CHECK64: ld [[SCRATCH:[0-9]+]], L..C[[TL_C:[0-9]+]](2) # @c56; CHECK: lwz 3, 0([[SCRATCH]])57; CHECK: blr58 59define i32 @D() local_unnamed_addr {60entry:61 %0 = load i32, ptr @d, align 462 ret i32 %063}64; CHECK: addis [[HI:[0-9]+]], L..C[[TL_D:[0-9]+]]@u(2)65; CHECK32: lwz [[ADDR:[0-9]+]], L..C[[TL_D]]@l([[HI]])66; CHECK64: ld [[ADDR:[0-9]+]], L..C[[TL_D]]@l([[HI]])67; CHECK: lwz 3, 0([[ADDR]])68; CHECK: blr69 70define i32 @E() {71entry:72 %0 = load i32, ptr @e, align 473 ret i32 %074}75; CHECK-LARGE: addis [[HI:[0-9]+]], L..C[[TL_E:[0-9]+]]@u(2)76; CHECK-LARGE32: lwz [[SCRATCH:[0-9]+]], L..C[[TL_E]]@l([[HI]])77; CHECK-SMALL32: lwz [[SCRATCH:[0-9]+]], L..C[[TL_E:[0-9]+]](2)78; CHECK-LARGE64: ld [[SCRATCH:[0-9]+]], L..C[[TL_E]]@l([[HI]])79; CHECK-SMALL64: ld [[SCRATCH:[0-9]+]], L..C[[TL_E:[0-9]+]](2)80; CHECK: lwz 3, 0([[SCRATCH]])81; CHECK: blr82 83define i32 @F() {84entry:85 %0 = load i32, ptr @f, align 486 ret i32 %087}88; CHECK-LARGE: addis [[HI:[0-9]+]], L..C[[TL_F:[0-9]+]]@u(2)89; CHECK-LARGE32: lwz [[SCRATCH:[0-9]+]], L..C[[TL_F]]@l([[HI]])90; CHECK-SMALL32: lwz [[SCRATCH:[0-9]+]], L..C[[TL_F:[0-9]+]](2)91; CHECK-LARGE64: ld [[SCRATCH:[0-9]+]], L..C[[TL_F]]@l([[HI]])92; CHECK-SMALL64: ld [[SCRATCH:[0-9]+]], L..C[[TL_F:[0-9]+]](2)93; CHECK: lwz 3, 0([[SCRATCH]])94; CHECK: blr95 96define noundef nonnull ptr @addr_a() local_unnamed_addr {97entry:98 ret ptr @a99}100; CHECK32: lwz 3, L..C[[TL_A]](2) # @a101; CHECK64: ld 3, L..C[[TL_A]](2) # @a102; CHECK: blr103 104define noundef nonnull ptr @addr_b() local_unnamed_addr {105entry:106 ret ptr @b107}108; CHECK: addis [[HI:[0-9]+]], L..C[[TL_B]]@u(2)109; CHECK32: lwz 3, L..C[[TL_B]]@l([[HI]])110; CHECK64: ld 3, L..C[[TL_B]]@l([[HI]])111; CHECK: blr112 113 114define noundef nonnull ptr @addr_c() local_unnamed_addr {115entry:116 ret ptr @c117}118; CHECK32: lwz 3, L..C[[TL_C]](2) # @c119; CHECK64: ld 3, L..C[[TL_C]](2) # @c120; CHECK: blr121 122define noundef nonnull ptr @addr_d() local_unnamed_addr {123entry:124 ret ptr @d125}126; CHECK: addis [[HI:[0-9]+]], L..C[[TL_D]]@u(2)127; CHECK32: lwz 3, L..C[[TL_D]]@l([[HI]])128; CHECK64: ld 3, L..C[[TL_D]]@l([[HI]])129; CHECK: blr130 131define i32 @G() {132 %tmp = load i32, ptr @al133 ret i32 %tmp134}135; CHECK: addis [[HI:[0-9]+]], L..C[[TL_AL:[0-9]+]]@u(2)136; CHECK32: lwz [[ADDR:[0-9]+]], L..C[[TL_AL]]@l([[HI]])137; CHECK64: ld [[ADDR:[0-9]+]], L..C[[TL_AL]]@l([[HI]])138; CHECK: lwz 3, 0([[ADDR]])139 140define i32 @H() {141 %tmp = load i32, ptr @as142 ret i32 %tmp143}144; CHECK32: lwz [[ADDR:[0-9]+]], L..C[[TL_AS:[0-9]+]](2)145; CHECK64: ld [[ADDR:[0-9]+]], L..C[[TL_AS:[0-9]+]](2)146; CHECK: lwz 3, 0([[ADDR]])147 148;; Check TOC entires have correct storage mapping class149; CHECK: L..C[[TL_A]]:150; CHECK: .tc a[TC],a[UA]151; CHECK: L..C[[TL_B]]:152; CHECK: .tc b[TE],b[UA]153; CHECK: L..C[[TL_C]]:154; CHECK: .tc c[TC],c[RW]155; CHECK: L..C[[TL_D]]:156; CHECK: .tc d[TE],d[RW]157; CHECK: L..C[[TL_E]]:158; CHECK-SMALL: .tc e[TC],e[UA]159; CHECK-LARGE: .tc e[TE],e[UA]160; CHECK: L..C[[TL_F]]:161; CHECK-SMALL: .tc f[TC],f[RW]162; CHECK-LARGE: .tc f[TE],f[RW]163; CHECK: L..C[[TL_AL]]:164; CHECK: .tc al[TE],al165; CHECK: L..C[[TL_AS]]:166; CHECK: .tc as[TC],as167