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1;; Test to ensure that we are not using any of the aliased reserved registers2;; under the Extended Altivec ABI on AIX.3; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+altivec \4; RUN: -stop-after=machine-cp -mtriple powerpc64-ibm-aix-xcoff < %s | \5; RUN: FileCheck %s --check-prefix=DFLABI6; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+altivec -vec-extabi\7; RUN: -stop-after=machine-cp -mtriple powerpc64-ibm-aix-xcoff < %s | \8; RUN: FileCheck %s --check-prefix=EXTABI9 10define double @dbl_test(double %a, ptr %b) local_unnamed_addr {11entry:12 %0 = load volatile double, ptr %b, align 413 %add = fadd double %0, %a14 store volatile double %add, ptr %b, align 415 ;; Clobbered all vector and floating point registers. In the default Altivec16 ;; ABI this forces a register spill since no registers are free to use.17 tail call void asm sideeffect "nop", "~{v19},~{v18},~{v17},~{v16},~{v15},~{v14},~{v13},~{v12},~{v11},~{v10},~{v9},~{v8},~{v7},~{v6},~{v5},~{v4},~{v3},~{v2},~{v1},~{v0},~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"()18 %mul = fmul double %a, %a19 %1 = load volatile double, ptr %b, align 420 %add1 = fadd double %mul, %121 store volatile double %add1, ptr %b, align 422 %2 = load volatile double, ptr %b, align 423 ret double %224}25 26define <4 x i32> @vec_test(<4 x i32> %a, ptr %b) local_unnamed_addr {27entry:28 %0 = load volatile <4 x i32>, ptr %b, align 429 %add = add <4 x i32> %0, %a30 store volatile <4 x i32> %add, ptr %b, align 431 tail call void asm sideeffect "nop", "~{v19},~{v18},~{v17},~{v16},~{v15},~{v14},~{v13},~{v12},~{v11},~{v10},~{v9},~{v8},~{v7},~{v6},~{v5},~{v4},~{v3},~{v2},~{v1},~{v0},~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"()32 %mul = mul <4 x i32> %a, %a33 %1 = load volatile <4 x i32>, ptr %b, align 434 %add1 = add <4 x i32> %mul, %135 store volatile <4 x i32> %add1, ptr %b, align 436 %2 = load volatile <4 x i32>, ptr %b, align 437 ret <4 x i32> %238}39 40; DFLABI-LABEL: dbl_test41 42; DFLABI-NOT: $v2043; DFLABI-NOT: $v2144; DFLABI-NOT: $v2245; DFLABI-NOT: $v2346; DFLABI-NOT: $v2447; DFLABI-NOT: $v2548; DFLABI-NOT: $v2649; DFLABI-NOT: $v2750; DFLABI-NOT: $v2851; DFLABI-NOT: $v2952; DFLABI-NOT: $v3053; DFLABI-NOT: $v3154 55; DFLABI-NOT: $vf2056; DFLABI-NOT: $vf2157; DFLABI-NOT: $vf2258; DFLABI-NOT: $vf2359; DFLABI-NOT: $vf2460; DFLABI-NOT: $vf2561; DFLABI-NOT: $vf2662; DFLABI-NOT: $vf2763; DFLABI-NOT: $vf2864; DFLABI-NOT: $vf2965; DFLABI-NOT: $vf3066; DFLABI-NOT: $vf3167 68; DFLABI-NOT: $vs2069; DFLABI-NOT: $vs2170; DFLABI-NOT: $vs2271; DFLABI-NOT: $vs2372; DFLABI-NOT: $vs2473; DFLABI-NOT: $vs2574; DFLABI-NOT: $vs2675; DFLABI-NOT: $vs2776; DFLABI-NOT: $vs2877; DFLABI-NOT: $vs2978; DFLABI-NOT: $vs3079; DFLABI-NOT: $vs3180 81; EXTABI-LABEL: vec_test82; EXTABI: liveins:83; EXTABI-NEXT: - { reg: '$f1', virtual-reg: '' }84; EXTABI-NEXT: - { reg: '$x4', virtual-reg: '' }85; EXTABI: body: |86; EXTABI: bb.0.entry:87; EXTABI: liveins: $f1, $x488; EXTABI-DAG: renamable $f0 = LFD 0, renamable $x4 :: (volatile load (s64) from %ir.b, align 4)89; EXTABI-DAG: renamable $f0 = nofpexcept XSADDDP killed renamable $f0, $f1, implicit $rm90; EXTABI: STFD killed renamable $f0, 0, renamable $x4 :: (volatile store (s64) into %ir.b, align 4)91; EXTABI-LABEL: INLINEASM92; EXTABI-DAG: renamable $f0 = nofpexcept XSMULDP killed renamable $vf31, renamable $vf31, implicit $rm93; EXTABI-DAG: renamable $f1 = LFD 0, renamable $x4 :: (volatile load (s64) from %ir.b, align 4)94; EXTABI-DAG: renamable $f0 = nofpexcept XSADDDP killed renamable $f0, killed renamable $f1, implicit $rm95; EXTABI-DAG: STFD killed renamable $f0, 0, renamable $x4 :: (volatile store (s64) into %ir.b, align 4)96; EXTABI: renamable $f1 = LFD 0, killed renamable $x4 :: (volatile load (s64) from %ir.b, align 4)97 98; DFLABI-LABEL: vec_test99 100; DFLABI-NOT: $v20101; DFLABI-NOT: $v21102; DFLABI-NOT: $v22103; DFLABI-NOT: $v23104; DFLABI-NOT: $v24105; DFLABI-NOT: $v25106; DFLABI-NOT: $v26107; DFLABI-NOT: $v27108; DFLABI-NOT: $v28109; DFLABI-NOT: $v29110; DFLABI-NOT: $v30111; DFLABI-NOT: $v31112 113; DFLABI-NOT: $vf20114; DFLABI-NOT: $vf21115; DFLABI-NOT: $vf22116; DFLABI-NOT: $vf23117; DFLABI-NOT: $vf24118; DFLABI-NOT: $vf25119; DFLABI-NOT: $vf26120; DFLABI-NOT: $vf27121; DFLABI-NOT: $vf28122; DFLABI-NOT: $vf29123; DFLABI-NOT: $vf30124; DFLABI-NOT: $vf31125 126; DFLABI-NOT: $vs20127; DFLABI-NOT: $vs21128; DFLABI-NOT: $vs22129; DFLABI-NOT: $vs23130; DFLABI-NOT: $vs24131; DFLABI-NOT: $vs25132; DFLABI-NOT: $vs26133; DFLABI-NOT: $vs27134; DFLABI-NOT: $vs28135; DFLABI-NOT: $vs29136; DFLABI-NOT: $vs30137; DFLABI-NOT: $vs31138 139; EXTABI-LABEL: vec_test140 141; EXTABI: liveins:142; EXTABI-NEXT: - { reg: '$v2', virtual-reg: '' }143; EXTABI-NEXT: - { reg: '$x3', virtual-reg: '' }144; EXTABI: body: |145; EXTABI-DAG: bb.0.entry:146; EXTABI-DAG: liveins: $v2, $x3147; EXTABI-DAG: renamable $v31 = COPY $v2148; EXTABI-DAG: renamable $v2 = LXVW4X $zero8, renamable $x3 :: (volatile load (s128) from %ir.b, align 4)149; EXTABI-DAG: renamable $v2 = VADDUWM killed renamable $v2, renamable $v31150; EXTABI-LABEL: INLINEASM151; EXTABI-DAG: renamable $v2 = VMULUWM killed renamable $v31, renamable $v31152; EXTABI-DAG: renamable $v3 = LXVW4X $zero8, renamable $x3 :: (volatile load (s128) from %ir.b, align 4)153; EXTABI-DAG: renamable $v2 = VADDUWM killed renamable $v2, killed renamable $v3154; EXTABI-DAG: STXVW4X killed renamable $v2, $zero8, renamable $x3 :: (volatile store (s128) into %ir.b, align 4)155; EXTABI: renamable $v2 = LXVW4X $zero8, killed renamable $x3 :: (volatile load (s128) from %ir.b, align 4)156