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1; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi \2; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-643; RUN: llc -mcpu=pwr9 -mtriple=powerpc-ibm-aix-xcoff -vec-extabi \4; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-325 6define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {7entry:8; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_9; CHECK: xxsldwi 0, 35, 35, 310; CHECK: xxinsertw 34, 0, 011 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3>12 ret <4 x float> %vecins13}14 15define <4 x float> @_Z7testInsILj0ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {16entry:17; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_18; CHECK-NOT: xxsldwi19; CHECK: xxinsertw 34, 35, 020 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 5, i32 1, i32 2, i32 3>21 ret <4 x float> %vecins22}23 24define <4 x float> @_Z7testInsILj0ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {25entry:26; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_27; CHECK: xxsldwi 0, 35, 35, 128; CHECK: xxinsertw 34, 0, 029 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 1, i32 2, i32 3>30 ret <4 x float> %vecins31}32 33define <4 x float> @_Z7testInsILj0ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {34entry:35; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_36; CHECK: xxswapd 0, 3537; CHECK: xxinsertw 34, 0, 038 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 7, i32 1, i32 2, i32 3>39 ret <4 x float> %vecins40}41 42define <4 x float> @_Z7testInsILj1ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {43entry:44; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_45; CHECK: xxsldwi 0, 35, 35, 346; CHECK: xxinsertw 34, 0, 447 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 3>48 ret <4 x float> %vecins49}50 51define <4 x float> @_Z7testInsILj1ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {52entry:53; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_54; CHECK-NOT: xxsldwi55; CHECK: xxinsertw 34, 35, 456 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>57 ret <4 x float> %vecins58}59 60define <4 x float> @_Z7testInsILj1ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {61entry:62; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_63; CHECK: xxsldwi 0, 35, 35, 164; CHECK: xxinsertw 34, 0, 465 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 6, i32 2, i32 3>66 ret <4 x float> %vecins67}68 69define <4 x float> @_Z7testInsILj1ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {70entry:71; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_72; CHECK: xxswapd 0, 3573; CHECK: xxinsertw 34, 0, 474 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3>75 ret <4 x float> %vecins76}77 78define <4 x float> @_Z7testInsILj2ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {79entry:80; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_81; CHECK: xxsldwi 0, 35, 35, 382; CHECK: xxinsertw 34, 0, 883 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 3>84 ret <4 x float> %vecins85}86 87define <4 x float> @_Z7testInsILj2ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {88entry:89; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_90; CHECK-NOT: xxsldwi91; CHECK: xxinsertw 34, 35, 892 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 5, i32 3>93 ret <4 x float> %vecins94}95 96define <4 x float> @_Z7testInsILj2ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {97entry:98; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_99; CHECK: xxsldwi 0, 35, 35, 1100; CHECK: xxinsertw 34, 0, 8101 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>102 ret <4 x float> %vecins103}104 105define <4 x float> @_Z7testInsILj2ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {106entry:107; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_108; CHECK: xxswapd 0, 35109; CHECK: xxinsertw 34, 0, 8110 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 7, i32 3>111 ret <4 x float> %vecins112}113 114define <4 x float> @_Z7testInsILj3ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {115entry:116; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_117; CHECK: xxsldwi 0, 35, 35, 3118; CHECK: xxinsertw 34, 0, 12119 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4>120 ret <4 x float> %vecins121}122 123define <4 x float> @_Z7testInsILj3ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {124entry:125; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_126; CHECK-NOT: xxsldwi127; CHECK: xxinsertw 34, 35, 12128 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 5>129 ret <4 x float> %vecins130}131 132define <4 x float> @_Z7testInsILj3ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {133entry:134; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_135; CHECK: xxsldwi 0, 35, 35, 1136; CHECK: xxinsertw 34, 0, 12137 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 6>138 ret <4 x float> %vecins139}140 141define <4 x float> @_Z7testInsILj3ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {142entry:143; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_144; CHECK: xxswapd 0, 35145; CHECK: xxinsertw 34, 0, 12146 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>147 ret <4 x float> %vecins148}149 150define <4 x i32> @_Z7testInsILj0ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {151entry:152; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_153; CHECK: xxsldwi 0, 35, 35, 3154; CHECK: xxinsertw 34, 0, 0155 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3>156 ret <4 x i32> %vecins157}158 159define <4 x i32> @_Z7testInsILj0ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {160entry:161; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_162; CHECK-NOT: xxsldwi163; CHECK: xxinsertw 34, 35, 0164 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 5, i32 1, i32 2, i32 3>165 ret <4 x i32> %vecins166}167 168define <4 x i32> @_Z7testInsILj0ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {169entry:170; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_171; CHECK: xxsldwi 0, 35, 35, 1172; CHECK: xxinsertw 34, 0, 0173 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 1, i32 2, i32 3>174 ret <4 x i32> %vecins175}176 177define <4 x i32> @_Z7testInsILj0ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {178entry:179; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_180; CHECK: xxswapd 0, 35181; CHECK: xxinsertw 34, 0, 0182 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 7, i32 1, i32 2, i32 3>183 ret <4 x i32> %vecins184}185 186define <4 x i32> @_Z7testInsILj1ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {187entry:188; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_189; CHECK: xxsldwi 0, 35, 35, 3190; CHECK: xxinsertw 34, 0, 4191 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 3>192 ret <4 x i32> %vecins193}194 195define <4 x i32> @_Z7testInsILj1ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {196entry:197; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_198; CHECK-NOT: xxsldwi199; CHECK: xxinsertw 34, 35, 4200 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>201 ret <4 x i32> %vecins202}203 204define <4 x i32> @_Z7testInsILj1ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {205entry:206; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_207; CHECK: xxsldwi 0, 35, 35, 1208; CHECK: xxinsertw 34, 0, 4209 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 6, i32 2, i32 3>210 ret <4 x i32> %vecins211}212 213define <4 x i32> @_Z7testInsILj1ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {214entry:215; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_216; CHECK: xxswapd 0, 35217; CHECK: xxinsertw 34, 0, 4218 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3>219 ret <4 x i32> %vecins220}221 222define <4 x i32> @_Z7testInsILj2ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {223entry:224; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_225; CHECK: xxsldwi 0, 35, 35, 3226; CHECK: xxinsertw 34, 0, 8227 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 3>228 ret <4 x i32> %vecins229}230 231define <4 x i32> @_Z7testInsILj2ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {232entry:233; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_234; CHECK-NOT: xxsldwi235; CHECK: xxinsertw 34, 35, 8236 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 5, i32 3>237 ret <4 x i32> %vecins238}239 240define <4 x i32> @_Z7testInsILj2ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {241entry:242; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_243; CHECK: xxsldwi 0, 35, 35, 1244; CHECK: xxinsertw 34, 0, 8245 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>246 ret <4 x i32> %vecins247}248 249define <4 x i32> @_Z7testInsILj2ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {250entry:251; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_252; CHECK: xxswapd 0, 35253; CHECK: xxinsertw 34, 0, 8254 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 7, i32 3>255 ret <4 x i32> %vecins256}257 258define <4 x i32> @_Z7testInsILj3ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {259entry:260; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_261; CHECK: xxsldwi 0, 35, 35, 3262; CHECK: xxinsertw 34, 0, 12263 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4>264 ret <4 x i32> %vecins265}266 267define <4 x i32> @_Z7testInsILj3ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {268entry:269; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_270; CHECK-NOT: xxsldwi271; CHECK: xxinsertw 34, 35, 12272 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 5>273 ret <4 x i32> %vecins274}275 276define <4 x i32> @_Z7testInsILj3ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {277entry:278; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_279; CHECK: xxsldwi 0, 35, 35, 1280; CHECK: xxinsertw 34, 0, 12281 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 6>282 ret <4 x i32> %vecins283}284 285define <4 x i32> @_Z7testInsILj3ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {286entry:287; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_288; CHECK: xxswapd 0, 35289; CHECK: xxinsertw 34, 0, 12290 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>291 ret <4 x i32> %vecins292}293 294define float @_Z13testUiToFpExtILj0EEfDv4_j(<4 x i32> %a) {295entry:296; CHECK-64-LABEL: _Z13testUiToFpExtILj0EEfDv4_j297; CHECK-64: xxextractuw 0, 34, 0298; CHECK-64: xscvuxdsp 1, 0299; CHECK-32-LABEL: _Z13testUiToFpExtILj0EEfDv4_j300; CHECK-32: lfiwzx 0, 0, 3301; CHECK-32: xscvuxdsp 1, 0302 %vecext = extractelement <4 x i32> %a, i32 0303 %conv = uitofp i32 %vecext to float304 ret float %conv305}306 307define float @_Z13testUiToFpExtILj1EEfDv4_j(<4 x i32> %a) {308entry:309; CHECK-64-LABEL: _Z13testUiToFpExtILj1EEfDv4_j310; CHECK-64: xxextractuw 0, 34, 4311; CHECK-64: xscvuxdsp 1, 0312; CHECK-32-LABEL: _Z13testUiToFpExtILj1EEfDv4_j313; CHECK-32: lfiwzx 0, 0, 3314; CHECK-32: xscvuxdsp 1, 0315 %vecext = extractelement <4 x i32> %a, i32 1316 %conv = uitofp i32 %vecext to float317 ret float %conv318}319 320define float @_Z13testUiToFpExtILj2EEfDv4_j(<4 x i32> %a) {321entry:322; CHECK-64-LABEL: _Z13testUiToFpExtILj2EEfDv4_j323; CHECK-64: xxextractuw 0, 34, 8324; CHECK-64: xscvuxdsp 1, 0325; CHECK-32-LABEL: _Z13testUiToFpExtILj2EEfDv4_j326; CHECK-32: lfiwzx 0, 0, 3327; CHECK-32: xscvuxdsp 1, 0328 %vecext = extractelement <4 x i32> %a, i32 2329 %conv = uitofp i32 %vecext to float330 ret float %conv331}332 333define float @_Z13testUiToFpExtILj3EEfDv4_j(<4 x i32> %a) {334entry:335; CHECK-64-LABEL: _Z13testUiToFpExtILj3EEfDv4_j336; CHECK-64: xxextractuw 0, 34, 12337; CHECK-64: xscvuxdsp 1, 0338; CHECK-32-LABEL: _Z13testUiToFpExtILj3EEfDv4_j339; CHECK-32: lfiwzx 0, 0, 3340; CHECK-32: xscvuxdsp 1, 0341 %vecext = extractelement <4 x i32> %a, i32 3342 %conv = uitofp i32 %vecext to float343 ret float %conv344}345 346; Verify we generate optimal code for unsigned vector int elem extract followed347; by conversion to double348 349define double @conv2dlbTestui0(<4 x i32> %a) {350entry:351; CHECK-64-LABEL: conv2dlbTestui0352; CHECK-64: xxextractuw [[CP64:[0-9]+]], 34, 0353; CHECK-64: xscvuxddp 1, [[CP64]]354; CHECK-32-LABEL: conv2dlbTestui0355; CHECK-32: lfiwzx [[CP32:[0-9]+]], 0, 3356; CHECK-32: xscvuxddp 1, [[CP32]]357 %0 = extractelement <4 x i32> %a, i32 0358 %1 = uitofp i32 %0 to double359 ret double %1360}361 362define double @conv2dlbTestui1(<4 x i32> %a) {363entry:364; CHECK-64-LABEL: conv2dlbTestui1365; CHECK-64: xxextractuw [[CP64:[0-9]+]], 34, 4366; CHECK-64: xscvuxddp 1, [[CP64]]367; CHECK-32-LABEL: conv2dlbTestui1368; CHECK-32: lfiwzx [[CP32:[0-9]+]], 0, 3369; CHECK-32: xscvuxddp 1, [[CP32]]370 %0 = extractelement <4 x i32> %a, i32 1371 %1 = uitofp i32 %0 to double372 ret double %1373}374 375define double @conv2dlbTestui2(<4 x i32> %a) {376entry:377; CHECK-64-LABEL: conv2dlbTestui2378; CHECK-64: xxextractuw [[CP64:[0-9]+]], 34, 8379; CHECK-64: xscvuxddp 1, [[CP64]]380; CHECK-32-LABEL: conv2dlbTestui2381; CHECK-32: lfiwzx [[CP32:[0-9]+]], 0, 3382; CHECK-32: xscvuxddp 1, [[CP32]]383 %0 = extractelement <4 x i32> %a, i32 2384 %1 = uitofp i32 %0 to double385 ret double %1386}387 388define double @conv2dlbTestui3(<4 x i32> %a) {389entry:390; CHECK-64-LABEL: conv2dlbTestui3391; CHECK-64: xxextractuw [[CP64:[0-9]+]], 34, 12392; CHECK-64: xscvuxddp 1, [[CP64]]393; CHECK-32-LABEL: conv2dlbTestui3394; CHECK-32: lfiwzx [[CP32:[0-9]+]], 0, 3395; CHECK-32: xscvuxddp 1, [[CP32]]396 %0 = extractelement <4 x i32> %a, i32 3397 %1 = uitofp i32 %0 to double398 ret double %1399}400 401; verify we don't crash for variable elem extract402define double @conv2dlbTestuiVar(<4 x i32> %a, i32 zeroext %elem) {403entry:404 %vecext = extractelement <4 x i32> %a, i32 %elem405 %conv = uitofp i32 %vecext to double406 ret double %conv407}408 409define <4 x float> @_Z10testInsEltILj0EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {410entry:411; CHECK-LABEL: _Z10testInsEltILj0EDv4_ffET0_S1_T1_412; CHECK: xscvdpspn 0, 1413; CHECK: xxsldwi 0, 0, 0, 3414; CHECK: xxinsertw 34, 0, 0415 %vecins = insertelement <4 x float> %a, float %b, i32 0416 ret <4 x float> %vecins417}418 419define <4 x float> @_Z10testInsEltILj1EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {420entry:421; CHECK-LABEL: _Z10testInsEltILj1EDv4_ffET0_S1_T1_422; CHECK: xscvdpspn 0, 1423; CHECK: xxsldwi 0, 0, 0, 3424; CHECK: xxinsertw 34, 0, 4425 %vecins = insertelement <4 x float> %a, float %b, i32 1426 ret <4 x float> %vecins427}428 429define <4 x float> @_Z10testInsEltILj2EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {430entry:431; CHECK-LABEL: _Z10testInsEltILj2EDv4_ffET0_S1_T1_432; CHECK: xscvdpspn 0, 1433; CHECK: xxsldwi 0, 0, 0, 3434; CHECK: xxinsertw 34, 0, 8435 %vecins = insertelement <4 x float> %a, float %b, i32 2436 ret <4 x float> %vecins437}438 439define <4 x float> @_Z10testInsEltILj3EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {440entry:441; CHECK-LABEL: _Z10testInsEltILj3EDv4_ffET0_S1_T1_442; CHECK: xscvdpspn 0, 1443; CHECK: xxsldwi 0, 0, 0, 3444; CHECK: xxinsertw 34, 0, 12445 %vecins = insertelement <4 x float> %a, float %b, i32 3446 ret <4 x float> %vecins447}448 449define <4 x i32> @_Z10testInsEltILj0EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {450entry:451; CHECK-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_452; CHECK: mtfprwz 0, 3453; CHECK: xxinsertw 34, 0, 0454 %vecins = insertelement <4 x i32> %a, i32 %b, i32 0455 ret <4 x i32> %vecins456}457 458define <4 x i32> @_Z10testInsEltILj1EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {459entry:460; CHECK-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_461; CHECK: mtfprwz 0, 3462; CHECK: xxinsertw 34, 0, 4463 %vecins = insertelement <4 x i32> %a, i32 %b, i32 1464 ret <4 x i32> %vecins465}466 467define <4 x i32> @_Z10testInsEltILj2EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {468entry:469; CHECK-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_470; CHECK: mtfprwz 0, 3471; CHECK: xxinsertw 34, 0, 8472 %vecins = insertelement <4 x i32> %a, i32 %b, i32 2473 ret <4 x i32> %vecins474}475 476define <4 x i32> @_Z10testInsEltILj3EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {477entry:478; CHECK-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_479; CHECK: mtfprwz 0, 3480; CHECK: xxinsertw 34, 0, 12481 %vecins = insertelement <4 x i32> %a, i32 %b, i32 3482 ret <4 x i32> %vecins483}484 485define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {486entry:487; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_488; CHECK: xxsldwi 0, 35, 35, 3489; CHECK: xxinsertw 34, 0, 0490 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>491 ret <4 x float> %vecins492}493 494define <4 x float> @_Z7testInsILj0ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {495entry:496; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_497; CHECK-NOT: xxsldwi498; CHECK: xxinsertw 34, 35, 0499 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 1, i32 5, i32 6, i32 7>500 ret <4 x float> %vecins501}502 503define <4 x float> @_Z7testInsILj0ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {504entry:505; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_506; CHECK: xxsldwi 0, 35, 35, 1507; CHECK: xxinsertw 34, 0, 0508 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 2, i32 5, i32 6, i32 7>509 ret <4 x float> %vecins510}511 512define <4 x float> @_Z7testInsILj0ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {513entry:514; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_515; CHECK: xxswapd 0, 35516; CHECK: xxinsertw 34, 0, 0517 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 3, i32 5, i32 6, i32 7>518 ret <4 x float> %vecins519}520 521define <4 x float> @_Z7testInsILj1ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {522entry:523; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_524; CHECK: xxsldwi 0, 35, 35, 3525; CHECK: xxinsertw 34, 0, 4526 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 0, i32 6, i32 7>527 ret <4 x float> %vecins528}529 530define <4 x float> @_Z7testInsILj1ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {531entry:532; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_533; CHECK-NOT: xxsldwi534; CHECK: xxinsertw 34, 35, 4535 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 7>536 ret <4 x float> %vecins537}538 539define <4 x float> @_Z7testInsILj1ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {540entry:541; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_542; CHECK: xxsldwi 0, 35, 35, 1543; CHECK: xxinsertw 34, 0, 4544 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 2, i32 6, i32 7>545 ret <4 x float> %vecins546}547 548define <4 x float> @_Z7testInsILj1ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {549entry:550; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_551; CHECK: xxswapd 0, 35552; CHECK: xxinsertw 34, 0, 4553 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 3, i32 6, i32 7>554 ret <4 x float> %vecins555}556 557define <4 x float> @_Z7testInsILj2ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {558entry:559; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_560; CHECK: xxsldwi 0, 35, 35, 3561; CHECK: xxinsertw 34, 0, 8562 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 0, i32 7>563 ret <4 x float> %vecins564}565 566define <4 x float> @_Z7testInsILj2ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {567entry:568; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_569; CHECK-NOT: xxsldwi570; CHECK: xxinsertw 34, 35, 8571 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 7>572 ret <4 x float> %vecins573}574 575define <4 x float> @_Z7testInsILj2ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {576entry:577; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_578; CHECK: xxsldwi 0, 35, 35, 1579; CHECK: xxinsertw 34, 0, 8580 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 7>581 ret <4 x float> %vecins582}583 584define <4 x float> @_Z7testInsILj2ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {585entry:586; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_587; CHECK: xxswapd 0, 35588; CHECK: xxinsertw 34, 0, 8589 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 3, i32 7>590 ret <4 x float> %vecins591}592 593define <4 x float> @_Z7testInsILj3ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {594entry:595; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_596; CHECK: xxsldwi 0, 35, 35, 3597; CHECK: xxinsertw 34, 0, 12598 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 0>599 ret <4 x float> %vecins600}601 602define <4 x float> @_Z7testInsILj3ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {603entry:604; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_605; CHECK-NOT: xxsldwi606; CHECK: xxinsertw 34, 35, 12607 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 1>608 ret <4 x float> %vecins609}610 611define <4 x float> @_Z7testInsILj3ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {612entry:613; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_614; CHECK: xxsldwi 0, 35, 35, 1615; CHECK: xxinsertw 34, 0, 12616 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 2>617 ret <4 x float> %vecins618}619 620define <4 x float> @_Z7testInsILj3ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {621entry:622; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_623; CHECK: xxswapd 0, 35624; CHECK: xxinsertw 34, 0, 12625 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 3>626 ret <4 x float> %vecins627}628 629define <4 x i32> @_Z7testInsILj0ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {630entry:631; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_632; CHECK: xxsldwi 0, 35, 35, 3633; CHECK: xxinsertw 34, 0, 0634 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>635 ret <4 x i32> %vecins636}637 638define <4 x i32> @_Z7testInsILj0ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {639entry:640; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_641; CHECK-NOT: xxsldwi642; CHECK: xxinsertw 34, 35, 0643 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 1, i32 5, i32 6, i32 7>644 ret <4 x i32> %vecins645}646 647define <4 x i32> @_Z7testInsILj0ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {648entry:649; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_650; CHECK: xxsldwi 0, 35, 35, 1651; CHECK: xxinsertw 34, 0, 0652 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 2, i32 5, i32 6, i32 7>653 ret <4 x i32> %vecins654}655 656define <4 x i32> @_Z7testInsILj0ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {657entry:658; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_659; CHECK: xxswapd 0, 35660; CHECK: xxinsertw 34, 0, 0661 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 3, i32 5, i32 6, i32 7>662 ret <4 x i32> %vecins663}664 665define <4 x i32> @_Z7testInsILj1ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {666entry:667; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_668; CHECK: xxsldwi 0, 35, 35, 3669; CHECK: xxinsertw 34, 0, 4670 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 0, i32 6, i32 7>671 ret <4 x i32> %vecins672}673 674define <4 x i32> @_Z7testInsILj1ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {675entry:676; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_677; CHECK-NOT: xxsldwi678; CHECK: xxinsertw 34, 35, 4679 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 7>680 ret <4 x i32> %vecins681}682 683define <4 x i32> @_Z7testInsILj1ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {684entry:685; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_686; CHECK: xxsldwi 0, 35, 35, 1687; CHECK: xxinsertw 34, 0, 4688 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 2, i32 6, i32 7>689 ret <4 x i32> %vecins690}691 692define <4 x i32> @_Z7testInsILj1ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {693entry:694; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_695; CHECK: xxswapd 0, 35696; CHECK: xxinsertw 34, 0, 4697 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 3, i32 6, i32 7>698 ret <4 x i32> %vecins699}700 701define <4 x i32> @_Z7testInsILj2ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {702entry:703; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_704; CHECK: xxsldwi 0, 35, 35, 3705; CHECK: xxinsertw 34, 0, 8706 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 0, i32 7>707 ret <4 x i32> %vecins708}709 710define <4 x i32> @_Z7testInsILj2ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {711entry:712; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_713; CHECK-NOT: xxsldwi714; CHECK: xxinsertw 34, 35, 8715 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 7>716 ret <4 x i32> %vecins717}718 719define <4 x i32> @_Z7testInsILj2ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {720entry:721; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_722; CHECK: xxsldwi 0, 35, 35, 1723; CHECK: xxinsertw 34, 0, 8724 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 7>725 ret <4 x i32> %vecins726}727 728define <4 x i32> @_Z7testInsILj2ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {729entry:730; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_731; CHECK: xxswapd 0, 35732; CHECK: xxinsertw 34, 0, 8733 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 3, i32 7>734 ret <4 x i32> %vecins735}736 737define <4 x i32> @_Z7testInsILj3ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {738entry:739; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_740; CHECK: xxsldwi 0, 35, 35, 3741; CHECK: xxinsertw 34, 0, 12742 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 0>743 ret <4 x i32> %vecins744}745 746define <4 x i32> @_Z7testInsILj3ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {747entry:748; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_749; CHECK-NOT: xxsldwi750; CHECK: xxinsertw 34, 35, 12751 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 1>752 ret <4 x i32> %vecins753}754 755define <4 x i32> @_Z7testInsILj3ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {756entry:757; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_758; CHECK: xxsldwi 0, 35, 35, 1759; CHECK: xxinsertw 34, 0, 12760 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 2>761 ret <4 x i32> %vecins762}763 764define <4 x i32> @_Z7testInsILj3ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {765entry:766; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_767; CHECK: xxswapd 0, 35768; CHECK: xxinsertw 34, 0, 12769 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 3>770 ret <4 x i32> %vecins771}772define <4 x float> @testSameVecEl0BE(<4 x float> %a) {773entry:774; CHECK-LABEL: testSameVecEl0BE775; CHECK: xxinsertw 34, 34, 0776 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 5, i32 1, i32 2, i32 3>777 ret <4 x float> %vecins778}779define <4 x float> @testSameVecEl2BE(<4 x float> %a) {780entry:781; CHECK-LABEL: testSameVecEl2BE782; CHECK: xxinsertw 34, 34, 8783 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 5, i32 3>784 ret <4 x float> %vecins785}786define <4 x float> @testSameVecEl3BE(<4 x float> %a) {787entry:788; CHECK-LABEL: testSameVecEl3BE789; CHECK: xxinsertw 34, 34, 12790 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 5>791 ret <4 x float> %vecins792}793define <4 x float> @insertVarF(<4 x float> %a, float %f, i32 %el) {794entry:795; CHECK-LABEL: insertVarF796; CHECK: stfsx 1,797; CHECK: lxv798 %vecins = insertelement <4 x float> %a, float %f, i32 %el799 ret <4 x float> %vecins800}801define <4 x i32> @insertVarI(<4 x i32> %a, i32 %i, i32 %el) {802entry:803; CHECK-LABEL: insertVarI804; CHECK: stwx805; CHECK: lxv806 %vecins = insertelement <4 x i32> %a, i32 %i, i32 %el807 ret <4 x i32> %vecins808}809