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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc --verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff \3; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | \4; RUN: FileCheck %s --check-prefixes=CHECK,CHECK325; RUN: llc --verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff \6; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | \7; RUN: FileCheck %s --check-prefixes=CHECK,CHECK648 9define ptr @lower_args(ptr %_0, i32 %0, i32 %1, i32 %2, i32 %3, ptr %4, ptr %5, i64 %6, i24 %7) {10; CHECK-LABEL: lower_args:11; CHECK: # %bb.0: # %entry12; CHECK-NEXT: blr13entry:14 ret ptr %_015}16 17define i32 @lower_args_withops_zeroext(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i24 %i) {18; CHECK32-LABEL: lower_args_withops_zeroext:19; CHECK32: # %bb.0: # %entry20; CHECK32-NEXT: lwz r3, 56(r1)21; CHECK32-NEXT: addi r3, r3, 25522; CHECK32-NEXT: clrlwi r3, r3, 823; CHECK32-NEXT: blr24;25; CHECK64-LABEL: lower_args_withops_zeroext:26; CHECK64: # %bb.0: # %entry27; CHECK64-NEXT: lwz r3, 116(r1)28; CHECK64-NEXT: addi r3, r3, 25529; CHECK64-NEXT: clrldi r3, r3, 4030; CHECK64-NEXT: blr31entry:32 %0 = add i24 %i, 25533 %1 = zext i24 %0 to i3234 ret i32 %135}36 37define i32 @lower_args_withops_signext(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i24 signext %i) {38; CHECK32-LABEL: lower_args_withops_signext:39; CHECK32: # %bb.0: # %entry40; CHECK32-NEXT: lwz r3, 56(r1)41; CHECK32-NEXT: slwi r3, r3, 842; CHECK32-NEXT: srawi r3, r3, 843; CHECK32-NEXT: slwi r3, r3, 844; CHECK32-NEXT: addi r3, r3, 2227245; CHECK32-NEXT: srawi r3, r3, 846; CHECK32-NEXT: blr47;48; CHECK64-LABEL: lower_args_withops_signext:49; CHECK64: # %bb.0: # %entry50; CHECK64-NEXT: lwz r3, 116(r1)51; CHECK64-NEXT: slwi r3, r3, 852; CHECK64-NEXT: srawi r3, r3, 853; CHECK64-NEXT: addi r3, r3, 8754; CHECK64-NEXT: sldi r3, r3, 4055; CHECK64-NEXT: sradi r3, r3, 4056; CHECK64-NEXT: blr57entry:58 %0 = add i24 %i, 8759 %1 = sext i24 %0 to i3260 ret i32 %161}62