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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff \3; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK-64,CHECK-64-OPT %s4; RUN: llc -O0 -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff \5; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK-64,CHECK-64-O0 %s6; RUN: llc -mcpu=pwr9 -mtriple=powerpc-ibm-aix-xcoff \7; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-32,CHECK-32-OPT8; RUN: llc -O0 -mcpu=pwr9 -mtriple=powerpc-ibm-aix-xcoff \9; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-32,CHECK-32-O010 11; The following testcases take one halfword element from the second vector and12; inserts it at various locations in the first vector13define <8 x i16> @shuffle_vector_halfword_0_8(<8 x i16> %a, <8 x i16> %b) {14; CHECK-64-LABEL: shuffle_vector_halfword_0_8:15; CHECK-64: # %bb.0: # %entry16; CHECK-64-NEXT: vsldoi 3, 3, 3, 1017; CHECK-64-NEXT: vinserth 2, 3, 018; CHECK-64-NEXT: blr19;20; CHECK-32-LABEL: shuffle_vector_halfword_0_8:21; CHECK-32: # %bb.0: # %entry22; CHECK-32-NEXT: vsldoi 3, 3, 3, 1023; CHECK-32-NEXT: vinserth 2, 3, 024; CHECK-32-NEXT: blr25entry:26 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>27 ret <8 x i16> %vecins28}29 30define <8 x i16> @shuffle_vector_halfword_1_15(<8 x i16> %a, <8 x i16> %b) {31; CHECK-64-LABEL: shuffle_vector_halfword_1_15:32; CHECK-64: # %bb.0: # %entry33; CHECK-64-NEXT: vsldoi 3, 3, 3, 834; CHECK-64-NEXT: vinserth 2, 3, 235; CHECK-64-NEXT: blr36;37; CHECK-32-LABEL: shuffle_vector_halfword_1_15:38; CHECK-32: # %bb.0: # %entry39; CHECK-32-NEXT: vsldoi 3, 3, 3, 840; CHECK-32-NEXT: vinserth 2, 3, 241; CHECK-32-NEXT: blr42entry:43 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 15, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>44 ret <8 x i16> %vecins45}46 47define <8 x i16> @shuffle_vector_halfword_2_9(<8 x i16> %a, <8 x i16> %b) {48; CHECK-64-LABEL: shuffle_vector_halfword_2_9:49; CHECK-64: # %bb.0: # %entry50; CHECK-64-NEXT: vsldoi 3, 3, 3, 1251; CHECK-64-NEXT: vinserth 2, 3, 452; CHECK-64-NEXT: blr53;54; CHECK-32-LABEL: shuffle_vector_halfword_2_9:55; CHECK-32: # %bb.0: # %entry56; CHECK-32-NEXT: vsldoi 3, 3, 3, 1257; CHECK-32-NEXT: vinserth 2, 3, 458; CHECK-32-NEXT: blr59entry:60 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 9, i32 3, i32 4, i32 5, i32 6, i32 7>61 ret <8 x i16> %vecins62}63 64define <8 x i16> @shuffle_vector_halfword_3_13(<8 x i16> %a, <8 x i16> %b) {65; CHECK-64-LABEL: shuffle_vector_halfword_3_13:66; CHECK-64: # %bb.0: # %entry67; CHECK-64-NEXT: vsldoi 3, 3, 3, 468; CHECK-64-NEXT: vinserth 2, 3, 669; CHECK-64-NEXT: blr70;71; CHECK-32-LABEL: shuffle_vector_halfword_3_13:72; CHECK-32: # %bb.0: # %entry73; CHECK-32-NEXT: vsldoi 3, 3, 3, 474; CHECK-32-NEXT: vinserth 2, 3, 675; CHECK-32-NEXT: blr76entry:77 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 13, i32 4, i32 5, i32 6, i32 7>78 ret <8 x i16> %vecins79}80 81define <8 x i16> @shuffle_vector_halfword_4_10(<8 x i16> %a, <8 x i16> %b) {82; CHECK-64-LABEL: shuffle_vector_halfword_4_10:83; CHECK-64: # %bb.0: # %entry84; CHECK-64-NEXT: vsldoi 3, 3, 3, 1485; CHECK-64-NEXT: vinserth 2, 3, 886; CHECK-64-NEXT: blr87;88; CHECK-32-LABEL: shuffle_vector_halfword_4_10:89; CHECK-32: # %bb.0: # %entry90; CHECK-32-NEXT: vsldoi 3, 3, 3, 1491; CHECK-32-NEXT: vinserth 2, 3, 892; CHECK-32-NEXT: blr93entry:94 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 10, i32 5, i32 6, i32 7>95 ret <8 x i16> %vecins96}97 98define <8 x i16> @shuffle_vector_halfword_5_14(<8 x i16> %a, <8 x i16> %b) {99; CHECK-64-LABEL: shuffle_vector_halfword_5_14:100; CHECK-64: # %bb.0: # %entry101; CHECK-64-NEXT: vsldoi 3, 3, 3, 6102; CHECK-64-NEXT: vinserth 2, 3, 10103; CHECK-64-NEXT: blr104;105; CHECK-32-LABEL: shuffle_vector_halfword_5_14:106; CHECK-32: # %bb.0: # %entry107; CHECK-32-NEXT: vsldoi 3, 3, 3, 6108; CHECK-32-NEXT: vinserth 2, 3, 10109; CHECK-32-NEXT: blr110entry:111 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 14, i32 6, i32 7>112 ret <8 x i16> %vecins113}114 115define <8 x i16> @shuffle_vector_halfword_6_11(<8 x i16> %a, <8 x i16> %b) {116; CHECK-64-LABEL: shuffle_vector_halfword_6_11:117; CHECK-64: # %bb.0: # %entry118; CHECK-64-NEXT: vinserth 2, 3, 12119; CHECK-64-NEXT: blr120;121; CHECK-32-LABEL: shuffle_vector_halfword_6_11:122; CHECK-32: # %bb.0: # %entry123; CHECK-32-NEXT: vinserth 2, 3, 12124; CHECK-32-NEXT: blr125entry:126 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 11, i32 7>127 ret <8 x i16> %vecins128}129 130define <8 x i16> @shuffle_vector_halfword_7_12(<8 x i16> %a, <8 x i16> %b) {131; CHECK-64-LABEL: shuffle_vector_halfword_7_12:132; CHECK-64: # %bb.0: # %entry133; CHECK-64-NEXT: vsldoi 3, 3, 3, 2134; CHECK-64-NEXT: vinserth 2, 3, 14135; CHECK-64-NEXT: blr136;137; CHECK-32-LABEL: shuffle_vector_halfword_7_12:138; CHECK-32: # %bb.0: # %entry139; CHECK-32-NEXT: vsldoi 3, 3, 3, 2140; CHECK-32-NEXT: vinserth 2, 3, 14141; CHECK-32-NEXT: blr142entry:143 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 12>144 ret <8 x i16> %vecins145}146 147define <8 x i16> @shuffle_vector_halfword_8_1(<8 x i16> %a, <8 x i16> %b) {148; CHECK-64-OPT-LABEL: shuffle_vector_halfword_8_1:149; CHECK-64-OPT: # %bb.0: # %entry150; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 12151; CHECK-64-OPT-NEXT: vinserth 3, 2, 0152; CHECK-64-OPT-NEXT: vmr 2, 3153; CHECK-64-OPT-NEXT: blr154;155; CHECK-64-O0-LABEL: shuffle_vector_halfword_8_1:156; CHECK-64-O0: # %bb.0: # %entry157; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill158; CHECK-64-O0-NEXT: vmr 3, 2159; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload160; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 12161; CHECK-64-O0-NEXT: vinserth 2, 3, 0162; CHECK-64-O0-NEXT: blr163;164; CHECK-32-OPT-LABEL: shuffle_vector_halfword_8_1:165; CHECK-32-OPT: # %bb.0: # %entry166; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 12167; CHECK-32-OPT-NEXT: vinserth 3, 2, 0168; CHECK-32-OPT-NEXT: vmr 2, 3169; CHECK-32-OPT-NEXT: blr170;171; CHECK-32-O0-LABEL: shuffle_vector_halfword_8_1:172; CHECK-32-O0: # %bb.0: # %entry173; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill174; CHECK-32-O0-NEXT: vmr 3, 2175; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload176; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 12177; CHECK-32-O0-NEXT: vinserth 2, 3, 0178; CHECK-32-O0-NEXT: blr179entry:180 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 1, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>181 ret <8 x i16> %vecins182}183 184; The following testcases take one halfword element from the first vector and185; inserts it at various locations in the second vector186define <8 x i16> @shuffle_vector_halfword_9_7(<8 x i16> %a, <8 x i16> %b) {187; CHECK-64-OPT-LABEL: shuffle_vector_halfword_9_7:188; CHECK-64-OPT: # %bb.0: # %entry189; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 8190; CHECK-64-OPT-NEXT: vinserth 3, 2, 2191; CHECK-64-OPT-NEXT: vmr 2, 3192; CHECK-64-OPT-NEXT: blr193;194; CHECK-64-O0-LABEL: shuffle_vector_halfword_9_7:195; CHECK-64-O0: # %bb.0: # %entry196; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill197; CHECK-64-O0-NEXT: vmr 3, 2198; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload199; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 8200; CHECK-64-O0-NEXT: vinserth 2, 3, 2201; CHECK-64-O0-NEXT: blr202;203; CHECK-32-OPT-LABEL: shuffle_vector_halfword_9_7:204; CHECK-32-OPT: # %bb.0: # %entry205; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 8206; CHECK-32-OPT-NEXT: vinserth 3, 2, 2207; CHECK-32-OPT-NEXT: vmr 2, 3208; CHECK-32-OPT-NEXT: blr209;210; CHECK-32-O0-LABEL: shuffle_vector_halfword_9_7:211; CHECK-32-O0: # %bb.0: # %entry212; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill213; CHECK-32-O0-NEXT: vmr 3, 2214; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload215; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 8216; CHECK-32-O0-NEXT: vinserth 2, 3, 2217; CHECK-32-O0-NEXT: blr218entry:219 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>220 ret <8 x i16> %vecins221}222 223define <8 x i16> @shuffle_vector_halfword_10_4(<8 x i16> %a, <8 x i16> %b) {224; CHECK-64-OPT-LABEL: shuffle_vector_halfword_10_4:225; CHECK-64-OPT: # %bb.0: # %entry226; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 2227; CHECK-64-OPT-NEXT: vinserth 3, 2, 4228; CHECK-64-OPT-NEXT: vmr 2, 3229; CHECK-64-OPT-NEXT: blr230;231; CHECK-64-O0-LABEL: shuffle_vector_halfword_10_4:232; CHECK-64-O0: # %bb.0: # %entry233; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill234; CHECK-64-O0-NEXT: vmr 3, 2235; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload236; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 2237; CHECK-64-O0-NEXT: vinserth 2, 3, 4238; CHECK-64-O0-NEXT: blr239;240; CHECK-32-OPT-LABEL: shuffle_vector_halfword_10_4:241; CHECK-32-OPT: # %bb.0: # %entry242; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 2243; CHECK-32-OPT-NEXT: vinserth 3, 2, 4244; CHECK-32-OPT-NEXT: vmr 2, 3245; CHECK-32-OPT-NEXT: blr246;247; CHECK-32-O0-LABEL: shuffle_vector_halfword_10_4:248; CHECK-32-O0: # %bb.0: # %entry249; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill250; CHECK-32-O0-NEXT: vmr 3, 2251; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload252; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 2253; CHECK-32-O0-NEXT: vinserth 2, 3, 4254; CHECK-32-O0-NEXT: blr255entry:256 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 4, i32 11, i32 12, i32 13, i32 14, i32 15>257 ret <8 x i16> %vecins258}259 260define <8 x i16> @shuffle_vector_halfword_11_2(<8 x i16> %a, <8 x i16> %b) {261; CHECK-64-OPT-LABEL: shuffle_vector_halfword_11_2:262; CHECK-64-OPT: # %bb.0: # %entry263; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 14264; CHECK-64-OPT-NEXT: vinserth 3, 2, 6265; CHECK-64-OPT-NEXT: vmr 2, 3266; CHECK-64-OPT-NEXT: blr267;268; CHECK-64-O0-LABEL: shuffle_vector_halfword_11_2:269; CHECK-64-O0: # %bb.0: # %entry270; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill271; CHECK-64-O0-NEXT: vmr 3, 2272; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload273; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 14274; CHECK-64-O0-NEXT: vinserth 2, 3, 6275; CHECK-64-O0-NEXT: blr276;277; CHECK-32-OPT-LABEL: shuffle_vector_halfword_11_2:278; CHECK-32-OPT: # %bb.0: # %entry279; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 14280; CHECK-32-OPT-NEXT: vinserth 3, 2, 6281; CHECK-32-OPT-NEXT: vmr 2, 3282; CHECK-32-OPT-NEXT: blr283;284; CHECK-32-O0-LABEL: shuffle_vector_halfword_11_2:285; CHECK-32-O0: # %bb.0: # %entry286; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill287; CHECK-32-O0-NEXT: vmr 3, 2288; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload289; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 14290; CHECK-32-O0-NEXT: vinserth 2, 3, 6291; CHECK-32-O0-NEXT: blr292entry:293 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 2, i32 12, i32 13, i32 14, i32 15>294 ret <8 x i16> %vecins295}296 297define <8 x i16> @shuffle_vector_halfword_12_6(<8 x i16> %a, <8 x i16> %b) {298; CHECK-64-OPT-LABEL: shuffle_vector_halfword_12_6:299; CHECK-64-OPT: # %bb.0: # %entry300; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 6301; CHECK-64-OPT-NEXT: vinserth 3, 2, 8302; CHECK-64-OPT-NEXT: vmr 2, 3303; CHECK-64-OPT-NEXT: blr304;305; CHECK-64-O0-LABEL: shuffle_vector_halfword_12_6:306; CHECK-64-O0: # %bb.0: # %entry307; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill308; CHECK-64-O0-NEXT: vmr 3, 2309; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload310; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 6311; CHECK-64-O0-NEXT: vinserth 2, 3, 8312; CHECK-64-O0-NEXT: blr313;314; CHECK-32-OPT-LABEL: shuffle_vector_halfword_12_6:315; CHECK-32-OPT: # %bb.0: # %entry316; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 6317; CHECK-32-OPT-NEXT: vinserth 3, 2, 8318; CHECK-32-OPT-NEXT: vmr 2, 3319; CHECK-32-OPT-NEXT: blr320;321; CHECK-32-O0-LABEL: shuffle_vector_halfword_12_6:322; CHECK-32-O0: # %bb.0: # %entry323; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill324; CHECK-32-O0-NEXT: vmr 3, 2325; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload326; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 6327; CHECK-32-O0-NEXT: vinserth 2, 3, 8328; CHECK-32-O0-NEXT: blr329entry:330 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 6, i32 13, i32 14, i32 15>331 ret <8 x i16> %vecins332}333 334define <8 x i16> @shuffle_vector_halfword_13_3(<8 x i16> %a, <8 x i16> %b) {335; CHECK-64-OPT-LABEL: shuffle_vector_halfword_13_3:336; CHECK-64-OPT: # %bb.0: # %entry337; CHECK-64-OPT-NEXT: vinserth 3, 2, 10338; CHECK-64-OPT-NEXT: vmr 2, 3339; CHECK-64-OPT-NEXT: blr340;341; CHECK-64-O0-LABEL: shuffle_vector_halfword_13_3:342; CHECK-64-O0: # %bb.0: # %entry343; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill344; CHECK-64-O0-NEXT: vmr 3, 2345; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload346; CHECK-64-O0-NEXT: vinserth 2, 3, 10347; CHECK-64-O0-NEXT: blr348;349; CHECK-32-OPT-LABEL: shuffle_vector_halfword_13_3:350; CHECK-32-OPT: # %bb.0: # %entry351; CHECK-32-OPT-NEXT: vinserth 3, 2, 10352; CHECK-32-OPT-NEXT: vmr 2, 3353; CHECK-32-OPT-NEXT: blr354;355; CHECK-32-O0-LABEL: shuffle_vector_halfword_13_3:356; CHECK-32-O0: # %bb.0: # %entry357; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill358; CHECK-32-O0-NEXT: vmr 3, 2359; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload360; CHECK-32-O0-NEXT: vinserth 2, 3, 10361; CHECK-32-O0-NEXT: blr362entry:363 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 3, i32 14, i32 15>364 ret <8 x i16> %vecins365}366 367define <8 x i16> @shuffle_vector_halfword_14_5(<8 x i16> %a, <8 x i16> %b) {368; CHECK-64-OPT-LABEL: shuffle_vector_halfword_14_5:369; CHECK-64-OPT: # %bb.0: # %entry370; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 4371; CHECK-64-OPT-NEXT: vinserth 3, 2, 12372; CHECK-64-OPT-NEXT: vmr 2, 3373; CHECK-64-OPT-NEXT: blr374;375; CHECK-64-O0-LABEL: shuffle_vector_halfword_14_5:376; CHECK-64-O0: # %bb.0: # %entry377; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill378; CHECK-64-O0-NEXT: vmr 3, 2379; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload380; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 4381; CHECK-64-O0-NEXT: vinserth 2, 3, 12382; CHECK-64-O0-NEXT: blr383;384; CHECK-32-OPT-LABEL: shuffle_vector_halfword_14_5:385; CHECK-32-OPT: # %bb.0: # %entry386; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 4387; CHECK-32-OPT-NEXT: vinserth 3, 2, 12388; CHECK-32-OPT-NEXT: vmr 2, 3389; CHECK-32-OPT-NEXT: blr390;391; CHECK-32-O0-LABEL: shuffle_vector_halfword_14_5:392; CHECK-32-O0: # %bb.0: # %entry393; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill394; CHECK-32-O0-NEXT: vmr 3, 2395; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload396; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 4397; CHECK-32-O0-NEXT: vinserth 2, 3, 12398; CHECK-32-O0-NEXT: blr399entry:400 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 5, i32 15>401 ret <8 x i16> %vecins402}403 404define <8 x i16> @shuffle_vector_halfword_15_0(<8 x i16> %a, <8 x i16> %b) {405; CHECK-64-OPT-LABEL: shuffle_vector_halfword_15_0:406; CHECK-64-OPT: # %bb.0: # %entry407; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 10408; CHECK-64-OPT-NEXT: vinserth 3, 2, 14409; CHECK-64-OPT-NEXT: vmr 2, 3410; CHECK-64-OPT-NEXT: blr411;412; CHECK-64-O0-LABEL: shuffle_vector_halfword_15_0:413; CHECK-64-O0: # %bb.0: # %entry414; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill415; CHECK-64-O0-NEXT: vmr 3, 2416; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload417; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 10418; CHECK-64-O0-NEXT: vinserth 2, 3, 14419; CHECK-64-O0-NEXT: blr420;421; CHECK-32-OPT-LABEL: shuffle_vector_halfword_15_0:422; CHECK-32-OPT: # %bb.0: # %entry423; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 10424; CHECK-32-OPT-NEXT: vinserth 3, 2, 14425; CHECK-32-OPT-NEXT: vmr 2, 3426; CHECK-32-OPT-NEXT: blr427;428; CHECK-32-O0-LABEL: shuffle_vector_halfword_15_0:429; CHECK-32-O0: # %bb.0: # %entry430; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill431; CHECK-32-O0-NEXT: vmr 3, 2432; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload433; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 10434; CHECK-32-O0-NEXT: vinserth 2, 3, 14435; CHECK-32-O0-NEXT: blr436entry:437 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0>438 ret <8 x i16> %vecins439}440 441; The following testcases use the same vector in both arguments of the442; shufflevector. If halfword element 3 in BE mode(or 4 in LE mode) is the one443; we're attempting to insert, then we can use the vector insert instruction444define <8 x i16> @shuffle_vector_halfword_0_4(<8 x i16> %a) {445; CHECK-64-LABEL: shuffle_vector_halfword_0_4:446; CHECK-64: # %bb.0: # %entry447; CHECK-64-NEXT: ld 3, L..C0(2) # %const.0448; CHECK-64-NEXT: lxv 0, 0(3)449; CHECK-64-NEXT: xxperm 34, 34, 0450; CHECK-64-NEXT: blr451;452; CHECK-32-LABEL: shuffle_vector_halfword_0_4:453; CHECK-32: # %bb.0: # %entry454; CHECK-32-NEXT: lwz 3, L..C0(2) # %const.0455; CHECK-32-NEXT: lxv 0, 0(3)456; CHECK-32-NEXT: xxperm 34, 34, 0457; CHECK-32-NEXT: blr458entry:459 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 4, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>460 ret <8 x i16> %vecins461}462 463define <8 x i16> @shuffle_vector_halfword_1_3(<8 x i16> %a) {464; CHECK-64-LABEL: shuffle_vector_halfword_1_3:465; CHECK-64: # %bb.0: # %entry466; CHECK-64-NEXT: vinserth 2, 2, 2467; CHECK-64-NEXT: blr468;469; CHECK-32-LABEL: shuffle_vector_halfword_1_3:470; CHECK-32: # %bb.0: # %entry471; CHECK-32-NEXT: vinserth 2, 2, 2472; CHECK-32-NEXT: blr473entry:474 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 3, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>475 ret <8 x i16> %vecins476}477 478define <8 x i16> @shuffle_vector_halfword_2_3(<8 x i16> %a) {479; CHECK-64-LABEL: shuffle_vector_halfword_2_3:480; CHECK-64: # %bb.0: # %entry481; CHECK-64-NEXT: vinserth 2, 2, 4482; CHECK-64-NEXT: blr483;484; CHECK-32-LABEL: shuffle_vector_halfword_2_3:485; CHECK-32: # %bb.0: # %entry486; CHECK-32-NEXT: vinserth 2, 2, 4487; CHECK-32-NEXT: blr488entry:489 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 3, i32 3, i32 4, i32 5, i32 6, i32 7>490 ret <8 x i16> %vecins491}492 493define <8 x i16> @shuffle_vector_halfword_3_4(<8 x i16> %a) {494; CHECK-64-LABEL: shuffle_vector_halfword_3_4:495; CHECK-64: # %bb.0: # %entry496; CHECK-64-NEXT: ld 3, L..C1(2) # %const.0497; CHECK-64-NEXT: lxv 0, 0(3)498; CHECK-64-NEXT: xxperm 34, 34, 0499; CHECK-64-NEXT: blr500;501; CHECK-32-LABEL: shuffle_vector_halfword_3_4:502; CHECK-32: # %bb.0: # %entry503; CHECK-32-NEXT: lwz 3, L..C1(2) # %const.0504; CHECK-32-NEXT: lxv 0, 0(3)505; CHECK-32-NEXT: xxperm 34, 34, 0506; CHECK-32-NEXT: blr507entry:508 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 4, i32 4, i32 5, i32 6, i32 7>509 ret <8 x i16> %vecins510}511 512define <8 x i16> @shuffle_vector_halfword_4_3(<8 x i16> %a) {513; CHECK-64-LABEL: shuffle_vector_halfword_4_3:514; CHECK-64: # %bb.0: # %entry515; CHECK-64-NEXT: vinserth 2, 2, 8516; CHECK-64-NEXT: blr517;518; CHECK-32-LABEL: shuffle_vector_halfword_4_3:519; CHECK-32: # %bb.0: # %entry520; CHECK-32-NEXT: vinserth 2, 2, 8521; CHECK-32-NEXT: blr522entry:523 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 3, i32 5, i32 6, i32 7>524 ret <8 x i16> %vecins525}526 527define <8 x i16> @shuffle_vector_halfword_5_3(<8 x i16> %a) {528; CHECK-64-LABEL: shuffle_vector_halfword_5_3:529; CHECK-64: # %bb.0: # %entry530; CHECK-64-NEXT: vinserth 2, 2, 10531; CHECK-64-NEXT: blr532;533; CHECK-32-LABEL: shuffle_vector_halfword_5_3:534; CHECK-32: # %bb.0: # %entry535; CHECK-32-NEXT: vinserth 2, 2, 10536; CHECK-32-NEXT: blr537entry:538 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 3, i32 6, i32 7>539 ret <8 x i16> %vecins540}541 542define <8 x i16> @shuffle_vector_halfword_6_4(<8 x i16> %a) {543; CHECK-64-LABEL: shuffle_vector_halfword_6_4:544; CHECK-64: # %bb.0: # %entry545; CHECK-64-NEXT: ld 3, L..C2(2) # %const.0546; CHECK-64-NEXT: lxv 0, 0(3)547; CHECK-64-NEXT: xxperm 34, 34, 0548; CHECK-64-NEXT: blr549;550; CHECK-32-LABEL: shuffle_vector_halfword_6_4:551; CHECK-32: # %bb.0: # %entry552; CHECK-32-NEXT: lwz 3, L..C2(2) # %const.0553; CHECK-32-NEXT: lxv 0, 0(3)554; CHECK-32-NEXT: xxperm 34, 34, 0555; CHECK-32-NEXT: blr556entry:557 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 4, i32 7>558 ret <8 x i16> %vecins559}560 561define <8 x i16> @shuffle_vector_halfword_7_4(<8 x i16> %a) {562; CHECK-64-LABEL: shuffle_vector_halfword_7_4:563; CHECK-64: # %bb.0: # %entry564; CHECK-64-NEXT: ld 3, L..C3(2) # %const.0565; CHECK-64-NEXT: lxv 0, 0(3)566; CHECK-64-NEXT: xxperm 34, 34, 0567; CHECK-64-NEXT: blr568;569; CHECK-32-LABEL: shuffle_vector_halfword_7_4:570; CHECK-32: # %bb.0: # %entry571; CHECK-32-NEXT: lwz 3, L..C3(2) # %const.0572; CHECK-32-NEXT: lxv 0, 0(3)573; CHECK-32-NEXT: xxperm 34, 34, 0574; CHECK-32-NEXT: blr575entry:576 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 4>577 ret <8 x i16> %vecins578}579 580; The following testcases take one byte element from the second vector and581; inserts it at various locations in the first vector582define <16 x i8> @shuffle_vector_byte_0_16(<16 x i8> %a, <16 x i8> %b) {583; CHECK-64-LABEL: shuffle_vector_byte_0_16:584; CHECK-64: # %bb.0: # %entry585; CHECK-64-NEXT: vsldoi 3, 3, 3, 9586; CHECK-64-NEXT: vinsertb 2, 3, 0587; CHECK-64-NEXT: blr588;589; CHECK-32-LABEL: shuffle_vector_byte_0_16:590; CHECK-32: # %bb.0: # %entry591; CHECK-32-NEXT: vsldoi 3, 3, 3, 9592; CHECK-32-NEXT: vinsertb 2, 3, 0593; CHECK-32-NEXT: blr594entry:595 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>596 ret <16 x i8> %vecins597}598 599define <16 x i8> @shuffle_vector_byte_1_25(<16 x i8> %a, <16 x i8> %b) {600; CHECK-64-LABEL: shuffle_vector_byte_1_25:601; CHECK-64: # %bb.0: # %entry602; CHECK-64-NEXT: vsldoi 3, 3, 3, 2603; CHECK-64-NEXT: vinsertb 2, 3, 1604; CHECK-64-NEXT: blr605;606; CHECK-32-LABEL: shuffle_vector_byte_1_25:607; CHECK-32: # %bb.0: # %entry608; CHECK-32-NEXT: vsldoi 3, 3, 3, 2609; CHECK-32-NEXT: vinsertb 2, 3, 1610; CHECK-32-NEXT: blr611entry:612 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 25, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>613 ret <16 x i8> %vecins614}615 616define <16 x i8> @shuffle_vector_byte_2_18(<16 x i8> %a, <16 x i8> %b) {617; CHECK-64-LABEL: shuffle_vector_byte_2_18:618; CHECK-64: # %bb.0: # %entry619; CHECK-64-NEXT: vsldoi 3, 3, 3, 11620; CHECK-64-NEXT: vinsertb 2, 3, 2621; CHECK-64-NEXT: blr622;623; CHECK-32-LABEL: shuffle_vector_byte_2_18:624; CHECK-32: # %bb.0: # %entry625; CHECK-32-NEXT: vsldoi 3, 3, 3, 11626; CHECK-32-NEXT: vinsertb 2, 3, 2627; CHECK-32-NEXT: blr628entry:629 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 18, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>630 ret <16 x i8> %vecins631}632 633define <16 x i8> @shuffle_vector_byte_3_27(<16 x i8> %a, <16 x i8> %b) {634; CHECK-64-LABEL: shuffle_vector_byte_3_27:635; CHECK-64: # %bb.0: # %entry636; CHECK-64-NEXT: vsldoi 3, 3, 3, 4637; CHECK-64-NEXT: vinsertb 2, 3, 3638; CHECK-64-NEXT: blr639;640; CHECK-32-LABEL: shuffle_vector_byte_3_27:641; CHECK-32: # %bb.0: # %entry642; CHECK-32-NEXT: vsldoi 3, 3, 3, 4643; CHECK-32-NEXT: vinsertb 2, 3, 3644; CHECK-32-NEXT: blr645entry:646 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 27, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>647 ret <16 x i8> %vecins648}649 650define <16 x i8> @shuffle_vector_byte_4_20(<16 x i8> %a, <16 x i8> %b) {651; CHECK-64-LABEL: shuffle_vector_byte_4_20:652; CHECK-64: # %bb.0: # %entry653; CHECK-64-NEXT: vsldoi 3, 3, 3, 13654; CHECK-64-NEXT: vinsertb 2, 3, 4655; CHECK-64-NEXT: blr656;657; CHECK-32-LABEL: shuffle_vector_byte_4_20:658; CHECK-32: # %bb.0: # %entry659; CHECK-32-NEXT: vsldoi 3, 3, 3, 13660; CHECK-32-NEXT: vinsertb 2, 3, 4661; CHECK-32-NEXT: blr662entry:663 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>664 ret <16 x i8> %vecins665}666 667define <16 x i8> @shuffle_vector_byte_5_29(<16 x i8> %a, <16 x i8> %b) {668; CHECK-64-LABEL: shuffle_vector_byte_5_29:669; CHECK-64: # %bb.0: # %entry670; CHECK-64-NEXT: vsldoi 3, 3, 3, 6671; CHECK-64-NEXT: vinsertb 2, 3, 5672; CHECK-64-NEXT: blr673;674; CHECK-32-LABEL: shuffle_vector_byte_5_29:675; CHECK-32: # %bb.0: # %entry676; CHECK-32-NEXT: vsldoi 3, 3, 3, 6677; CHECK-32-NEXT: vinsertb 2, 3, 5678; CHECK-32-NEXT: blr679entry:680 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 29, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>681 ret <16 x i8> %vecins682}683 684define <16 x i8> @shuffle_vector_byte_6_22(<16 x i8> %a, <16 x i8> %b) {685; CHECK-64-LABEL: shuffle_vector_byte_6_22:686; CHECK-64: # %bb.0: # %entry687; CHECK-64-NEXT: vsldoi 3, 3, 3, 15688; CHECK-64-NEXT: vinsertb 2, 3, 6689; CHECK-64-NEXT: blr690;691; CHECK-32-LABEL: shuffle_vector_byte_6_22:692; CHECK-32: # %bb.0: # %entry693; CHECK-32-NEXT: vsldoi 3, 3, 3, 15694; CHECK-32-NEXT: vinsertb 2, 3, 6695; CHECK-32-NEXT: blr696entry:697 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 22, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>698 ret <16 x i8> %vecins699}700 701define <16 x i8> @shuffle_vector_byte_7_31(<16 x i8> %a, <16 x i8> %b) {702; CHECK-64-LABEL: shuffle_vector_byte_7_31:703; CHECK-64: # %bb.0: # %entry704; CHECK-64-NEXT: vsldoi 3, 3, 3, 8705; CHECK-64-NEXT: vinsertb 2, 3, 7706; CHECK-64-NEXT: blr707;708; CHECK-32-LABEL: shuffle_vector_byte_7_31:709; CHECK-32: # %bb.0: # %entry710; CHECK-32-NEXT: vsldoi 3, 3, 3, 8711; CHECK-32-NEXT: vinsertb 2, 3, 7712; CHECK-32-NEXT: blr713entry:714 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 31, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>715 ret <16 x i8> %vecins716}717 718define <16 x i8> @shuffle_vector_byte_8_24(<16 x i8> %a, <16 x i8> %b) {719; CHECK-64-LABEL: shuffle_vector_byte_8_24:720; CHECK-64: # %bb.0: # %entry721; CHECK-64-NEXT: vsldoi 3, 3, 3, 1722; CHECK-64-NEXT: vinsertb 2, 3, 8723; CHECK-64-NEXT: blr724;725; CHECK-32-LABEL: shuffle_vector_byte_8_24:726; CHECK-32: # %bb.0: # %entry727; CHECK-32-NEXT: vsldoi 3, 3, 3, 1728; CHECK-32-NEXT: vinsertb 2, 3, 8729; CHECK-32-NEXT: blr730entry:731 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>732 ret <16 x i8> %vecins733}734 735define <16 x i8> @shuffle_vector_byte_9_17(<16 x i8> %a, <16 x i8> %b) {736; CHECK-64-LABEL: shuffle_vector_byte_9_17:737; CHECK-64: # %bb.0: # %entry738; CHECK-64-NEXT: vsldoi 3, 3, 3, 10739; CHECK-64-NEXT: vinsertb 2, 3, 9740; CHECK-64-NEXT: blr741;742; CHECK-32-LABEL: shuffle_vector_byte_9_17:743; CHECK-32: # %bb.0: # %entry744; CHECK-32-NEXT: vsldoi 3, 3, 3, 10745; CHECK-32-NEXT: vinsertb 2, 3, 9746; CHECK-32-NEXT: blr747entry:748 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 17, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>749 ret <16 x i8> %vecins750}751 752define <16 x i8> @shuffle_vector_byte_10_26(<16 x i8> %a, <16 x i8> %b) {753; CHECK-64-LABEL: shuffle_vector_byte_10_26:754; CHECK-64: # %bb.0: # %entry755; CHECK-64-NEXT: vsldoi 3, 3, 3, 3756; CHECK-64-NEXT: vinsertb 2, 3, 10757; CHECK-64-NEXT: blr758;759; CHECK-32-LABEL: shuffle_vector_byte_10_26:760; CHECK-32: # %bb.0: # %entry761; CHECK-32-NEXT: vsldoi 3, 3, 3, 3762; CHECK-32-NEXT: vinsertb 2, 3, 10763; CHECK-32-NEXT: blr764entry:765 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 26, i32 11, i32 12, i32 13, i32 14, i32 15>766 ret <16 x i8> %vecins767}768 769define <16 x i8> @shuffle_vector_byte_11_19(<16 x i8> %a, <16 x i8> %b) {770; CHECK-64-LABEL: shuffle_vector_byte_11_19:771; CHECK-64: # %bb.0: # %entry772; CHECK-64-NEXT: vsldoi 3, 3, 3, 12773; CHECK-64-NEXT: vinsertb 2, 3, 11774; CHECK-64-NEXT: blr775;776; CHECK-32-LABEL: shuffle_vector_byte_11_19:777; CHECK-32: # %bb.0: # %entry778; CHECK-32-NEXT: vsldoi 3, 3, 3, 12779; CHECK-32-NEXT: vinsertb 2, 3, 11780; CHECK-32-NEXT: blr781entry:782 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 19, i32 12, i32 13, i32 14, i32 15>783 ret <16 x i8> %vecins784}785 786define <16 x i8> @shuffle_vector_byte_12_28(<16 x i8> %a, <16 x i8> %b) {787; CHECK-64-LABEL: shuffle_vector_byte_12_28:788; CHECK-64: # %bb.0: # %entry789; CHECK-64-NEXT: vsldoi 3, 3, 3, 5790; CHECK-64-NEXT: vinsertb 2, 3, 12791; CHECK-64-NEXT: blr792;793; CHECK-32-LABEL: shuffle_vector_byte_12_28:794; CHECK-32: # %bb.0: # %entry795; CHECK-32-NEXT: vsldoi 3, 3, 3, 5796; CHECK-32-NEXT: vinsertb 2, 3, 12797; CHECK-32-NEXT: blr798entry:799 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 28, i32 13, i32 14, i32 15>800 ret <16 x i8> %vecins801}802 803define <16 x i8> @shuffle_vector_byte_13_21(<16 x i8> %a, <16 x i8> %b) {804; CHECK-64-LABEL: shuffle_vector_byte_13_21:805; CHECK-64: # %bb.0: # %entry806; CHECK-64-NEXT: vsldoi 3, 3, 3, 14807; CHECK-64-NEXT: vinsertb 2, 3, 13808; CHECK-64-NEXT: blr809;810; CHECK-32-LABEL: shuffle_vector_byte_13_21:811; CHECK-32: # %bb.0: # %entry812; CHECK-32-NEXT: vsldoi 3, 3, 3, 14813; CHECK-32-NEXT: vinsertb 2, 3, 13814; CHECK-32-NEXT: blr815entry:816 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 21, i32 14, i32 15>817 ret <16 x i8> %vecins818}819 820define <16 x i8> @shuffle_vector_byte_14_30(<16 x i8> %a, <16 x i8> %b) {821; CHECK-64-LABEL: shuffle_vector_byte_14_30:822; CHECK-64: # %bb.0: # %entry823; CHECK-64-NEXT: vsldoi 3, 3, 3, 7824; CHECK-64-NEXT: vinsertb 2, 3, 14825; CHECK-64-NEXT: blr826;827; CHECK-32-LABEL: shuffle_vector_byte_14_30:828; CHECK-32: # %bb.0: # %entry829; CHECK-32-NEXT: vsldoi 3, 3, 3, 7830; CHECK-32-NEXT: vinsertb 2, 3, 14831; CHECK-32-NEXT: blr832entry:833 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 30, i32 15>834 ret <16 x i8> %vecins835}836 837define <16 x i8> @shuffle_vector_byte_15_23(<16 x i8> %a, <16 x i8> %b) {838; CHECK-64-LABEL: shuffle_vector_byte_15_23:839; CHECK-64: # %bb.0: # %entry840; CHECK-64-NEXT: vinsertb 2, 3, 15841; CHECK-64-NEXT: blr842;843; CHECK-32-LABEL: shuffle_vector_byte_15_23:844; CHECK-32: # %bb.0: # %entry845; CHECK-32-NEXT: vinsertb 2, 3, 15846; CHECK-32-NEXT: blr847entry:848 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 23>849 ret <16 x i8> %vecins850}851 852; The following testcases take one byte element from the first vector and853; inserts it at various locations in the second vector854define <16 x i8> @shuffle_vector_byte_16_8(<16 x i8> %a, <16 x i8> %b) {855; CHECK-64-OPT-LABEL: shuffle_vector_byte_16_8:856; CHECK-64-OPT: # %bb.0: # %entry857; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 1858; CHECK-64-OPT-NEXT: vinsertb 3, 2, 0859; CHECK-64-OPT-NEXT: vmr 2, 3860; CHECK-64-OPT-NEXT: blr861;862; CHECK-64-O0-LABEL: shuffle_vector_byte_16_8:863; CHECK-64-O0: # %bb.0: # %entry864; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill865; CHECK-64-O0-NEXT: vmr 3, 2866; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload867; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 1868; CHECK-64-O0-NEXT: vinsertb 2, 3, 0869; CHECK-64-O0-NEXT: blr870;871; CHECK-32-OPT-LABEL: shuffle_vector_byte_16_8:872; CHECK-32-OPT: # %bb.0: # %entry873; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 1874; CHECK-32-OPT-NEXT: vinsertb 3, 2, 0875; CHECK-32-OPT-NEXT: vmr 2, 3876; CHECK-32-OPT-NEXT: blr877;878; CHECK-32-O0-LABEL: shuffle_vector_byte_16_8:879; CHECK-32-O0: # %bb.0: # %entry880; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill881; CHECK-32-O0-NEXT: vmr 3, 2882; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload883; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 1884; CHECK-32-O0-NEXT: vinsertb 2, 3, 0885; CHECK-32-O0-NEXT: blr886entry:887 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>888 ret <16 x i8> %vecins889}890 891define <16 x i8> @shuffle_vector_byte_17_1(<16 x i8> %a, <16 x i8> %b) {892; CHECK-64-OPT-LABEL: shuffle_vector_byte_17_1:893; CHECK-64-OPT: # %bb.0: # %entry894; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 10895; CHECK-64-OPT-NEXT: vinsertb 3, 2, 1896; CHECK-64-OPT-NEXT: vmr 2, 3897; CHECK-64-OPT-NEXT: blr898;899; CHECK-64-O0-LABEL: shuffle_vector_byte_17_1:900; CHECK-64-O0: # %bb.0: # %entry901; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill902; CHECK-64-O0-NEXT: vmr 3, 2903; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload904; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 10905; CHECK-64-O0-NEXT: vinsertb 2, 3, 1906; CHECK-64-O0-NEXT: blr907;908; CHECK-32-OPT-LABEL: shuffle_vector_byte_17_1:909; CHECK-32-OPT: # %bb.0: # %entry910; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 10911; CHECK-32-OPT-NEXT: vinsertb 3, 2, 1912; CHECK-32-OPT-NEXT: vmr 2, 3913; CHECK-32-OPT-NEXT: blr914;915; CHECK-32-O0-LABEL: shuffle_vector_byte_17_1:916; CHECK-32-O0: # %bb.0: # %entry917; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill918; CHECK-32-O0-NEXT: vmr 3, 2919; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload920; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 10921; CHECK-32-O0-NEXT: vinsertb 2, 3, 1922; CHECK-32-O0-NEXT: blr923entry:924 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>925 ret <16 x i8> %vecins926}927 928define <16 x i8> @shuffle_vector_byte_18_10(<16 x i8> %a, <16 x i8> %b) {929; CHECK-64-OPT-LABEL: shuffle_vector_byte_18_10:930; CHECK-64-OPT: # %bb.0: # %entry931; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 3932; CHECK-64-OPT-NEXT: vinsertb 3, 2, 2933; CHECK-64-OPT-NEXT: vmr 2, 3934; CHECK-64-OPT-NEXT: blr935;936; CHECK-64-O0-LABEL: shuffle_vector_byte_18_10:937; CHECK-64-O0: # %bb.0: # %entry938; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill939; CHECK-64-O0-NEXT: vmr 3, 2940; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload941; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 3942; CHECK-64-O0-NEXT: vinsertb 2, 3, 2943; CHECK-64-O0-NEXT: blr944;945; CHECK-32-OPT-LABEL: shuffle_vector_byte_18_10:946; CHECK-32-OPT: # %bb.0: # %entry947; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 3948; CHECK-32-OPT-NEXT: vinsertb 3, 2, 2949; CHECK-32-OPT-NEXT: vmr 2, 3950; CHECK-32-OPT-NEXT: blr951;952; CHECK-32-O0-LABEL: shuffle_vector_byte_18_10:953; CHECK-32-O0: # %bb.0: # %entry954; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill955; CHECK-32-O0-NEXT: vmr 3, 2956; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload957; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 3958; CHECK-32-O0-NEXT: vinsertb 2, 3, 2959; CHECK-32-O0-NEXT: blr960entry:961 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 10, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>962 ret <16 x i8> %vecins963}964 965define <16 x i8> @shuffle_vector_byte_19_3(<16 x i8> %a, <16 x i8> %b) {966; CHECK-64-OPT-LABEL: shuffle_vector_byte_19_3:967; CHECK-64-OPT: # %bb.0: # %entry968; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 12969; CHECK-64-OPT-NEXT: vinsertb 3, 2, 3970; CHECK-64-OPT-NEXT: vmr 2, 3971; CHECK-64-OPT-NEXT: blr972;973; CHECK-64-O0-LABEL: shuffle_vector_byte_19_3:974; CHECK-64-O0: # %bb.0: # %entry975; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill976; CHECK-64-O0-NEXT: vmr 3, 2977; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload978; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 12979; CHECK-64-O0-NEXT: vinsertb 2, 3, 3980; CHECK-64-O0-NEXT: blr981;982; CHECK-32-OPT-LABEL: shuffle_vector_byte_19_3:983; CHECK-32-OPT: # %bb.0: # %entry984; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 12985; CHECK-32-OPT-NEXT: vinsertb 3, 2, 3986; CHECK-32-OPT-NEXT: vmr 2, 3987; CHECK-32-OPT-NEXT: blr988;989; CHECK-32-O0-LABEL: shuffle_vector_byte_19_3:990; CHECK-32-O0: # %bb.0: # %entry991; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill992; CHECK-32-O0-NEXT: vmr 3, 2993; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload994; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 12995; CHECK-32-O0-NEXT: vinsertb 2, 3, 3996; CHECK-32-O0-NEXT: blr997entry:998 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>999 ret <16 x i8> %vecins1000}1001 1002define <16 x i8> @shuffle_vector_byte_20_12(<16 x i8> %a, <16 x i8> %b) {1003; CHECK-64-OPT-LABEL: shuffle_vector_byte_20_12:1004; CHECK-64-OPT: # %bb.0: # %entry1005; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 51006; CHECK-64-OPT-NEXT: vinsertb 3, 2, 41007; CHECK-64-OPT-NEXT: vmr 2, 31008; CHECK-64-OPT-NEXT: blr1009;1010; CHECK-64-O0-LABEL: shuffle_vector_byte_20_12:1011; CHECK-64-O0: # %bb.0: # %entry1012; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1013; CHECK-64-O0-NEXT: vmr 3, 21014; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1015; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 51016; CHECK-64-O0-NEXT: vinsertb 2, 3, 41017; CHECK-64-O0-NEXT: blr1018;1019; CHECK-32-OPT-LABEL: shuffle_vector_byte_20_12:1020; CHECK-32-OPT: # %bb.0: # %entry1021; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 51022; CHECK-32-OPT-NEXT: vinsertb 3, 2, 41023; CHECK-32-OPT-NEXT: vmr 2, 31024; CHECK-32-OPT-NEXT: blr1025;1026; CHECK-32-O0-LABEL: shuffle_vector_byte_20_12:1027; CHECK-32-O0: # %bb.0: # %entry1028; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1029; CHECK-32-O0-NEXT: vmr 3, 21030; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1031; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 51032; CHECK-32-O0-NEXT: vinsertb 2, 3, 41033; CHECK-32-O0-NEXT: blr1034entry:1035 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 12, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>1036 ret <16 x i8> %vecins1037}1038 1039define <16 x i8> @shuffle_vector_byte_21_5(<16 x i8> %a, <16 x i8> %b) {1040; CHECK-64-OPT-LABEL: shuffle_vector_byte_21_5:1041; CHECK-64-OPT: # %bb.0: # %entry1042; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 141043; CHECK-64-OPT-NEXT: vinsertb 3, 2, 51044; CHECK-64-OPT-NEXT: vmr 2, 31045; CHECK-64-OPT-NEXT: blr1046;1047; CHECK-64-O0-LABEL: shuffle_vector_byte_21_5:1048; CHECK-64-O0: # %bb.0: # %entry1049; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1050; CHECK-64-O0-NEXT: vmr 3, 21051; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1052; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 141053; CHECK-64-O0-NEXT: vinsertb 2, 3, 51054; CHECK-64-O0-NEXT: blr1055;1056; CHECK-32-OPT-LABEL: shuffle_vector_byte_21_5:1057; CHECK-32-OPT: # %bb.0: # %entry1058; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 141059; CHECK-32-OPT-NEXT: vinsertb 3, 2, 51060; CHECK-32-OPT-NEXT: vmr 2, 31061; CHECK-32-OPT-NEXT: blr1062;1063; CHECK-32-O0-LABEL: shuffle_vector_byte_21_5:1064; CHECK-32-O0: # %bb.0: # %entry1065; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1066; CHECK-32-O0-NEXT: vmr 3, 21067; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1068; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 141069; CHECK-32-O0-NEXT: vinsertb 2, 3, 51070; CHECK-32-O0-NEXT: blr1071entry:1072 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 5, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>1073 ret <16 x i8> %vecins1074}1075 1076define <16 x i8> @shuffle_vector_byte_22_14(<16 x i8> %a, <16 x i8> %b) {1077; CHECK-64-OPT-LABEL: shuffle_vector_byte_22_14:1078; CHECK-64-OPT: # %bb.0: # %entry1079; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 71080; CHECK-64-OPT-NEXT: vinsertb 3, 2, 61081; CHECK-64-OPT-NEXT: vmr 2, 31082; CHECK-64-OPT-NEXT: blr1083;1084; CHECK-64-O0-LABEL: shuffle_vector_byte_22_14:1085; CHECK-64-O0: # %bb.0: # %entry1086; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1087; CHECK-64-O0-NEXT: vmr 3, 21088; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1089; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 71090; CHECK-64-O0-NEXT: vinsertb 2, 3, 61091; CHECK-64-O0-NEXT: blr1092;1093; CHECK-32-OPT-LABEL: shuffle_vector_byte_22_14:1094; CHECK-32-OPT: # %bb.0: # %entry1095; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 71096; CHECK-32-OPT-NEXT: vinsertb 3, 2, 61097; CHECK-32-OPT-NEXT: vmr 2, 31098; CHECK-32-OPT-NEXT: blr1099;1100; CHECK-32-O0-LABEL: shuffle_vector_byte_22_14:1101; CHECK-32-O0: # %bb.0: # %entry1102; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1103; CHECK-32-O0-NEXT: vmr 3, 21104; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1105; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 71106; CHECK-32-O0-NEXT: vinsertb 2, 3, 61107; CHECK-32-O0-NEXT: blr1108entry:1109 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 14, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>1110 ret <16 x i8> %vecins1111}1112 1113define <16 x i8> @shuffle_vector_byte_23_7(<16 x i8> %a, <16 x i8> %b) {1114; CHECK-64-OPT-LABEL: shuffle_vector_byte_23_7:1115; CHECK-64-OPT: # %bb.0: # %entry1116; CHECK-64-OPT-NEXT: vinsertb 3, 2, 71117; CHECK-64-OPT-NEXT: vmr 2, 31118; CHECK-64-OPT-NEXT: blr1119;1120; CHECK-64-O0-LABEL: shuffle_vector_byte_23_7:1121; CHECK-64-O0: # %bb.0: # %entry1122; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1123; CHECK-64-O0-NEXT: vmr 3, 21124; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1125; CHECK-64-O0-NEXT: vinsertb 2, 3, 71126; CHECK-64-O0-NEXT: blr1127;1128; CHECK-32-OPT-LABEL: shuffle_vector_byte_23_7:1129; CHECK-32-OPT: # %bb.0: # %entry1130; CHECK-32-OPT-NEXT: vinsertb 3, 2, 71131; CHECK-32-OPT-NEXT: vmr 2, 31132; CHECK-32-OPT-NEXT: blr1133;1134; CHECK-32-O0-LABEL: shuffle_vector_byte_23_7:1135; CHECK-32-O0: # %bb.0: # %entry1136; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1137; CHECK-32-O0-NEXT: vmr 3, 21138; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1139; CHECK-32-O0-NEXT: vinsertb 2, 3, 71140; CHECK-32-O0-NEXT: blr1141entry:1142 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>1143 ret <16 x i8> %vecins1144}1145 1146define <16 x i8> @shuffle_vector_byte_24_0(<16 x i8> %a, <16 x i8> %b) {1147; CHECK-64-OPT-LABEL: shuffle_vector_byte_24_0:1148; CHECK-64-OPT: # %bb.0: # %entry1149; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 91150; CHECK-64-OPT-NEXT: vinsertb 3, 2, 81151; CHECK-64-OPT-NEXT: vmr 2, 31152; CHECK-64-OPT-NEXT: blr1153;1154; CHECK-64-O0-LABEL: shuffle_vector_byte_24_0:1155; CHECK-64-O0: # %bb.0: # %entry1156; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1157; CHECK-64-O0-NEXT: vmr 3, 21158; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1159; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 91160; CHECK-64-O0-NEXT: vinsertb 2, 3, 81161; CHECK-64-O0-NEXT: blr1162;1163; CHECK-32-OPT-LABEL: shuffle_vector_byte_24_0:1164; CHECK-32-OPT: # %bb.0: # %entry1165; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 91166; CHECK-32-OPT-NEXT: vinsertb 3, 2, 81167; CHECK-32-OPT-NEXT: vmr 2, 31168; CHECK-32-OPT-NEXT: blr1169;1170; CHECK-32-O0-LABEL: shuffle_vector_byte_24_0:1171; CHECK-32-O0: # %bb.0: # %entry1172; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1173; CHECK-32-O0-NEXT: vmr 3, 21174; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1175; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 91176; CHECK-32-O0-NEXT: vinsertb 2, 3, 81177; CHECK-32-O0-NEXT: blr1178entry:1179 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 0, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>1180 ret <16 x i8> %vecins1181}1182 1183define <16 x i8> @shuffle_vector_byte_25_9(<16 x i8> %a, <16 x i8> %b) {1184; CHECK-64-OPT-LABEL: shuffle_vector_byte_25_9:1185; CHECK-64-OPT: # %bb.0: # %entry1186; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 21187; CHECK-64-OPT-NEXT: vinsertb 3, 2, 91188; CHECK-64-OPT-NEXT: vmr 2, 31189; CHECK-64-OPT-NEXT: blr1190;1191; CHECK-64-O0-LABEL: shuffle_vector_byte_25_9:1192; CHECK-64-O0: # %bb.0: # %entry1193; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1194; CHECK-64-O0-NEXT: vmr 3, 21195; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1196; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 21197; CHECK-64-O0-NEXT: vinsertb 2, 3, 91198; CHECK-64-O0-NEXT: blr1199;1200; CHECK-32-OPT-LABEL: shuffle_vector_byte_25_9:1201; CHECK-32-OPT: # %bb.0: # %entry1202; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 21203; CHECK-32-OPT-NEXT: vinsertb 3, 2, 91204; CHECK-32-OPT-NEXT: vmr 2, 31205; CHECK-32-OPT-NEXT: blr1206;1207; CHECK-32-O0-LABEL: shuffle_vector_byte_25_9:1208; CHECK-32-O0: # %bb.0: # %entry1209; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1210; CHECK-32-O0-NEXT: vmr 3, 21211; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1212; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 21213; CHECK-32-O0-NEXT: vinsertb 2, 3, 91214; CHECK-32-O0-NEXT: blr1215entry:1216 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 9, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>1217 ret <16 x i8> %vecins1218}1219 1220define <16 x i8> @shuffle_vector_byte_26_2(<16 x i8> %a, <16 x i8> %b) {1221; CHECK-64-OPT-LABEL: shuffle_vector_byte_26_2:1222; CHECK-64-OPT: # %bb.0: # %entry1223; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 111224; CHECK-64-OPT-NEXT: vinsertb 3, 2, 101225; CHECK-64-OPT-NEXT: vmr 2, 31226; CHECK-64-OPT-NEXT: blr1227;1228; CHECK-64-O0-LABEL: shuffle_vector_byte_26_2:1229; CHECK-64-O0: # %bb.0: # %entry1230; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1231; CHECK-64-O0-NEXT: vmr 3, 21232; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1233; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 111234; CHECK-64-O0-NEXT: vinsertb 2, 3, 101235; CHECK-64-O0-NEXT: blr1236;1237; CHECK-32-OPT-LABEL: shuffle_vector_byte_26_2:1238; CHECK-32-OPT: # %bb.0: # %entry1239; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 111240; CHECK-32-OPT-NEXT: vinsertb 3, 2, 101241; CHECK-32-OPT-NEXT: vmr 2, 31242; CHECK-32-OPT-NEXT: blr1243;1244; CHECK-32-O0-LABEL: shuffle_vector_byte_26_2:1245; CHECK-32-O0: # %bb.0: # %entry1246; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1247; CHECK-32-O0-NEXT: vmr 3, 21248; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1249; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 111250; CHECK-32-O0-NEXT: vinsertb 2, 3, 101251; CHECK-32-O0-NEXT: blr1252entry:1253 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 2, i32 27, i32 28, i32 29, i32 30, i32 31>1254 ret <16 x i8> %vecins1255}1256 1257define <16 x i8> @shuffle_vector_byte_27_11(<16 x i8> %a, <16 x i8> %b) {1258; CHECK-64-OPT-LABEL: shuffle_vector_byte_27_11:1259; CHECK-64-OPT: # %bb.0: # %entry1260; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 41261; CHECK-64-OPT-NEXT: vinsertb 3, 2, 111262; CHECK-64-OPT-NEXT: vmr 2, 31263; CHECK-64-OPT-NEXT: blr1264;1265; CHECK-64-O0-LABEL: shuffle_vector_byte_27_11:1266; CHECK-64-O0: # %bb.0: # %entry1267; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1268; CHECK-64-O0-NEXT: vmr 3, 21269; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1270; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 41271; CHECK-64-O0-NEXT: vinsertb 2, 3, 111272; CHECK-64-O0-NEXT: blr1273;1274; CHECK-32-OPT-LABEL: shuffle_vector_byte_27_11:1275; CHECK-32-OPT: # %bb.0: # %entry1276; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 41277; CHECK-32-OPT-NEXT: vinsertb 3, 2, 111278; CHECK-32-OPT-NEXT: vmr 2, 31279; CHECK-32-OPT-NEXT: blr1280;1281; CHECK-32-O0-LABEL: shuffle_vector_byte_27_11:1282; CHECK-32-O0: # %bb.0: # %entry1283; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1284; CHECK-32-O0-NEXT: vmr 3, 21285; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1286; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 41287; CHECK-32-O0-NEXT: vinsertb 2, 3, 111288; CHECK-32-O0-NEXT: blr1289entry:1290 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 11, i32 28, i32 29, i32 30, i32 31>1291 ret <16 x i8> %vecins1292}1293 1294define <16 x i8> @shuffle_vector_byte_28_4(<16 x i8> %a, <16 x i8> %b) {1295; CHECK-64-OPT-LABEL: shuffle_vector_byte_28_4:1296; CHECK-64-OPT: # %bb.0: # %entry1297; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 131298; CHECK-64-OPT-NEXT: vinsertb 3, 2, 121299; CHECK-64-OPT-NEXT: vmr 2, 31300; CHECK-64-OPT-NEXT: blr1301;1302; CHECK-64-O0-LABEL: shuffle_vector_byte_28_4:1303; CHECK-64-O0: # %bb.0: # %entry1304; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1305; CHECK-64-O0-NEXT: vmr 3, 21306; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1307; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 131308; CHECK-64-O0-NEXT: vinsertb 2, 3, 121309; CHECK-64-O0-NEXT: blr1310;1311; CHECK-32-OPT-LABEL: shuffle_vector_byte_28_4:1312; CHECK-32-OPT: # %bb.0: # %entry1313; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 131314; CHECK-32-OPT-NEXT: vinsertb 3, 2, 121315; CHECK-32-OPT-NEXT: vmr 2, 31316; CHECK-32-OPT-NEXT: blr1317;1318; CHECK-32-O0-LABEL: shuffle_vector_byte_28_4:1319; CHECK-32-O0: # %bb.0: # %entry1320; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1321; CHECK-32-O0-NEXT: vmr 3, 21322; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1323; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 131324; CHECK-32-O0-NEXT: vinsertb 2, 3, 121325; CHECK-32-O0-NEXT: blr1326entry:1327 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 4, i32 29, i32 30, i32 31>1328 ret <16 x i8> %vecins1329}1330 1331define <16 x i8> @shuffle_vector_byte_29_13(<16 x i8> %a, <16 x i8> %b) {1332; CHECK-64-OPT-LABEL: shuffle_vector_byte_29_13:1333; CHECK-64-OPT: # %bb.0: # %entry1334; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 61335; CHECK-64-OPT-NEXT: vinsertb 3, 2, 131336; CHECK-64-OPT-NEXT: vmr 2, 31337; CHECK-64-OPT-NEXT: blr1338;1339; CHECK-64-O0-LABEL: shuffle_vector_byte_29_13:1340; CHECK-64-O0: # %bb.0: # %entry1341; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1342; CHECK-64-O0-NEXT: vmr 3, 21343; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1344; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 61345; CHECK-64-O0-NEXT: vinsertb 2, 3, 131346; CHECK-64-O0-NEXT: blr1347;1348; CHECK-32-OPT-LABEL: shuffle_vector_byte_29_13:1349; CHECK-32-OPT: # %bb.0: # %entry1350; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 61351; CHECK-32-OPT-NEXT: vinsertb 3, 2, 131352; CHECK-32-OPT-NEXT: vmr 2, 31353; CHECK-32-OPT-NEXT: blr1354;1355; CHECK-32-O0-LABEL: shuffle_vector_byte_29_13:1356; CHECK-32-O0: # %bb.0: # %entry1357; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1358; CHECK-32-O0-NEXT: vmr 3, 21359; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1360; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 61361; CHECK-32-O0-NEXT: vinsertb 2, 3, 131362; CHECK-32-O0-NEXT: blr1363entry:1364 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 13, i32 30, i32 31>1365 ret <16 x i8> %vecins1366}1367 1368define <16 x i8> @shuffle_vector_byte_30_6(<16 x i8> %a, <16 x i8> %b) {1369; CHECK-64-OPT-LABEL: shuffle_vector_byte_30_6:1370; CHECK-64-OPT: # %bb.0: # %entry1371; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 151372; CHECK-64-OPT-NEXT: vinsertb 3, 2, 141373; CHECK-64-OPT-NEXT: vmr 2, 31374; CHECK-64-OPT-NEXT: blr1375;1376; CHECK-64-O0-LABEL: shuffle_vector_byte_30_6:1377; CHECK-64-O0: # %bb.0: # %entry1378; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1379; CHECK-64-O0-NEXT: vmr 3, 21380; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1381; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 151382; CHECK-64-O0-NEXT: vinsertb 2, 3, 141383; CHECK-64-O0-NEXT: blr1384;1385; CHECK-32-OPT-LABEL: shuffle_vector_byte_30_6:1386; CHECK-32-OPT: # %bb.0: # %entry1387; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 151388; CHECK-32-OPT-NEXT: vinsertb 3, 2, 141389; CHECK-32-OPT-NEXT: vmr 2, 31390; CHECK-32-OPT-NEXT: blr1391;1392; CHECK-32-O0-LABEL: shuffle_vector_byte_30_6:1393; CHECK-32-O0: # %bb.0: # %entry1394; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1395; CHECK-32-O0-NEXT: vmr 3, 21396; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1397; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 151398; CHECK-32-O0-NEXT: vinsertb 2, 3, 141399; CHECK-32-O0-NEXT: blr1400entry:1401 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 6, i32 31>1402 ret <16 x i8> %vecins1403}1404 1405define <16 x i8> @shuffle_vector_byte_31_15(<16 x i8> %a, <16 x i8> %b) {1406; CHECK-64-OPT-LABEL: shuffle_vector_byte_31_15:1407; CHECK-64-OPT: # %bb.0: # %entry1408; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 81409; CHECK-64-OPT-NEXT: vinsertb 3, 2, 151410; CHECK-64-OPT-NEXT: vmr 2, 31411; CHECK-64-OPT-NEXT: blr1412;1413; CHECK-64-O0-LABEL: shuffle_vector_byte_31_15:1414; CHECK-64-O0: # %bb.0: # %entry1415; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1416; CHECK-64-O0-NEXT: vmr 3, 21417; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1418; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 81419; CHECK-64-O0-NEXT: vinsertb 2, 3, 151420; CHECK-64-O0-NEXT: blr1421;1422; CHECK-32-OPT-LABEL: shuffle_vector_byte_31_15:1423; CHECK-32-OPT: # %bb.0: # %entry1424; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 81425; CHECK-32-OPT-NEXT: vinsertb 3, 2, 151426; CHECK-32-OPT-NEXT: vmr 2, 31427; CHECK-32-OPT-NEXT: blr1428;1429; CHECK-32-O0-LABEL: shuffle_vector_byte_31_15:1430; CHECK-32-O0: # %bb.0: # %entry1431; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1432; CHECK-32-O0-NEXT: vmr 3, 21433; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1434; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 81435; CHECK-32-O0-NEXT: vinsertb 2, 3, 151436; CHECK-32-O0-NEXT: blr1437entry:1438 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 15>1439 ret <16 x i8> %vecins1440}1441 1442; The following testcases use the same vector in both arguments of the1443; shufflevector. If byte element 7 in BE mode(or 8 in LE mode) is the one1444; we're attempting to insert, then we can use the vector insert instruction1445define <16 x i8> @shuffle_vector_byte_0_7(<16 x i8> %a) {1446; CHECK-64-LABEL: shuffle_vector_byte_0_7:1447; CHECK-64: # %bb.0: # %entry1448; CHECK-64-NEXT: vinsertb 2, 2, 01449; CHECK-64-NEXT: blr1450;1451; CHECK-32-LABEL: shuffle_vector_byte_0_7:1452; CHECK-32: # %bb.0: # %entry1453; CHECK-32-NEXT: vinsertb 2, 2, 01454; CHECK-32-NEXT: blr1455entry:1456 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 7, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1457 ret <16 x i8> %vecins1458}1459 1460define <16 x i8> @shuffle_vector_byte_1_8(<16 x i8> %a) {1461; CHECK-64-LABEL: shuffle_vector_byte_1_8:1462; CHECK-64: # %bb.0: # %entry1463; CHECK-64-NEXT: ld 3, L..C4(2) # %const.01464; CHECK-64-NEXT: lxv 0, 0(3)1465; CHECK-64-NEXT: xxperm 34, 34, 01466; CHECK-64-NEXT: blr1467;1468; CHECK-32-LABEL: shuffle_vector_byte_1_8:1469; CHECK-32: # %bb.0: # %entry1470; CHECK-32-NEXT: lwz 3, L..C4(2) # %const.01471; CHECK-32-NEXT: lxv 0, 0(3)1472; CHECK-32-NEXT: xxperm 34, 34, 01473; CHECK-32-NEXT: blr1474entry:1475 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 8, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1476 ret <16 x i8> %vecins1477}1478 1479define <16 x i8> @shuffle_vector_byte_2_8(<16 x i8> %a) {1480; CHECK-64-LABEL: shuffle_vector_byte_2_8:1481; CHECK-64: # %bb.0: # %entry1482; CHECK-64-NEXT: ld 3, L..C5(2) # %const.01483; CHECK-64-NEXT: lxv 0, 0(3)1484; CHECK-64-NEXT: xxperm 34, 34, 01485; CHECK-64-NEXT: blr1486;1487; CHECK-32-LABEL: shuffle_vector_byte_2_8:1488; CHECK-32: # %bb.0: # %entry1489; CHECK-32-NEXT: lwz 3, L..C5(2) # %const.01490; CHECK-32-NEXT: lxv 0, 0(3)1491; CHECK-32-NEXT: xxperm 34, 34, 01492; CHECK-32-NEXT: blr1493entry:1494 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 8, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1495 ret <16 x i8> %vecins1496}1497 1498define <16 x i8> @shuffle_vector_byte_3_7(<16 x i8> %a) {1499; CHECK-64-LABEL: shuffle_vector_byte_3_7:1500; CHECK-64: # %bb.0: # %entry1501; CHECK-64-NEXT: vinsertb 2, 2, 31502; CHECK-64-NEXT: blr1503;1504; CHECK-32-LABEL: shuffle_vector_byte_3_7:1505; CHECK-32: # %bb.0: # %entry1506; CHECK-32-NEXT: vinsertb 2, 2, 31507; CHECK-32-NEXT: blr1508entry:1509 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 7, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1510 ret <16 x i8> %vecins1511}1512 1513define <16 x i8> @shuffle_vector_byte_4_7(<16 x i8> %a) {1514; CHECK-64-LABEL: shuffle_vector_byte_4_7:1515; CHECK-64: # %bb.0: # %entry1516; CHECK-64-NEXT: vinsertb 2, 2, 41517; CHECK-64-NEXT: blr1518;1519; CHECK-32-LABEL: shuffle_vector_byte_4_7:1520; CHECK-32: # %bb.0: # %entry1521; CHECK-32-NEXT: vinsertb 2, 2, 41522; CHECK-32-NEXT: blr1523entry:1524 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 7, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1525 ret <16 x i8> %vecins1526}1527 1528define <16 x i8> @shuffle_vector_byte_5_8(<16 x i8> %a) {1529; CHECK-64-LABEL: shuffle_vector_byte_5_8:1530; CHECK-64: # %bb.0: # %entry1531; CHECK-64-NEXT: ld 3, L..C6(2) # %const.01532; CHECK-64-NEXT: lxv 0, 0(3)1533; CHECK-64-NEXT: xxperm 34, 34, 01534; CHECK-64-NEXT: blr1535;1536; CHECK-32-LABEL: shuffle_vector_byte_5_8:1537; CHECK-32: # %bb.0: # %entry1538; CHECK-32-NEXT: lwz 3, L..C6(2) # %const.01539; CHECK-32-NEXT: lxv 0, 0(3)1540; CHECK-32-NEXT: xxperm 34, 34, 01541; CHECK-32-NEXT: blr1542entry:1543 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 8, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1544 ret <16 x i8> %vecins1545}1546 1547define <16 x i8> @shuffle_vector_byte_6_8(<16 x i8> %a) {1548; CHECK-64-LABEL: shuffle_vector_byte_6_8:1549; CHECK-64: # %bb.0: # %entry1550; CHECK-64-NEXT: ld 3, L..C7(2) # %const.01551; CHECK-64-NEXT: lxv 0, 0(3)1552; CHECK-64-NEXT: xxperm 34, 34, 01553; CHECK-64-NEXT: blr1554;1555; CHECK-32-LABEL: shuffle_vector_byte_6_8:1556; CHECK-32: # %bb.0: # %entry1557; CHECK-32-NEXT: lwz 3, L..C7(2) # %const.01558; CHECK-32-NEXT: lxv 0, 0(3)1559; CHECK-32-NEXT: xxperm 34, 34, 01560; CHECK-32-NEXT: blr1561entry:1562 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1563 ret <16 x i8> %vecins1564}1565 1566define <16 x i8> @shuffle_vector_byte_7_8(<16 x i8> %a) {1567; CHECK-64-LABEL: shuffle_vector_byte_7_8:1568; CHECK-64: # %bb.0: # %entry1569; CHECK-64-NEXT: ld 3, L..C8(2) # %const.01570; CHECK-64-NEXT: lxv 0, 0(3)1571; CHECK-64-NEXT: xxperm 34, 34, 01572; CHECK-64-NEXT: blr1573;1574; CHECK-32-LABEL: shuffle_vector_byte_7_8:1575; CHECK-32: # %bb.0: # %entry1576; CHECK-32-NEXT: lwz 3, L..C8(2) # %const.01577; CHECK-32-NEXT: lxv 0, 0(3)1578; CHECK-32-NEXT: xxperm 34, 34, 01579; CHECK-32-NEXT: blr1580entry:1581 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 8, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1582 ret <16 x i8> %vecins1583}1584 1585define <16 x i8> @shuffle_vector_byte_8_7(<16 x i8> %a) {1586; CHECK-64-LABEL: shuffle_vector_byte_8_7:1587; CHECK-64: # %bb.0: # %entry1588; CHECK-64-NEXT: vinsertb 2, 2, 81589; CHECK-64-NEXT: blr1590;1591; CHECK-32-LABEL: shuffle_vector_byte_8_7:1592; CHECK-32: # %bb.0: # %entry1593; CHECK-32-NEXT: vinsertb 2, 2, 81594; CHECK-32-NEXT: blr1595entry:1596 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 7, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1597 ret <16 x i8> %vecins1598}1599 1600define <16 x i8> @shuffle_vector_byte_9_7(<16 x i8> %a) {1601; CHECK-64-LABEL: shuffle_vector_byte_9_7:1602; CHECK-64: # %bb.0: # %entry1603; CHECK-64-NEXT: vinsertb 2, 2, 91604; CHECK-64-NEXT: blr1605;1606; CHECK-32-LABEL: shuffle_vector_byte_9_7:1607; CHECK-32: # %bb.0: # %entry1608; CHECK-32-NEXT: vinsertb 2, 2, 91609; CHECK-32-NEXT: blr1610entry:1611 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1612 ret <16 x i8> %vecins1613}1614 1615define <16 x i8> @shuffle_vector_byte_10_7(<16 x i8> %a) {1616; CHECK-64-LABEL: shuffle_vector_byte_10_7:1617; CHECK-64: # %bb.0: # %entry1618; CHECK-64-NEXT: vinsertb 2, 2, 101619; CHECK-64-NEXT: blr1620;1621; CHECK-32-LABEL: shuffle_vector_byte_10_7:1622; CHECK-32: # %bb.0: # %entry1623; CHECK-32-NEXT: vinsertb 2, 2, 101624; CHECK-32-NEXT: blr1625entry:1626 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 7, i32 11, i32 12, i32 13, i32 14, i32 15>1627 ret <16 x i8> %vecins1628}1629 1630define <16 x i8> @shuffle_vector_byte_11_8(<16 x i8> %a) {1631; CHECK-64-LABEL: shuffle_vector_byte_11_8:1632; CHECK-64: # %bb.0: # %entry1633; CHECK-64-NEXT: ld 3, L..C9(2) # %const.01634; CHECK-64-NEXT: lxv 0, 0(3)1635; CHECK-64-NEXT: xxperm 34, 34, 01636; CHECK-64-NEXT: blr1637;1638; CHECK-32-LABEL: shuffle_vector_byte_11_8:1639; CHECK-32: # %bb.0: # %entry1640; CHECK-32-NEXT: lwz 3, L..C9(2) # %const.01641; CHECK-32-NEXT: lxv 0, 0(3)1642; CHECK-32-NEXT: xxperm 34, 34, 01643; CHECK-32-NEXT: blr1644entry:1645 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 8, i32 12, i32 13, i32 14, i32 15>1646 ret <16 x i8> %vecins1647}1648 1649define <16 x i8> @shuffle_vector_byte_12_8(<16 x i8> %a) {1650; CHECK-64-LABEL: shuffle_vector_byte_12_8:1651; CHECK-64: # %bb.0: # %entry1652; CHECK-64-NEXT: ld 3, L..C10(2) # %const.01653; CHECK-64-NEXT: lxv 0, 0(3)1654; CHECK-64-NEXT: xxperm 34, 34, 01655; CHECK-64-NEXT: blr1656;1657; CHECK-32-LABEL: shuffle_vector_byte_12_8:1658; CHECK-32: # %bb.0: # %entry1659; CHECK-32-NEXT: lwz 3, L..C10(2) # %const.01660; CHECK-32-NEXT: lxv 0, 0(3)1661; CHECK-32-NEXT: xxperm 34, 34, 01662; CHECK-32-NEXT: blr1663entry:1664 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 8, i32 13, i32 14, i32 15>1665 ret <16 x i8> %vecins1666}1667 1668define <16 x i8> @shuffle_vector_byte_13_7(<16 x i8> %a) {1669; CHECK-64-LABEL: shuffle_vector_byte_13_7:1670; CHECK-64: # %bb.0: # %entry1671; CHECK-64-NEXT: vinsertb 2, 2, 131672; CHECK-64-NEXT: blr1673;1674; CHECK-32-LABEL: shuffle_vector_byte_13_7:1675; CHECK-32: # %bb.0: # %entry1676; CHECK-32-NEXT: vinsertb 2, 2, 131677; CHECK-32-NEXT: blr1678entry:1679 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 7, i32 14, i32 15>1680 ret <16 x i8> %vecins1681}1682 1683define <16 x i8> @shuffle_vector_byte_14_7(<16 x i8> %a) {1684; CHECK-64-LABEL: shuffle_vector_byte_14_7:1685; CHECK-64: # %bb.0: # %entry1686; CHECK-64-NEXT: vinsertb 2, 2, 141687; CHECK-64-NEXT: blr1688;1689; CHECK-32-LABEL: shuffle_vector_byte_14_7:1690; CHECK-32: # %bb.0: # %entry1691; CHECK-32-NEXT: vinsertb 2, 2, 141692; CHECK-32-NEXT: blr1693entry:1694 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 7, i32 15>1695 ret <16 x i8> %vecins1696}1697 1698define <16 x i8> @shuffle_vector_byte_15_8(<16 x i8> %a) {1699; CHECK-64-LABEL: shuffle_vector_byte_15_8:1700; CHECK-64: # %bb.0: # %entry1701; CHECK-64-NEXT: ld 3, L..C11(2) # %const.01702; CHECK-64-NEXT: lxv 0, 0(3)1703; CHECK-64-NEXT: xxperm 34, 34, 01704; CHECK-64-NEXT: blr1705;1706; CHECK-32-LABEL: shuffle_vector_byte_15_8:1707; CHECK-32: # %bb.0: # %entry1708; CHECK-32-NEXT: lwz 3, L..C11(2) # %const.01709; CHECK-32-NEXT: lxv 0, 0(3)1710; CHECK-32-NEXT: xxperm 34, 34, 01711; CHECK-32-NEXT: blr1712entry:1713 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 8>1714 ret <16 x i8> %vecins1715}1716 1717; The following tests try to insert one halfword element into the vector. We1718; should always be using the 'vinserth' instruction.1719define <8 x i16> @insert_halfword_0(<8 x i16> %a, i16 %b) {1720; CHECK-64-OPT-LABEL: insert_halfword_0:1721; CHECK-64-OPT: # %bb.0: # %entry1722; CHECK-64-OPT-NEXT: mtvsrwz 35, 31723; CHECK-64-OPT-NEXT: vinserth 2, 3, 01724; CHECK-64-OPT-NEXT: blr1725;1726; CHECK-64-O0-LABEL: insert_halfword_0:1727; CHECK-64-O0: # %bb.0: # %entry1728; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x31729; CHECK-64-O0-NEXT: mtfprwz 0, 31730; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 01731; CHECK-64-O0-NEXT: vinserth 2, 3, 01732; CHECK-64-O0-NEXT: blr1733;1734; CHECK-32-OPT-LABEL: insert_halfword_0:1735; CHECK-32-OPT: # %bb.0: # %entry1736; CHECK-32-OPT-NEXT: mtvsrwz 35, 31737; CHECK-32-OPT-NEXT: vinserth 2, 3, 01738; CHECK-32-OPT-NEXT: blr1739;1740; CHECK-32-O0-LABEL: insert_halfword_0:1741; CHECK-32-O0: # %bb.0: # %entry1742; CHECK-32-O0-NEXT: # kill: def $r4 killed $r31743; CHECK-32-O0-NEXT: mtfprwz 0, 31744; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 01745; CHECK-32-O0-NEXT: vinserth 2, 3, 01746; CHECK-32-O0-NEXT: blr1747entry:1748 %vecins = insertelement <8 x i16> %a, i16 %b, i32 01749 ret <8 x i16> %vecins1750}1751 1752define <8 x i16> @insert_halfword_1(<8 x i16> %a, i16 %b) {1753; CHECK-64-OPT-LABEL: insert_halfword_1:1754; CHECK-64-OPT: # %bb.0: # %entry1755; CHECK-64-OPT-NEXT: mtvsrwz 35, 31756; CHECK-64-OPT-NEXT: vinserth 2, 3, 21757; CHECK-64-OPT-NEXT: blr1758;1759; CHECK-64-O0-LABEL: insert_halfword_1:1760; CHECK-64-O0: # %bb.0: # %entry1761; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x31762; CHECK-64-O0-NEXT: mtfprwz 0, 31763; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 01764; CHECK-64-O0-NEXT: vinserth 2, 3, 21765; CHECK-64-O0-NEXT: blr1766;1767; CHECK-32-OPT-LABEL: insert_halfword_1:1768; CHECK-32-OPT: # %bb.0: # %entry1769; CHECK-32-OPT-NEXT: mtvsrwz 35, 31770; CHECK-32-OPT-NEXT: vinserth 2, 3, 21771; CHECK-32-OPT-NEXT: blr1772;1773; CHECK-32-O0-LABEL: insert_halfword_1:1774; CHECK-32-O0: # %bb.0: # %entry1775; CHECK-32-O0-NEXT: # kill: def $r4 killed $r31776; CHECK-32-O0-NEXT: mtfprwz 0, 31777; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 01778; CHECK-32-O0-NEXT: vinserth 2, 3, 21779; CHECK-32-O0-NEXT: blr1780entry:1781 %vecins = insertelement <8 x i16> %a, i16 %b, i32 11782 ret <8 x i16> %vecins1783}1784 1785define <8 x i16> @insert_halfword_2(<8 x i16> %a, i16 %b) {1786; CHECK-64-OPT-LABEL: insert_halfword_2:1787; CHECK-64-OPT: # %bb.0: # %entry1788; CHECK-64-OPT-NEXT: mtvsrwz 35, 31789; CHECK-64-OPT-NEXT: vinserth 2, 3, 41790; CHECK-64-OPT-NEXT: blr1791;1792; CHECK-64-O0-LABEL: insert_halfword_2:1793; CHECK-64-O0: # %bb.0: # %entry1794; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x31795; CHECK-64-O0-NEXT: mtfprwz 0, 31796; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 01797; CHECK-64-O0-NEXT: vinserth 2, 3, 41798; CHECK-64-O0-NEXT: blr1799;1800; CHECK-32-OPT-LABEL: insert_halfword_2:1801; CHECK-32-OPT: # %bb.0: # %entry1802; CHECK-32-OPT-NEXT: mtvsrwz 35, 31803; CHECK-32-OPT-NEXT: vinserth 2, 3, 41804; CHECK-32-OPT-NEXT: blr1805;1806; CHECK-32-O0-LABEL: insert_halfword_2:1807; CHECK-32-O0: # %bb.0: # %entry1808; CHECK-32-O0-NEXT: # kill: def $r4 killed $r31809; CHECK-32-O0-NEXT: mtfprwz 0, 31810; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 01811; CHECK-32-O0-NEXT: vinserth 2, 3, 41812; CHECK-32-O0-NEXT: blr1813entry:1814 %vecins = insertelement <8 x i16> %a, i16 %b, i32 21815 ret <8 x i16> %vecins1816}1817 1818define <8 x i16> @insert_halfword_3(<8 x i16> %a, i16 %b) {1819; CHECK-64-OPT-LABEL: insert_halfword_3:1820; CHECK-64-OPT: # %bb.0: # %entry1821; CHECK-64-OPT-NEXT: mtvsrwz 35, 31822; CHECK-64-OPT-NEXT: vinserth 2, 3, 61823; CHECK-64-OPT-NEXT: blr1824;1825; CHECK-64-O0-LABEL: insert_halfword_3:1826; CHECK-64-O0: # %bb.0: # %entry1827; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x31828; CHECK-64-O0-NEXT: mtfprwz 0, 31829; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 01830; CHECK-64-O0-NEXT: vinserth 2, 3, 61831; CHECK-64-O0-NEXT: blr1832;1833; CHECK-32-OPT-LABEL: insert_halfword_3:1834; CHECK-32-OPT: # %bb.0: # %entry1835; CHECK-32-OPT-NEXT: mtvsrwz 35, 31836; CHECK-32-OPT-NEXT: vinserth 2, 3, 61837; CHECK-32-OPT-NEXT: blr1838;1839; CHECK-32-O0-LABEL: insert_halfword_3:1840; CHECK-32-O0: # %bb.0: # %entry1841; CHECK-32-O0-NEXT: # kill: def $r4 killed $r31842; CHECK-32-O0-NEXT: mtfprwz 0, 31843; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 01844; CHECK-32-O0-NEXT: vinserth 2, 3, 61845; CHECK-32-O0-NEXT: blr1846entry:1847 %vecins = insertelement <8 x i16> %a, i16 %b, i32 31848 ret <8 x i16> %vecins1849}1850 1851define <8 x i16> @insert_halfword_4(<8 x i16> %a, i16 %b) {1852; CHECK-64-OPT-LABEL: insert_halfword_4:1853; CHECK-64-OPT: # %bb.0: # %entry1854; CHECK-64-OPT-NEXT: mtvsrwz 35, 31855; CHECK-64-OPT-NEXT: vinserth 2, 3, 81856; CHECK-64-OPT-NEXT: blr1857;1858; CHECK-64-O0-LABEL: insert_halfword_4:1859; CHECK-64-O0: # %bb.0: # %entry1860; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x31861; CHECK-64-O0-NEXT: mtfprwz 0, 31862; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 01863; CHECK-64-O0-NEXT: vinserth 2, 3, 81864; CHECK-64-O0-NEXT: blr1865;1866; CHECK-32-OPT-LABEL: insert_halfword_4:1867; CHECK-32-OPT: # %bb.0: # %entry1868; CHECK-32-OPT-NEXT: mtvsrwz 35, 31869; CHECK-32-OPT-NEXT: vinserth 2, 3, 81870; CHECK-32-OPT-NEXT: blr1871;1872; CHECK-32-O0-LABEL: insert_halfword_4:1873; CHECK-32-O0: # %bb.0: # %entry1874; CHECK-32-O0-NEXT: # kill: def $r4 killed $r31875; CHECK-32-O0-NEXT: mtfprwz 0, 31876; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 01877; CHECK-32-O0-NEXT: vinserth 2, 3, 81878; CHECK-32-O0-NEXT: blr1879entry:1880 %vecins = insertelement <8 x i16> %a, i16 %b, i32 41881 ret <8 x i16> %vecins1882}1883 1884define <8 x i16> @insert_halfword_5(<8 x i16> %a, i16 %b) {1885; CHECK-64-OPT-LABEL: insert_halfword_5:1886; CHECK-64-OPT: # %bb.0: # %entry1887; CHECK-64-OPT-NEXT: mtvsrwz 35, 31888; CHECK-64-OPT-NEXT: vinserth 2, 3, 101889; CHECK-64-OPT-NEXT: blr1890;1891; CHECK-64-O0-LABEL: insert_halfword_5:1892; CHECK-64-O0: # %bb.0: # %entry1893; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x31894; CHECK-64-O0-NEXT: mtfprwz 0, 31895; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 01896; CHECK-64-O0-NEXT: vinserth 2, 3, 101897; CHECK-64-O0-NEXT: blr1898;1899; CHECK-32-OPT-LABEL: insert_halfword_5:1900; CHECK-32-OPT: # %bb.0: # %entry1901; CHECK-32-OPT-NEXT: mtvsrwz 35, 31902; CHECK-32-OPT-NEXT: vinserth 2, 3, 101903; CHECK-32-OPT-NEXT: blr1904;1905; CHECK-32-O0-LABEL: insert_halfword_5:1906; CHECK-32-O0: # %bb.0: # %entry1907; CHECK-32-O0-NEXT: # kill: def $r4 killed $r31908; CHECK-32-O0-NEXT: mtfprwz 0, 31909; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 01910; CHECK-32-O0-NEXT: vinserth 2, 3, 101911; CHECK-32-O0-NEXT: blr1912entry:1913 %vecins = insertelement <8 x i16> %a, i16 %b, i32 51914 ret <8 x i16> %vecins1915}1916 1917define <8 x i16> @insert_halfword_6(<8 x i16> %a, i16 %b) {1918; CHECK-64-OPT-LABEL: insert_halfword_6:1919; CHECK-64-OPT: # %bb.0: # %entry1920; CHECK-64-OPT-NEXT: mtvsrwz 35, 31921; CHECK-64-OPT-NEXT: vinserth 2, 3, 121922; CHECK-64-OPT-NEXT: blr1923;1924; CHECK-64-O0-LABEL: insert_halfword_6:1925; CHECK-64-O0: # %bb.0: # %entry1926; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x31927; CHECK-64-O0-NEXT: mtfprwz 0, 31928; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 01929; CHECK-64-O0-NEXT: vinserth 2, 3, 121930; CHECK-64-O0-NEXT: blr1931;1932; CHECK-32-OPT-LABEL: insert_halfword_6:1933; CHECK-32-OPT: # %bb.0: # %entry1934; CHECK-32-OPT-NEXT: mtvsrwz 35, 31935; CHECK-32-OPT-NEXT: vinserth 2, 3, 121936; CHECK-32-OPT-NEXT: blr1937;1938; CHECK-32-O0-LABEL: insert_halfword_6:1939; CHECK-32-O0: # %bb.0: # %entry1940; CHECK-32-O0-NEXT: # kill: def $r4 killed $r31941; CHECK-32-O0-NEXT: mtfprwz 0, 31942; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 01943; CHECK-32-O0-NEXT: vinserth 2, 3, 121944; CHECK-32-O0-NEXT: blr1945entry:1946 %vecins = insertelement <8 x i16> %a, i16 %b, i32 61947 ret <8 x i16> %vecins1948}1949 1950define <8 x i16> @insert_halfword_7(<8 x i16> %a, i16 %b) {1951; CHECK-64-OPT-LABEL: insert_halfword_7:1952; CHECK-64-OPT: # %bb.0: # %entry1953; CHECK-64-OPT-NEXT: mtvsrwz 35, 31954; CHECK-64-OPT-NEXT: vinserth 2, 3, 141955; CHECK-64-OPT-NEXT: blr1956;1957; CHECK-64-O0-LABEL: insert_halfword_7:1958; CHECK-64-O0: # %bb.0: # %entry1959; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x31960; CHECK-64-O0-NEXT: mtfprwz 0, 31961; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 01962; CHECK-64-O0-NEXT: vinserth 2, 3, 141963; CHECK-64-O0-NEXT: blr1964;1965; CHECK-32-OPT-LABEL: insert_halfword_7:1966; CHECK-32-OPT: # %bb.0: # %entry1967; CHECK-32-OPT-NEXT: mtvsrwz 35, 31968; CHECK-32-OPT-NEXT: vinserth 2, 3, 141969; CHECK-32-OPT-NEXT: blr1970;1971; CHECK-32-O0-LABEL: insert_halfword_7:1972; CHECK-32-O0: # %bb.0: # %entry1973; CHECK-32-O0-NEXT: # kill: def $r4 killed $r31974; CHECK-32-O0-NEXT: mtfprwz 0, 31975; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 01976; CHECK-32-O0-NEXT: vinserth 2, 3, 141977; CHECK-32-O0-NEXT: blr1978entry:1979 %vecins = insertelement <8 x i16> %a, i16 %b, i32 71980 ret <8 x i16> %vecins1981}1982 1983; The following tests try to insert one byte element into the vector. We1984; should always be using the 'vinsertb' instruction.1985define <16 x i8> @insert_byte_0(<16 x i8> %a, i8 %b) {1986; CHECK-64-OPT-LABEL: insert_byte_0:1987; CHECK-64-OPT: # %bb.0: # %entry1988; CHECK-64-OPT-NEXT: mtvsrwz 35, 31989; CHECK-64-OPT-NEXT: vinsertb 2, 3, 01990; CHECK-64-OPT-NEXT: blr1991;1992; CHECK-64-O0-LABEL: insert_byte_0:1993; CHECK-64-O0: # %bb.0: # %entry1994; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x31995; CHECK-64-O0-NEXT: mtfprwz 0, 31996; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 01997; CHECK-64-O0-NEXT: vinsertb 2, 3, 01998; CHECK-64-O0-NEXT: blr1999;2000; CHECK-32-OPT-LABEL: insert_byte_0:2001; CHECK-32-OPT: # %bb.0: # %entry2002; CHECK-32-OPT-NEXT: mtvsrwz 35, 32003; CHECK-32-OPT-NEXT: vinsertb 2, 3, 02004; CHECK-32-OPT-NEXT: blr2005;2006; CHECK-32-O0-LABEL: insert_byte_0:2007; CHECK-32-O0: # %bb.0: # %entry2008; CHECK-32-O0-NEXT: # kill: def $r4 killed $r32009; CHECK-32-O0-NEXT: mtfprwz 0, 32010; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 02011; CHECK-32-O0-NEXT: vinsertb 2, 3, 02012; CHECK-32-O0-NEXT: blr2013entry:2014 %vecins = insertelement <16 x i8> %a, i8 %b, i32 02015 ret <16 x i8> %vecins2016}2017 2018define <16 x i8> @insert_byte_1(<16 x i8> %a, i8 %b) {2019; CHECK-64-OPT-LABEL: insert_byte_1:2020; CHECK-64-OPT: # %bb.0: # %entry2021; CHECK-64-OPT-NEXT: mtvsrwz 35, 32022; CHECK-64-OPT-NEXT: vinsertb 2, 3, 12023; CHECK-64-OPT-NEXT: blr2024;2025; CHECK-64-O0-LABEL: insert_byte_1:2026; CHECK-64-O0: # %bb.0: # %entry2027; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x32028; CHECK-64-O0-NEXT: mtfprwz 0, 32029; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 02030; CHECK-64-O0-NEXT: vinsertb 2, 3, 12031; CHECK-64-O0-NEXT: blr2032;2033; CHECK-32-OPT-LABEL: insert_byte_1:2034; CHECK-32-OPT: # %bb.0: # %entry2035; CHECK-32-OPT-NEXT: mtvsrwz 35, 32036; CHECK-32-OPT-NEXT: vinsertb 2, 3, 12037; CHECK-32-OPT-NEXT: blr2038;2039; CHECK-32-O0-LABEL: insert_byte_1:2040; CHECK-32-O0: # %bb.0: # %entry2041; CHECK-32-O0-NEXT: # kill: def $r4 killed $r32042; CHECK-32-O0-NEXT: mtfprwz 0, 32043; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 02044; CHECK-32-O0-NEXT: vinsertb 2, 3, 12045; CHECK-32-O0-NEXT: blr2046entry:2047 %vecins = insertelement <16 x i8> %a, i8 %b, i32 12048 ret <16 x i8> %vecins2049}2050 2051define <16 x i8> @insert_byte_2(<16 x i8> %a, i8 %b) {2052; CHECK-64-OPT-LABEL: insert_byte_2:2053; CHECK-64-OPT: # %bb.0: # %entry2054; CHECK-64-OPT-NEXT: mtvsrwz 35, 32055; CHECK-64-OPT-NEXT: vinsertb 2, 3, 22056; CHECK-64-OPT-NEXT: blr2057;2058; CHECK-64-O0-LABEL: insert_byte_2:2059; CHECK-64-O0: # %bb.0: # %entry2060; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x32061; CHECK-64-O0-NEXT: mtfprwz 0, 32062; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 02063; CHECK-64-O0-NEXT: vinsertb 2, 3, 22064; CHECK-64-O0-NEXT: blr2065;2066; CHECK-32-OPT-LABEL: insert_byte_2:2067; CHECK-32-OPT: # %bb.0: # %entry2068; CHECK-32-OPT-NEXT: mtvsrwz 35, 32069; CHECK-32-OPT-NEXT: vinsertb 2, 3, 22070; CHECK-32-OPT-NEXT: blr2071;2072; CHECK-32-O0-LABEL: insert_byte_2:2073; CHECK-32-O0: # %bb.0: # %entry2074; CHECK-32-O0-NEXT: # kill: def $r4 killed $r32075; CHECK-32-O0-NEXT: mtfprwz 0, 32076; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 02077; CHECK-32-O0-NEXT: vinsertb 2, 3, 22078; CHECK-32-O0-NEXT: blr2079entry:2080 %vecins = insertelement <16 x i8> %a, i8 %b, i32 22081 ret <16 x i8> %vecins2082}2083 2084define <16 x i8> @insert_byte_3(<16 x i8> %a, i8 %b) {2085; CHECK-64-OPT-LABEL: insert_byte_3:2086; CHECK-64-OPT: # %bb.0: # %entry2087; CHECK-64-OPT-NEXT: mtvsrwz 35, 32088; CHECK-64-OPT-NEXT: vinsertb 2, 3, 32089; CHECK-64-OPT-NEXT: blr2090;2091; CHECK-64-O0-LABEL: insert_byte_3:2092; CHECK-64-O0: # %bb.0: # %entry2093; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x32094; CHECK-64-O0-NEXT: mtfprwz 0, 32095; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 02096; CHECK-64-O0-NEXT: vinsertb 2, 3, 32097; CHECK-64-O0-NEXT: blr2098;2099; CHECK-32-OPT-LABEL: insert_byte_3:2100; CHECK-32-OPT: # %bb.0: # %entry2101; CHECK-32-OPT-NEXT: mtvsrwz 35, 32102; CHECK-32-OPT-NEXT: vinsertb 2, 3, 32103; CHECK-32-OPT-NEXT: blr2104;2105; CHECK-32-O0-LABEL: insert_byte_3:2106; CHECK-32-O0: # %bb.0: # %entry2107; CHECK-32-O0-NEXT: # kill: def $r4 killed $r32108; CHECK-32-O0-NEXT: mtfprwz 0, 32109; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 02110; CHECK-32-O0-NEXT: vinsertb 2, 3, 32111; CHECK-32-O0-NEXT: blr2112entry:2113 %vecins = insertelement <16 x i8> %a, i8 %b, i32 32114 ret <16 x i8> %vecins2115}2116 2117define <16 x i8> @insert_byte_4(<16 x i8> %a, i8 %b) {2118; CHECK-64-OPT-LABEL: insert_byte_4:2119; CHECK-64-OPT: # %bb.0: # %entry2120; CHECK-64-OPT-NEXT: mtvsrwz 35, 32121; CHECK-64-OPT-NEXT: vinsertb 2, 3, 42122; CHECK-64-OPT-NEXT: blr2123;2124; CHECK-64-O0-LABEL: insert_byte_4:2125; CHECK-64-O0: # %bb.0: # %entry2126; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x32127; CHECK-64-O0-NEXT: mtfprwz 0, 32128; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 02129; CHECK-64-O0-NEXT: vinsertb 2, 3, 42130; CHECK-64-O0-NEXT: blr2131;2132; CHECK-32-OPT-LABEL: insert_byte_4:2133; CHECK-32-OPT: # %bb.0: # %entry2134; CHECK-32-OPT-NEXT: mtvsrwz 35, 32135; CHECK-32-OPT-NEXT: vinsertb 2, 3, 42136; CHECK-32-OPT-NEXT: blr2137;2138; CHECK-32-O0-LABEL: insert_byte_4:2139; CHECK-32-O0: # %bb.0: # %entry2140; CHECK-32-O0-NEXT: # kill: def $r4 killed $r32141; CHECK-32-O0-NEXT: mtfprwz 0, 32142; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 02143; CHECK-32-O0-NEXT: vinsertb 2, 3, 42144; CHECK-32-O0-NEXT: blr2145entry:2146 %vecins = insertelement <16 x i8> %a, i8 %b, i32 42147 ret <16 x i8> %vecins2148}2149 2150define <16 x i8> @insert_byte_5(<16 x i8> %a, i8 %b) {2151; CHECK-64-OPT-LABEL: insert_byte_5:2152; CHECK-64-OPT: # %bb.0: # %entry2153; CHECK-64-OPT-NEXT: mtvsrwz 35, 32154; CHECK-64-OPT-NEXT: vinsertb 2, 3, 52155; CHECK-64-OPT-NEXT: blr2156;2157; CHECK-64-O0-LABEL: insert_byte_5:2158; CHECK-64-O0: # %bb.0: # %entry2159; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x32160; CHECK-64-O0-NEXT: mtfprwz 0, 32161; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 02162; CHECK-64-O0-NEXT: vinsertb 2, 3, 52163; CHECK-64-O0-NEXT: blr2164;2165; CHECK-32-OPT-LABEL: insert_byte_5:2166; CHECK-32-OPT: # %bb.0: # %entry2167; CHECK-32-OPT-NEXT: mtvsrwz 35, 32168; CHECK-32-OPT-NEXT: vinsertb 2, 3, 52169; CHECK-32-OPT-NEXT: blr2170;2171; CHECK-32-O0-LABEL: insert_byte_5:2172; CHECK-32-O0: # %bb.0: # %entry2173; CHECK-32-O0-NEXT: # kill: def $r4 killed $r32174; CHECK-32-O0-NEXT: mtfprwz 0, 32175; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 02176; CHECK-32-O0-NEXT: vinsertb 2, 3, 52177; CHECK-32-O0-NEXT: blr2178entry:2179 %vecins = insertelement <16 x i8> %a, i8 %b, i32 52180 ret <16 x i8> %vecins2181}2182 2183define <16 x i8> @insert_byte_6(<16 x i8> %a, i8 %b) {2184; CHECK-64-OPT-LABEL: insert_byte_6:2185; CHECK-64-OPT: # %bb.0: # %entry2186; CHECK-64-OPT-NEXT: mtvsrwz 35, 32187; CHECK-64-OPT-NEXT: vinsertb 2, 3, 62188; CHECK-64-OPT-NEXT: blr2189;2190; CHECK-64-O0-LABEL: insert_byte_6:2191; CHECK-64-O0: # %bb.0: # %entry2192; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x32193; CHECK-64-O0-NEXT: mtfprwz 0, 32194; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 02195; CHECK-64-O0-NEXT: vinsertb 2, 3, 62196; CHECK-64-O0-NEXT: blr2197;2198; CHECK-32-OPT-LABEL: insert_byte_6:2199; CHECK-32-OPT: # %bb.0: # %entry2200; CHECK-32-OPT-NEXT: mtvsrwz 35, 32201; CHECK-32-OPT-NEXT: vinsertb 2, 3, 62202; CHECK-32-OPT-NEXT: blr2203;2204; CHECK-32-O0-LABEL: insert_byte_6:2205; CHECK-32-O0: # %bb.0: # %entry2206; CHECK-32-O0-NEXT: # kill: def $r4 killed $r32207; CHECK-32-O0-NEXT: mtfprwz 0, 32208; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 02209; CHECK-32-O0-NEXT: vinsertb 2, 3, 62210; CHECK-32-O0-NEXT: blr2211entry:2212 %vecins = insertelement <16 x i8> %a, i8 %b, i32 62213 ret <16 x i8> %vecins2214}2215 2216define <16 x i8> @insert_byte_7(<16 x i8> %a, i8 %b) {2217; CHECK-64-OPT-LABEL: insert_byte_7:2218; CHECK-64-OPT: # %bb.0: # %entry2219; CHECK-64-OPT-NEXT: mtvsrwz 35, 32220; CHECK-64-OPT-NEXT: vinsertb 2, 3, 72221; CHECK-64-OPT-NEXT: blr2222;2223; CHECK-64-O0-LABEL: insert_byte_7:2224; CHECK-64-O0: # %bb.0: # %entry2225; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x32226; CHECK-64-O0-NEXT: mtfprwz 0, 32227; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 02228; CHECK-64-O0-NEXT: vinsertb 2, 3, 72229; CHECK-64-O0-NEXT: blr2230;2231; CHECK-32-OPT-LABEL: insert_byte_7:2232; CHECK-32-OPT: # %bb.0: # %entry2233; CHECK-32-OPT-NEXT: mtvsrwz 35, 32234; CHECK-32-OPT-NEXT: vinsertb 2, 3, 72235; CHECK-32-OPT-NEXT: blr2236;2237; CHECK-32-O0-LABEL: insert_byte_7:2238; CHECK-32-O0: # %bb.0: # %entry2239; CHECK-32-O0-NEXT: # kill: def $r4 killed $r32240; CHECK-32-O0-NEXT: mtfprwz 0, 32241; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 02242; CHECK-32-O0-NEXT: vinsertb 2, 3, 72243; CHECK-32-O0-NEXT: blr2244entry:2245 %vecins = insertelement <16 x i8> %a, i8 %b, i32 72246 ret <16 x i8> %vecins2247}2248 2249define <16 x i8> @insert_byte_8(<16 x i8> %a, i8 %b) {2250; CHECK-64-OPT-LABEL: insert_byte_8:2251; CHECK-64-OPT: # %bb.0: # %entry2252; CHECK-64-OPT-NEXT: mtvsrwz 35, 32253; CHECK-64-OPT-NEXT: vinsertb 2, 3, 82254; CHECK-64-OPT-NEXT: blr2255;2256; CHECK-64-O0-LABEL: insert_byte_8:2257; CHECK-64-O0: # %bb.0: # %entry2258; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x32259; CHECK-64-O0-NEXT: mtfprwz 0, 32260; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 02261; CHECK-64-O0-NEXT: vinsertb 2, 3, 82262; CHECK-64-O0-NEXT: blr2263;2264; CHECK-32-OPT-LABEL: insert_byte_8:2265; CHECK-32-OPT: # %bb.0: # %entry2266; CHECK-32-OPT-NEXT: mtvsrwz 35, 32267; CHECK-32-OPT-NEXT: vinsertb 2, 3, 82268; CHECK-32-OPT-NEXT: blr2269;2270; CHECK-32-O0-LABEL: insert_byte_8:2271; CHECK-32-O0: # %bb.0: # %entry2272; CHECK-32-O0-NEXT: # kill: def $r4 killed $r32273; CHECK-32-O0-NEXT: mtfprwz 0, 32274; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 02275; CHECK-32-O0-NEXT: vinsertb 2, 3, 82276; CHECK-32-O0-NEXT: blr2277entry:2278 %vecins = insertelement <16 x i8> %a, i8 %b, i32 82279 ret <16 x i8> %vecins2280}2281 2282define <16 x i8> @insert_byte_9(<16 x i8> %a, i8 %b) {2283; CHECK-64-OPT-LABEL: insert_byte_9:2284; CHECK-64-OPT: # %bb.0: # %entry2285; CHECK-64-OPT-NEXT: mtvsrwz 35, 32286; CHECK-64-OPT-NEXT: vinsertb 2, 3, 92287; CHECK-64-OPT-NEXT: blr2288;2289; CHECK-64-O0-LABEL: insert_byte_9:2290; CHECK-64-O0: # %bb.0: # %entry2291; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x32292; CHECK-64-O0-NEXT: mtfprwz 0, 32293; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 02294; CHECK-64-O0-NEXT: vinsertb 2, 3, 92295; CHECK-64-O0-NEXT: blr2296;2297; CHECK-32-OPT-LABEL: insert_byte_9:2298; CHECK-32-OPT: # %bb.0: # %entry2299; CHECK-32-OPT-NEXT: mtvsrwz 35, 32300; CHECK-32-OPT-NEXT: vinsertb 2, 3, 92301; CHECK-32-OPT-NEXT: blr2302;2303; CHECK-32-O0-LABEL: insert_byte_9:2304; CHECK-32-O0: # %bb.0: # %entry2305; CHECK-32-O0-NEXT: # kill: def $r4 killed $r32306; CHECK-32-O0-NEXT: mtfprwz 0, 32307; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 02308; CHECK-32-O0-NEXT: vinsertb 2, 3, 92309; CHECK-32-O0-NEXT: blr2310entry:2311 %vecins = insertelement <16 x i8> %a, i8 %b, i32 92312 ret <16 x i8> %vecins2313}2314 2315define <16 x i8> @insert_byte_10(<16 x i8> %a, i8 %b) {2316; CHECK-64-OPT-LABEL: insert_byte_10:2317; CHECK-64-OPT: # %bb.0: # %entry2318; CHECK-64-OPT-NEXT: mtvsrwz 35, 32319; CHECK-64-OPT-NEXT: vinsertb 2, 3, 102320; CHECK-64-OPT-NEXT: blr2321;2322; CHECK-64-O0-LABEL: insert_byte_10:2323; CHECK-64-O0: # %bb.0: # %entry2324; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x32325; CHECK-64-O0-NEXT: mtfprwz 0, 32326; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 02327; CHECK-64-O0-NEXT: vinsertb 2, 3, 102328; CHECK-64-O0-NEXT: blr2329;2330; CHECK-32-OPT-LABEL: insert_byte_10:2331; CHECK-32-OPT: # %bb.0: # %entry2332; CHECK-32-OPT-NEXT: mtvsrwz 35, 32333; CHECK-32-OPT-NEXT: vinsertb 2, 3, 102334; CHECK-32-OPT-NEXT: blr2335;2336; CHECK-32-O0-LABEL: insert_byte_10:2337; CHECK-32-O0: # %bb.0: # %entry2338; CHECK-32-O0-NEXT: # kill: def $r4 killed $r32339; CHECK-32-O0-NEXT: mtfprwz 0, 32340; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 02341; CHECK-32-O0-NEXT: vinsertb 2, 3, 102342; CHECK-32-O0-NEXT: blr2343entry:2344 %vecins = insertelement <16 x i8> %a, i8 %b, i32 102345 ret <16 x i8> %vecins2346}2347 2348define <16 x i8> @insert_byte_11(<16 x i8> %a, i8 %b) {2349; CHECK-64-OPT-LABEL: insert_byte_11:2350; CHECK-64-OPT: # %bb.0: # %entry2351; CHECK-64-OPT-NEXT: mtvsrwz 35, 32352; CHECK-64-OPT-NEXT: vinsertb 2, 3, 112353; CHECK-64-OPT-NEXT: blr2354;2355; CHECK-64-O0-LABEL: insert_byte_11:2356; CHECK-64-O0: # %bb.0: # %entry2357; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x32358; CHECK-64-O0-NEXT: mtfprwz 0, 32359; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 02360; CHECK-64-O0-NEXT: vinsertb 2, 3, 112361; CHECK-64-O0-NEXT: blr2362;2363; CHECK-32-OPT-LABEL: insert_byte_11:2364; CHECK-32-OPT: # %bb.0: # %entry2365; CHECK-32-OPT-NEXT: mtvsrwz 35, 32366; CHECK-32-OPT-NEXT: vinsertb 2, 3, 112367; CHECK-32-OPT-NEXT: blr2368;2369; CHECK-32-O0-LABEL: insert_byte_11:2370; CHECK-32-O0: # %bb.0: # %entry2371; CHECK-32-O0-NEXT: # kill: def $r4 killed $r32372; CHECK-32-O0-NEXT: mtfprwz 0, 32373; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 02374; CHECK-32-O0-NEXT: vinsertb 2, 3, 112375; CHECK-32-O0-NEXT: blr2376entry:2377 %vecins = insertelement <16 x i8> %a, i8 %b, i32 112378 ret <16 x i8> %vecins2379}2380 2381define <16 x i8> @insert_byte_12(<16 x i8> %a, i8 %b) {2382; CHECK-64-OPT-LABEL: insert_byte_12:2383; CHECK-64-OPT: # %bb.0: # %entry2384; CHECK-64-OPT-NEXT: mtvsrwz 35, 32385; CHECK-64-OPT-NEXT: vinsertb 2, 3, 122386; CHECK-64-OPT-NEXT: blr2387;2388; CHECK-64-O0-LABEL: insert_byte_12:2389; CHECK-64-O0: # %bb.0: # %entry2390; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x32391; CHECK-64-O0-NEXT: mtfprwz 0, 32392; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 02393; CHECK-64-O0-NEXT: vinsertb 2, 3, 122394; CHECK-64-O0-NEXT: blr2395;2396; CHECK-32-OPT-LABEL: insert_byte_12:2397; CHECK-32-OPT: # %bb.0: # %entry2398; CHECK-32-OPT-NEXT: mtvsrwz 35, 32399; CHECK-32-OPT-NEXT: vinsertb 2, 3, 122400; CHECK-32-OPT-NEXT: blr2401;2402; CHECK-32-O0-LABEL: insert_byte_12:2403; CHECK-32-O0: # %bb.0: # %entry2404; CHECK-32-O0-NEXT: # kill: def $r4 killed $r32405; CHECK-32-O0-NEXT: mtfprwz 0, 32406; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 02407; CHECK-32-O0-NEXT: vinsertb 2, 3, 122408; CHECK-32-O0-NEXT: blr2409entry:2410 %vecins = insertelement <16 x i8> %a, i8 %b, i32 122411 ret <16 x i8> %vecins2412}2413 2414define <16 x i8> @insert_byte_13(<16 x i8> %a, i8 %b) {2415; CHECK-64-OPT-LABEL: insert_byte_13:2416; CHECK-64-OPT: # %bb.0: # %entry2417; CHECK-64-OPT-NEXT: mtvsrwz 35, 32418; CHECK-64-OPT-NEXT: vinsertb 2, 3, 132419; CHECK-64-OPT-NEXT: blr2420;2421; CHECK-64-O0-LABEL: insert_byte_13:2422; CHECK-64-O0: # %bb.0: # %entry2423; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x32424; CHECK-64-O0-NEXT: mtfprwz 0, 32425; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 02426; CHECK-64-O0-NEXT: vinsertb 2, 3, 132427; CHECK-64-O0-NEXT: blr2428;2429; CHECK-32-OPT-LABEL: insert_byte_13:2430; CHECK-32-OPT: # %bb.0: # %entry2431; CHECK-32-OPT-NEXT: mtvsrwz 35, 32432; CHECK-32-OPT-NEXT: vinsertb 2, 3, 132433; CHECK-32-OPT-NEXT: blr2434;2435; CHECK-32-O0-LABEL: insert_byte_13:2436; CHECK-32-O0: # %bb.0: # %entry2437; CHECK-32-O0-NEXT: # kill: def $r4 killed $r32438; CHECK-32-O0-NEXT: mtfprwz 0, 32439; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 02440; CHECK-32-O0-NEXT: vinsertb 2, 3, 132441; CHECK-32-O0-NEXT: blr2442entry:2443 %vecins = insertelement <16 x i8> %a, i8 %b, i32 132444 ret <16 x i8> %vecins2445}2446 2447define <16 x i8> @insert_byte_14(<16 x i8> %a, i8 %b) {2448; CHECK-64-OPT-LABEL: insert_byte_14:2449; CHECK-64-OPT: # %bb.0: # %entry2450; CHECK-64-OPT-NEXT: mtvsrwz 35, 32451; CHECK-64-OPT-NEXT: vinsertb 2, 3, 142452; CHECK-64-OPT-NEXT: blr2453;2454; CHECK-64-O0-LABEL: insert_byte_14:2455; CHECK-64-O0: # %bb.0: # %entry2456; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x32457; CHECK-64-O0-NEXT: mtfprwz 0, 32458; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 02459; CHECK-64-O0-NEXT: vinsertb 2, 3, 142460; CHECK-64-O0-NEXT: blr2461;2462; CHECK-32-OPT-LABEL: insert_byte_14:2463; CHECK-32-OPT: # %bb.0: # %entry2464; CHECK-32-OPT-NEXT: mtvsrwz 35, 32465; CHECK-32-OPT-NEXT: vinsertb 2, 3, 142466; CHECK-32-OPT-NEXT: blr2467;2468; CHECK-32-O0-LABEL: insert_byte_14:2469; CHECK-32-O0: # %bb.0: # %entry2470; CHECK-32-O0-NEXT: # kill: def $r4 killed $r32471; CHECK-32-O0-NEXT: mtfprwz 0, 32472; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 02473; CHECK-32-O0-NEXT: vinsertb 2, 3, 142474; CHECK-32-O0-NEXT: blr2475entry:2476 %vecins = insertelement <16 x i8> %a, i8 %b, i32 142477 ret <16 x i8> %vecins2478}2479 2480define <16 x i8> @insert_byte_15(<16 x i8> %a, i8 %b) {2481; CHECK-64-OPT-LABEL: insert_byte_15:2482; CHECK-64-OPT: # %bb.0: # %entry2483; CHECK-64-OPT-NEXT: mtvsrwz 35, 32484; CHECK-64-OPT-NEXT: vinsertb 2, 3, 152485; CHECK-64-OPT-NEXT: blr2486;2487; CHECK-64-O0-LABEL: insert_byte_15:2488; CHECK-64-O0: # %bb.0: # %entry2489; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x32490; CHECK-64-O0-NEXT: mtfprwz 0, 32491; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 02492; CHECK-64-O0-NEXT: vinsertb 2, 3, 152493; CHECK-64-O0-NEXT: blr2494;2495; CHECK-32-OPT-LABEL: insert_byte_15:2496; CHECK-32-OPT: # %bb.0: # %entry2497; CHECK-32-OPT-NEXT: mtvsrwz 35, 32498; CHECK-32-OPT-NEXT: vinsertb 2, 3, 152499; CHECK-32-OPT-NEXT: blr2500;2501; CHECK-32-O0-LABEL: insert_byte_15:2502; CHECK-32-O0: # %bb.0: # %entry2503; CHECK-32-O0-NEXT: # kill: def $r4 killed $r32504; CHECK-32-O0-NEXT: mtfprwz 0, 32505; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 02506; CHECK-32-O0-NEXT: vinsertb 2, 3, 152507; CHECK-32-O0-NEXT: blr2508entry:2509 %vecins = insertelement <16 x i8> %a, i8 %b, i32 152510 ret <16 x i8> %vecins2511}2512