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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-644; RUN: llc -mcpu=pwr9 -mtriple=powerpc-ibm-aix-xcoff \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-326 7define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {8; CHECK-64-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_:9; CHECK-64: # %bb.0: # %entry10; CHECK-64-NEXT: xxsldwi 0, 35, 35, 311; CHECK-64-NEXT: xxinsertw 34, 0, 012; CHECK-64-NEXT: blr13;14; CHECK-32-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_:15; CHECK-32: # %bb.0: # %entry16; CHECK-32-NEXT: xxsldwi 0, 35, 35, 317; CHECK-32-NEXT: xxinsertw 34, 0, 018; CHECK-32-NEXT: blr19entry:20 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3>21 ret <4 x float> %vecins22}23 24define <4 x float> @_Z7testInsILj0ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {25; CHECK-64-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_:26; CHECK-64: # %bb.0: # %entry27; CHECK-64-NEXT: xxinsertw 34, 35, 028; CHECK-64-NEXT: blr29;30; CHECK-32-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_:31; CHECK-32: # %bb.0: # %entry32; CHECK-32-NEXT: xxinsertw 34, 35, 033; CHECK-32-NEXT: blr34entry:35 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 5, i32 1, i32 2, i32 3>36 ret <4 x float> %vecins37}38 39define <4 x float> @_Z7testInsILj0ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {40; CHECK-64-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_:41; CHECK-64: # %bb.0: # %entry42; CHECK-64-NEXT: xxsldwi 0, 35, 35, 143; CHECK-64-NEXT: xxinsertw 34, 0, 044; CHECK-64-NEXT: blr45;46; CHECK-32-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_:47; CHECK-32: # %bb.0: # %entry48; CHECK-32-NEXT: xxsldwi 0, 35, 35, 149; CHECK-32-NEXT: xxinsertw 34, 0, 050; CHECK-32-NEXT: blr51entry:52 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 1, i32 2, i32 3>53 ret <4 x float> %vecins54}55 56define <4 x float> @_Z7testInsILj0ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {57; CHECK-64-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_:58; CHECK-64: # %bb.0: # %entry59; CHECK-64-NEXT: xxswapd 0, 3560; CHECK-64-NEXT: xxinsertw 34, 0, 061; CHECK-64-NEXT: blr62;63; CHECK-32-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_:64; CHECK-32: # %bb.0: # %entry65; CHECK-32-NEXT: xxswapd 0, 3566; CHECK-32-NEXT: xxinsertw 34, 0, 067; CHECK-32-NEXT: blr68entry:69 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 7, i32 1, i32 2, i32 3>70 ret <4 x float> %vecins71}72 73define <4 x float> @_Z7testInsILj1ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {74; CHECK-64-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_:75; CHECK-64: # %bb.0: # %entry76; CHECK-64-NEXT: xxsldwi 0, 35, 35, 377; CHECK-64-NEXT: xxinsertw 34, 0, 478; CHECK-64-NEXT: blr79;80; CHECK-32-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_:81; CHECK-32: # %bb.0: # %entry82; CHECK-32-NEXT: xxsldwi 0, 35, 35, 383; CHECK-32-NEXT: xxinsertw 34, 0, 484; CHECK-32-NEXT: blr85entry:86 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 3>87 ret <4 x float> %vecins88}89 90define <4 x float> @_Z7testInsILj1ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {91; CHECK-64-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_:92; CHECK-64: # %bb.0: # %entry93; CHECK-64-NEXT: xxinsertw 34, 35, 494; CHECK-64-NEXT: blr95;96; CHECK-32-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_:97; CHECK-32: # %bb.0: # %entry98; CHECK-32-NEXT: xxinsertw 34, 35, 499; CHECK-32-NEXT: blr100entry:101 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>102 ret <4 x float> %vecins103}104 105define <4 x float> @_Z7testInsILj1ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {106; CHECK-64-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_:107; CHECK-64: # %bb.0: # %entry108; CHECK-64-NEXT: xxsldwi 0, 35, 35, 1109; CHECK-64-NEXT: xxinsertw 34, 0, 4110; CHECK-64-NEXT: blr111;112; CHECK-32-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_:113; CHECK-32: # %bb.0: # %entry114; CHECK-32-NEXT: xxsldwi 0, 35, 35, 1115; CHECK-32-NEXT: xxinsertw 34, 0, 4116; CHECK-32-NEXT: blr117entry:118 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 6, i32 2, i32 3>119 ret <4 x float> %vecins120}121 122define <4 x float> @_Z7testInsILj1ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {123; CHECK-64-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_:124; CHECK-64: # %bb.0: # %entry125; CHECK-64-NEXT: xxswapd 0, 35126; CHECK-64-NEXT: xxinsertw 34, 0, 4127; CHECK-64-NEXT: blr128;129; CHECK-32-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_:130; CHECK-32: # %bb.0: # %entry131; CHECK-32-NEXT: xxswapd 0, 35132; CHECK-32-NEXT: xxinsertw 34, 0, 4133; CHECK-32-NEXT: blr134entry:135 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3>136 ret <4 x float> %vecins137}138 139define <4 x float> @_Z7testInsILj2ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {140; CHECK-64-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_:141; CHECK-64: # %bb.0: # %entry142; CHECK-64-NEXT: xxsldwi 0, 35, 35, 3143; CHECK-64-NEXT: xxinsertw 34, 0, 8144; CHECK-64-NEXT: blr145;146; CHECK-32-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_:147; CHECK-32: # %bb.0: # %entry148; CHECK-32-NEXT: xxsldwi 0, 35, 35, 3149; CHECK-32-NEXT: xxinsertw 34, 0, 8150; CHECK-32-NEXT: blr151entry:152 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 3>153 ret <4 x float> %vecins154}155 156define <4 x float> @_Z7testInsILj2ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {157; CHECK-64-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_:158; CHECK-64: # %bb.0: # %entry159; CHECK-64-NEXT: xxinsertw 34, 35, 8160; CHECK-64-NEXT: blr161;162; CHECK-32-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_:163; CHECK-32: # %bb.0: # %entry164; CHECK-32-NEXT: xxinsertw 34, 35, 8165; CHECK-32-NEXT: blr166entry:167 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 5, i32 3>168 ret <4 x float> %vecins169}170 171define <4 x float> @_Z7testInsILj2ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {172; CHECK-64-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_:173; CHECK-64: # %bb.0: # %entry174; CHECK-64-NEXT: xxsldwi 0, 35, 35, 1175; CHECK-64-NEXT: xxinsertw 34, 0, 8176; CHECK-64-NEXT: blr177;178; CHECK-32-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_:179; CHECK-32: # %bb.0: # %entry180; CHECK-32-NEXT: xxsldwi 0, 35, 35, 1181; CHECK-32-NEXT: xxinsertw 34, 0, 8182; CHECK-32-NEXT: blr183entry:184 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>185 ret <4 x float> %vecins186}187 188define <4 x float> @_Z7testInsILj2ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {189; CHECK-64-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_:190; CHECK-64: # %bb.0: # %entry191; CHECK-64-NEXT: xxswapd 0, 35192; CHECK-64-NEXT: xxinsertw 34, 0, 8193; CHECK-64-NEXT: blr194;195; CHECK-32-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_:196; CHECK-32: # %bb.0: # %entry197; CHECK-32-NEXT: xxswapd 0, 35198; CHECK-32-NEXT: xxinsertw 34, 0, 8199; CHECK-32-NEXT: blr200entry:201 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 7, i32 3>202 ret <4 x float> %vecins203}204 205define <4 x float> @_Z7testInsILj3ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {206; CHECK-64-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_:207; CHECK-64: # %bb.0: # %entry208; CHECK-64-NEXT: xxsldwi 0, 35, 35, 3209; CHECK-64-NEXT: xxinsertw 34, 0, 12210; CHECK-64-NEXT: blr211;212; CHECK-32-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_:213; CHECK-32: # %bb.0: # %entry214; CHECK-32-NEXT: xxsldwi 0, 35, 35, 3215; CHECK-32-NEXT: xxinsertw 34, 0, 12216; CHECK-32-NEXT: blr217entry:218 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4>219 ret <4 x float> %vecins220}221 222define <4 x float> @_Z7testInsILj3ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {223; CHECK-64-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_:224; CHECK-64: # %bb.0: # %entry225; CHECK-64-NEXT: xxinsertw 34, 35, 12226; CHECK-64-NEXT: blr227;228; CHECK-32-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_:229; CHECK-32: # %bb.0: # %entry230; CHECK-32-NEXT: xxinsertw 34, 35, 12231; CHECK-32-NEXT: blr232entry:233 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 5>234 ret <4 x float> %vecins235}236 237define <4 x float> @_Z7testInsILj3ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {238; CHECK-64-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_:239; CHECK-64: # %bb.0: # %entry240; CHECK-64-NEXT: xxsldwi 0, 35, 35, 1241; CHECK-64-NEXT: xxinsertw 34, 0, 12242; CHECK-64-NEXT: blr243;244; CHECK-32-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_:245; CHECK-32: # %bb.0: # %entry246; CHECK-32-NEXT: xxsldwi 0, 35, 35, 1247; CHECK-32-NEXT: xxinsertw 34, 0, 12248; CHECK-32-NEXT: blr249entry:250 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 6>251 ret <4 x float> %vecins252}253 254define <4 x float> @_Z7testInsILj3ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {255; CHECK-64-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_:256; CHECK-64: # %bb.0: # %entry257; CHECK-64-NEXT: xxswapd 0, 35258; CHECK-64-NEXT: xxinsertw 34, 0, 12259; CHECK-64-NEXT: blr260;261; CHECK-32-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_:262; CHECK-32: # %bb.0: # %entry263; CHECK-32-NEXT: xxswapd 0, 35264; CHECK-32-NEXT: xxinsertw 34, 0, 12265; CHECK-32-NEXT: blr266entry:267 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>268 ret <4 x float> %vecins269}270 271define <4 x i32> @_Z7testInsILj0ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {272; CHECK-64-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_:273; CHECK-64: # %bb.0: # %entry274; CHECK-64-NEXT: xxsldwi 0, 35, 35, 3275; CHECK-64-NEXT: xxinsertw 34, 0, 0276; CHECK-64-NEXT: blr277;278; CHECK-32-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_:279; CHECK-32: # %bb.0: # %entry280; CHECK-32-NEXT: xxsldwi 0, 35, 35, 3281; CHECK-32-NEXT: xxinsertw 34, 0, 0282; CHECK-32-NEXT: blr283entry:284 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3>285 ret <4 x i32> %vecins286}287 288define <4 x i32> @_Z7testInsILj0ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {289; CHECK-64-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_:290; CHECK-64: # %bb.0: # %entry291; CHECK-64-NEXT: xxinsertw 34, 35, 0292; CHECK-64-NEXT: blr293;294; CHECK-32-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_:295; CHECK-32: # %bb.0: # %entry296; CHECK-32-NEXT: xxinsertw 34, 35, 0297; CHECK-32-NEXT: blr298entry:299 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 5, i32 1, i32 2, i32 3>300 ret <4 x i32> %vecins301}302 303define <4 x i32> @_Z7testInsILj0ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {304; CHECK-64-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_:305; CHECK-64: # %bb.0: # %entry306; CHECK-64-NEXT: xxsldwi 0, 35, 35, 1307; CHECK-64-NEXT: xxinsertw 34, 0, 0308; CHECK-64-NEXT: blr309;310; CHECK-32-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_:311; CHECK-32: # %bb.0: # %entry312; CHECK-32-NEXT: xxsldwi 0, 35, 35, 1313; CHECK-32-NEXT: xxinsertw 34, 0, 0314; CHECK-32-NEXT: blr315entry:316 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 1, i32 2, i32 3>317 ret <4 x i32> %vecins318}319 320define <4 x i32> @_Z7testInsILj0ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {321; CHECK-64-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_:322; CHECK-64: # %bb.0: # %entry323; CHECK-64-NEXT: xxswapd 0, 35324; CHECK-64-NEXT: xxinsertw 34, 0, 0325; CHECK-64-NEXT: blr326;327; CHECK-32-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_:328; CHECK-32: # %bb.0: # %entry329; CHECK-32-NEXT: xxswapd 0, 35330; CHECK-32-NEXT: xxinsertw 34, 0, 0331; CHECK-32-NEXT: blr332entry:333 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 7, i32 1, i32 2, i32 3>334 ret <4 x i32> %vecins335}336 337define <4 x i32> @_Z7testInsILj1ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {338; CHECK-64-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_:339; CHECK-64: # %bb.0: # %entry340; CHECK-64-NEXT: xxsldwi 0, 35, 35, 3341; CHECK-64-NEXT: xxinsertw 34, 0, 4342; CHECK-64-NEXT: blr343;344; CHECK-32-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_:345; CHECK-32: # %bb.0: # %entry346; CHECK-32-NEXT: xxsldwi 0, 35, 35, 3347; CHECK-32-NEXT: xxinsertw 34, 0, 4348; CHECK-32-NEXT: blr349entry:350 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 3>351 ret <4 x i32> %vecins352}353 354define <4 x i32> @_Z7testInsILj1ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {355; CHECK-64-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_:356; CHECK-64: # %bb.0: # %entry357; CHECK-64-NEXT: xxinsertw 34, 35, 4358; CHECK-64-NEXT: blr359;360; CHECK-32-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_:361; CHECK-32: # %bb.0: # %entry362; CHECK-32-NEXT: xxinsertw 34, 35, 4363; CHECK-32-NEXT: blr364entry:365 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>366 ret <4 x i32> %vecins367}368 369define <4 x i32> @_Z7testInsILj1ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {370; CHECK-64-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_:371; CHECK-64: # %bb.0: # %entry372; CHECK-64-NEXT: xxsldwi 0, 35, 35, 1373; CHECK-64-NEXT: xxinsertw 34, 0, 4374; CHECK-64-NEXT: blr375;376; CHECK-32-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_:377; CHECK-32: # %bb.0: # %entry378; CHECK-32-NEXT: xxsldwi 0, 35, 35, 1379; CHECK-32-NEXT: xxinsertw 34, 0, 4380; CHECK-32-NEXT: blr381entry:382 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 6, i32 2, i32 3>383 ret <4 x i32> %vecins384}385 386define <4 x i32> @_Z7testInsILj1ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {387; CHECK-64-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_:388; CHECK-64: # %bb.0: # %entry389; CHECK-64-NEXT: xxswapd 0, 35390; CHECK-64-NEXT: xxinsertw 34, 0, 4391; CHECK-64-NEXT: blr392;393; CHECK-32-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_:394; CHECK-32: # %bb.0: # %entry395; CHECK-32-NEXT: xxswapd 0, 35396; CHECK-32-NEXT: xxinsertw 34, 0, 4397; CHECK-32-NEXT: blr398entry:399 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3>400 ret <4 x i32> %vecins401}402 403define <4 x i32> @_Z7testInsILj2ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {404; CHECK-64-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_:405; CHECK-64: # %bb.0: # %entry406; CHECK-64-NEXT: xxsldwi 0, 35, 35, 3407; CHECK-64-NEXT: xxinsertw 34, 0, 8408; CHECK-64-NEXT: blr409;410; CHECK-32-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_:411; CHECK-32: # %bb.0: # %entry412; CHECK-32-NEXT: xxsldwi 0, 35, 35, 3413; CHECK-32-NEXT: xxinsertw 34, 0, 8414; CHECK-32-NEXT: blr415entry:416 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 3>417 ret <4 x i32> %vecins418}419 420define <4 x i32> @_Z7testInsILj2ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {421; CHECK-64-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_:422; CHECK-64: # %bb.0: # %entry423; CHECK-64-NEXT: xxinsertw 34, 35, 8424; CHECK-64-NEXT: blr425;426; CHECK-32-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_:427; CHECK-32: # %bb.0: # %entry428; CHECK-32-NEXT: xxinsertw 34, 35, 8429; CHECK-32-NEXT: blr430entry:431 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 5, i32 3>432 ret <4 x i32> %vecins433}434 435define <4 x i32> @_Z7testInsILj2ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {436; CHECK-64-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_:437; CHECK-64: # %bb.0: # %entry438; CHECK-64-NEXT: xxsldwi 0, 35, 35, 1439; CHECK-64-NEXT: xxinsertw 34, 0, 8440; CHECK-64-NEXT: blr441;442; CHECK-32-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_:443; CHECK-32: # %bb.0: # %entry444; CHECK-32-NEXT: xxsldwi 0, 35, 35, 1445; CHECK-32-NEXT: xxinsertw 34, 0, 8446; CHECK-32-NEXT: blr447entry:448 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>449 ret <4 x i32> %vecins450}451 452define <4 x i32> @_Z7testInsILj2ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {453; CHECK-64-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_:454; CHECK-64: # %bb.0: # %entry455; CHECK-64-NEXT: xxswapd 0, 35456; CHECK-64-NEXT: xxinsertw 34, 0, 8457; CHECK-64-NEXT: blr458;459; CHECK-32-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_:460; CHECK-32: # %bb.0: # %entry461; CHECK-32-NEXT: xxswapd 0, 35462; CHECK-32-NEXT: xxinsertw 34, 0, 8463; CHECK-32-NEXT: blr464entry:465 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 7, i32 3>466 ret <4 x i32> %vecins467}468 469define <4 x i32> @_Z7testInsILj3ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {470; CHECK-64-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_:471; CHECK-64: # %bb.0: # %entry472; CHECK-64-NEXT: xxsldwi 0, 35, 35, 3473; CHECK-64-NEXT: xxinsertw 34, 0, 12474; CHECK-64-NEXT: blr475;476; CHECK-32-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_:477; CHECK-32: # %bb.0: # %entry478; CHECK-32-NEXT: xxsldwi 0, 35, 35, 3479; CHECK-32-NEXT: xxinsertw 34, 0, 12480; CHECK-32-NEXT: blr481entry:482 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4>483 ret <4 x i32> %vecins484}485 486define <4 x i32> @_Z7testInsILj3ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {487; CHECK-64-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_:488; CHECK-64: # %bb.0: # %entry489; CHECK-64-NEXT: xxinsertw 34, 35, 12490; CHECK-64-NEXT: blr491;492; CHECK-32-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_:493; CHECK-32: # %bb.0: # %entry494; CHECK-32-NEXT: xxinsertw 34, 35, 12495; CHECK-32-NEXT: blr496entry:497 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 5>498 ret <4 x i32> %vecins499}500 501define <4 x i32> @_Z7testInsILj3ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {502; CHECK-64-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_:503; CHECK-64: # %bb.0: # %entry504; CHECK-64-NEXT: xxsldwi 0, 35, 35, 1505; CHECK-64-NEXT: xxinsertw 34, 0, 12506; CHECK-64-NEXT: blr507;508; CHECK-32-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_:509; CHECK-32: # %bb.0: # %entry510; CHECK-32-NEXT: xxsldwi 0, 35, 35, 1511; CHECK-32-NEXT: xxinsertw 34, 0, 12512; CHECK-32-NEXT: blr513entry:514 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 6>515 ret <4 x i32> %vecins516}517 518define <4 x i32> @_Z7testInsILj3ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {519; CHECK-64-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_:520; CHECK-64: # %bb.0: # %entry521; CHECK-64-NEXT: xxswapd 0, 35522; CHECK-64-NEXT: xxinsertw 34, 0, 12523; CHECK-64-NEXT: blr524;525; CHECK-32-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_:526; CHECK-32: # %bb.0: # %entry527; CHECK-32-NEXT: xxswapd 0, 35528; CHECK-32-NEXT: xxinsertw 34, 0, 12529; CHECK-32-NEXT: blr530entry:531 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>532 ret <4 x i32> %vecins533}534 535define float @_Z13testUiToFpExtILj0EEfDv4_j(<4 x i32> %a) {536; CHECK-64-LABEL: _Z13testUiToFpExtILj0EEfDv4_j:537; CHECK-64: # %bb.0: # %entry538; CHECK-64-NEXT: xxextractuw 0, 34, 0539; CHECK-64-NEXT: xscvuxdsp 1, 0540; CHECK-64-NEXT: blr541;542; CHECK-32-LABEL: _Z13testUiToFpExtILj0EEfDv4_j:543; CHECK-32: # %bb.0: # %entry544; CHECK-32-NEXT: stxv 34, -32(1)545; CHECK-32-NEXT: lwz 3, -32(1)546; CHECK-32-NEXT: stw 3, -4(1)547; CHECK-32-NEXT: addi 3, 1, -4548; CHECK-32-NEXT: lfiwzx 0, 0, 3549; CHECK-32-NEXT: xscvuxdsp 1, 0550; CHECK-32-NEXT: blr551entry:552 %vecext = extractelement <4 x i32> %a, i32 0553 %conv = uitofp i32 %vecext to float554 ret float %conv555}556 557define float @_Z13testUiToFpExtILj1EEfDv4_j(<4 x i32> %a) {558; CHECK-64-LABEL: _Z13testUiToFpExtILj1EEfDv4_j:559; CHECK-64: # %bb.0: # %entry560; CHECK-64-NEXT: xxextractuw 0, 34, 4561; CHECK-64-NEXT: xscvuxdsp 1, 0562; CHECK-64-NEXT: blr563;564; CHECK-32-LABEL: _Z13testUiToFpExtILj1EEfDv4_j:565; CHECK-32: # %bb.0: # %entry566; CHECK-32-NEXT: stxv 34, -32(1)567; CHECK-32-NEXT: lwz 3, -28(1)568; CHECK-32-NEXT: stw 3, -4(1)569; CHECK-32-NEXT: addi 3, 1, -4570; CHECK-32-NEXT: lfiwzx 0, 0, 3571; CHECK-32-NEXT: xscvuxdsp 1, 0572; CHECK-32-NEXT: blr573entry:574 %vecext = extractelement <4 x i32> %a, i32 1575 %conv = uitofp i32 %vecext to float576 ret float %conv577}578 579define float @_Z13testUiToFpExtILj2EEfDv4_j(<4 x i32> %a) {580; CHECK-64-LABEL: _Z13testUiToFpExtILj2EEfDv4_j:581; CHECK-64: # %bb.0: # %entry582; CHECK-64-NEXT: xxextractuw 0, 34, 8583; CHECK-64-NEXT: xscvuxdsp 1, 0584; CHECK-64-NEXT: blr585;586; CHECK-32-LABEL: _Z13testUiToFpExtILj2EEfDv4_j:587; CHECK-32: # %bb.0: # %entry588; CHECK-32-NEXT: stxv 34, -32(1)589; CHECK-32-NEXT: lwz 3, -24(1)590; CHECK-32-NEXT: stw 3, -4(1)591; CHECK-32-NEXT: addi 3, 1, -4592; CHECK-32-NEXT: lfiwzx 0, 0, 3593; CHECK-32-NEXT: xscvuxdsp 1, 0594; CHECK-32-NEXT: blr595entry:596 %vecext = extractelement <4 x i32> %a, i32 2597 %conv = uitofp i32 %vecext to float598 ret float %conv599}600 601define float @_Z13testUiToFpExtILj3EEfDv4_j(<4 x i32> %a) {602; CHECK-64-LABEL: _Z13testUiToFpExtILj3EEfDv4_j:603; CHECK-64: # %bb.0: # %entry604; CHECK-64-NEXT: xxextractuw 0, 34, 12605; CHECK-64-NEXT: xscvuxdsp 1, 0606; CHECK-64-NEXT: blr607;608; CHECK-32-LABEL: _Z13testUiToFpExtILj3EEfDv4_j:609; CHECK-32: # %bb.0: # %entry610; CHECK-32-NEXT: stxv 34, -32(1)611; CHECK-32-NEXT: lwz 3, -20(1)612; CHECK-32-NEXT: stw 3, -4(1)613; CHECK-32-NEXT: addi 3, 1, -4614; CHECK-32-NEXT: lfiwzx 0, 0, 3615; CHECK-32-NEXT: xscvuxdsp 1, 0616; CHECK-32-NEXT: blr617entry:618 %vecext = extractelement <4 x i32> %a, i32 3619 %conv = uitofp i32 %vecext to float620 ret float %conv621}622 623; Verify we generate optimal code for unsigned vector int elem extract followed624; by conversion to double625 626define double @conv2dlbTestui0(<4 x i32> %a) {627; CHECK-64-LABEL: conv2dlbTestui0:628; CHECK-64: # %bb.0: # %entry629; CHECK-64-NEXT: xxextractuw 0, 34, 0630; CHECK-64-NEXT: xscvuxddp 1, 0631; CHECK-64-NEXT: blr632;633; CHECK-32-LABEL: conv2dlbTestui0:634; CHECK-32: # %bb.0: # %entry635; CHECK-32-NEXT: stxv 34, -32(1)636; CHECK-32-NEXT: lwz 3, -32(1)637; CHECK-32-NEXT: stw 3, -4(1)638; CHECK-32-NEXT: addi 3, 1, -4639; CHECK-32-NEXT: lfiwzx 0, 0, 3640; CHECK-32-NEXT: xscvuxddp 1, 0641; CHECK-32-NEXT: blr642entry:643 %0 = extractelement <4 x i32> %a, i32 0644 %1 = uitofp i32 %0 to double645 ret double %1646}647 648define double @conv2dlbTestui1(<4 x i32> %a) {649; CHECK-64-LABEL: conv2dlbTestui1:650; CHECK-64: # %bb.0: # %entry651; CHECK-64-NEXT: xxextractuw 0, 34, 4652; CHECK-64-NEXT: xscvuxddp 1, 0653; CHECK-64-NEXT: blr654;655; CHECK-32-LABEL: conv2dlbTestui1:656; CHECK-32: # %bb.0: # %entry657; CHECK-32-NEXT: stxv 34, -32(1)658; CHECK-32-NEXT: lwz 3, -28(1)659; CHECK-32-NEXT: stw 3, -4(1)660; CHECK-32-NEXT: addi 3, 1, -4661; CHECK-32-NEXT: lfiwzx 0, 0, 3662; CHECK-32-NEXT: xscvuxddp 1, 0663; CHECK-32-NEXT: blr664entry:665 %0 = extractelement <4 x i32> %a, i32 1666 %1 = uitofp i32 %0 to double667 ret double %1668}669 670define double @conv2dlbTestui2(<4 x i32> %a) {671; CHECK-64-LABEL: conv2dlbTestui2:672; CHECK-64: # %bb.0: # %entry673; CHECK-64-NEXT: xxextractuw 0, 34, 8674; CHECK-64-NEXT: xscvuxddp 1, 0675; CHECK-64-NEXT: blr676;677; CHECK-32-LABEL: conv2dlbTestui2:678; CHECK-32: # %bb.0: # %entry679; CHECK-32-NEXT: stxv 34, -32(1)680; CHECK-32-NEXT: lwz 3, -24(1)681; CHECK-32-NEXT: stw 3, -4(1)682; CHECK-32-NEXT: addi 3, 1, -4683; CHECK-32-NEXT: lfiwzx 0, 0, 3684; CHECK-32-NEXT: xscvuxddp 1, 0685; CHECK-32-NEXT: blr686entry:687 %0 = extractelement <4 x i32> %a, i32 2688 %1 = uitofp i32 %0 to double689 ret double %1690}691 692define double @conv2dlbTestui3(<4 x i32> %a) {693; CHECK-64-LABEL: conv2dlbTestui3:694; CHECK-64: # %bb.0: # %entry695; CHECK-64-NEXT: xxextractuw 0, 34, 12696; CHECK-64-NEXT: xscvuxddp 1, 0697; CHECK-64-NEXT: blr698;699; CHECK-32-LABEL: conv2dlbTestui3:700; CHECK-32: # %bb.0: # %entry701; CHECK-32-NEXT: stxv 34, -32(1)702; CHECK-32-NEXT: lwz 3, -20(1)703; CHECK-32-NEXT: stw 3, -4(1)704; CHECK-32-NEXT: addi 3, 1, -4705; CHECK-32-NEXT: lfiwzx 0, 0, 3706; CHECK-32-NEXT: xscvuxddp 1, 0707; CHECK-32-NEXT: blr708entry:709 %0 = extractelement <4 x i32> %a, i32 3710 %1 = uitofp i32 %0 to double711 ret double %1712}713 714; verify we don't crash for variable elem extract715define double @conv2dlbTestuiVar(<4 x i32> %a, i32 zeroext %elem) {716; CHECK-64-LABEL: conv2dlbTestuiVar:717; CHECK-64: # %bb.0: # %entry718; CHECK-64-NEXT: rlwinm 3, 3, 2, 28, 29719; CHECK-64-NEXT: vextuwlx 3, 3, 2720; CHECK-64-NEXT: mtfprwz 0, 3721; CHECK-64-NEXT: xscvuxddp 1, 0722; CHECK-64-NEXT: blr723;724; CHECK-32-LABEL: conv2dlbTestuiVar:725; CHECK-32: # %bb.0: # %entry726; CHECK-32-NEXT: addi 4, 1, -32727; CHECK-32-NEXT: rlwinm 3, 3, 2, 28, 29728; CHECK-32-NEXT: stxv 34, -32(1)729; CHECK-32-NEXT: lwzx 3, 4, 3730; CHECK-32-NEXT: stw 3, -4(1)731; CHECK-32-NEXT: addi 3, 1, -4732; CHECK-32-NEXT: lfiwzx 0, 0, 3733; CHECK-32-NEXT: xscvuxddp 1, 0734; CHECK-32-NEXT: blr735entry:736 %vecext = extractelement <4 x i32> %a, i32 %elem737 %conv = uitofp i32 %vecext to double738 ret double %conv739}740 741define <4 x float> @_Z10testInsEltILj0EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {742; CHECK-64-LABEL: _Z10testInsEltILj0EDv4_ffET0_S1_T1_:743; CHECK-64: # %bb.0: # %entry744; CHECK-64-NEXT: xscvdpspn 0, 1745; CHECK-64-NEXT: xxinsertw 34, 0, 0746; CHECK-64-NEXT: blr747;748; CHECK-32-LABEL: _Z10testInsEltILj0EDv4_ffET0_S1_T1_:749; CHECK-32: # %bb.0: # %entry750; CHECK-32-NEXT: xscvdpspn 0, 1751; CHECK-32-NEXT: xxinsertw 34, 0, 0752; CHECK-32-NEXT: blr753entry:754 %vecins = insertelement <4 x float> %a, float %b, i32 0755 ret <4 x float> %vecins756}757 758define <4 x float> @_Z10testInsEltILj1EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {759; CHECK-64-LABEL: _Z10testInsEltILj1EDv4_ffET0_S1_T1_:760; CHECK-64: # %bb.0: # %entry761; CHECK-64-NEXT: xscvdpspn 0, 1762; CHECK-64-NEXT: xxinsertw 34, 0, 4763; CHECK-64-NEXT: blr764;765; CHECK-32-LABEL: _Z10testInsEltILj1EDv4_ffET0_S1_T1_:766; CHECK-32: # %bb.0: # %entry767; CHECK-32-NEXT: xscvdpspn 0, 1768; CHECK-32-NEXT: xxinsertw 34, 0, 4769; CHECK-32-NEXT: blr770entry:771 %vecins = insertelement <4 x float> %a, float %b, i32 1772 ret <4 x float> %vecins773}774 775define <4 x float> @_Z10testInsEltILj2EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {776; CHECK-64-LABEL: _Z10testInsEltILj2EDv4_ffET0_S1_T1_:777; CHECK-64: # %bb.0: # %entry778; CHECK-64-NEXT: xscvdpspn 0, 1779; CHECK-64-NEXT: xxinsertw 34, 0, 8780; CHECK-64-NEXT: blr781;782; CHECK-32-LABEL: _Z10testInsEltILj2EDv4_ffET0_S1_T1_:783; CHECK-32: # %bb.0: # %entry784; CHECK-32-NEXT: xscvdpspn 0, 1785; CHECK-32-NEXT: xxinsertw 34, 0, 8786; CHECK-32-NEXT: blr787entry:788 %vecins = insertelement <4 x float> %a, float %b, i32 2789 ret <4 x float> %vecins790}791 792define <4 x float> @_Z10testInsEltILj3EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {793; CHECK-64-LABEL: _Z10testInsEltILj3EDv4_ffET0_S1_T1_:794; CHECK-64: # %bb.0: # %entry795; CHECK-64-NEXT: xscvdpspn 0, 1796; CHECK-64-NEXT: xxinsertw 34, 0, 12797; CHECK-64-NEXT: blr798;799; CHECK-32-LABEL: _Z10testInsEltILj3EDv4_ffET0_S1_T1_:800; CHECK-32: # %bb.0: # %entry801; CHECK-32-NEXT: xscvdpspn 0, 1802; CHECK-32-NEXT: xxinsertw 34, 0, 12803; CHECK-32-NEXT: blr804entry:805 %vecins = insertelement <4 x float> %a, float %b, i32 3806 ret <4 x float> %vecins807}808 809define <4 x i32> @_Z10testInsEltILj0EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {810; CHECK-64-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_:811; CHECK-64: # %bb.0: # %entry812; CHECK-64-NEXT: mtfprwz 0, 3813; CHECK-64-NEXT: xxinsertw 34, 0, 0814; CHECK-64-NEXT: blr815;816; CHECK-32-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_:817; CHECK-32: # %bb.0: # %entry818; CHECK-32-NEXT: mtfprwz 0, 3819; CHECK-32-NEXT: xxinsertw 34, 0, 0820; CHECK-32-NEXT: blr821entry:822 %vecins = insertelement <4 x i32> %a, i32 %b, i32 0823 ret <4 x i32> %vecins824}825 826define <4 x i32> @_Z10testInsEltILj1EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {827; CHECK-64-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_:828; CHECK-64: # %bb.0: # %entry829; CHECK-64-NEXT: mtfprwz 0, 3830; CHECK-64-NEXT: xxinsertw 34, 0, 4831; CHECK-64-NEXT: blr832;833; CHECK-32-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_:834; CHECK-32: # %bb.0: # %entry835; CHECK-32-NEXT: mtfprwz 0, 3836; CHECK-32-NEXT: xxinsertw 34, 0, 4837; CHECK-32-NEXT: blr838entry:839 %vecins = insertelement <4 x i32> %a, i32 %b, i32 1840 ret <4 x i32> %vecins841}842 843define <4 x i32> @_Z10testInsEltILj2EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {844; CHECK-64-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_:845; CHECK-64: # %bb.0: # %entry846; CHECK-64-NEXT: mtfprwz 0, 3847; CHECK-64-NEXT: xxinsertw 34, 0, 8848; CHECK-64-NEXT: blr849;850; CHECK-32-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_:851; CHECK-32: # %bb.0: # %entry852; CHECK-32-NEXT: mtfprwz 0, 3853; CHECK-32-NEXT: xxinsertw 34, 0, 8854; CHECK-32-NEXT: blr855entry:856 %vecins = insertelement <4 x i32> %a, i32 %b, i32 2857 ret <4 x i32> %vecins858}859 860define <4 x i32> @_Z10testInsEltILj3EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {861; CHECK-64-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_:862; CHECK-64: # %bb.0: # %entry863; CHECK-64-NEXT: mtfprwz 0, 3864; CHECK-64-NEXT: xxinsertw 34, 0, 12865; CHECK-64-NEXT: blr866;867; CHECK-32-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_:868; CHECK-32: # %bb.0: # %entry869; CHECK-32-NEXT: mtfprwz 0, 3870; CHECK-32-NEXT: xxinsertw 34, 0, 12871; CHECK-32-NEXT: blr872entry:873 %vecins = insertelement <4 x i32> %a, i32 %b, i32 3874 ret <4 x i32> %vecins875}876 877define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {878; CHECK-64-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_r:879; CHECK-64: # %bb.0: # %entry880; CHECK-64-NEXT: xxsldwi 0, 35, 35, 3881; CHECK-64-NEXT: xxinsertw 34, 0, 0882; CHECK-64-NEXT: blr883;884; CHECK-32-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_r:885; CHECK-32: # %bb.0: # %entry886; CHECK-32-NEXT: xxsldwi 0, 35, 35, 3887; CHECK-32-NEXT: xxinsertw 34, 0, 0888; CHECK-32-NEXT: blr889entry:890 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>891 ret <4 x float> %vecins892}893 894define <4 x float> @_Z7testInsILj0ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {895; CHECK-64-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_r:896; CHECK-64: # %bb.0: # %entry897; CHECK-64-NEXT: xxinsertw 34, 35, 0898; CHECK-64-NEXT: blr899;900; CHECK-32-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_r:901; CHECK-32: # %bb.0: # %entry902; CHECK-32-NEXT: xxinsertw 34, 35, 0903; CHECK-32-NEXT: blr904entry:905 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 1, i32 5, i32 6, i32 7>906 ret <4 x float> %vecins907}908 909define <4 x float> @_Z7testInsILj0ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {910; CHECK-64-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_r:911; CHECK-64: # %bb.0: # %entry912; CHECK-64-NEXT: xxsldwi 0, 35, 35, 1913; CHECK-64-NEXT: xxinsertw 34, 0, 0914; CHECK-64-NEXT: blr915;916; CHECK-32-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_r:917; CHECK-32: # %bb.0: # %entry918; CHECK-32-NEXT: xxsldwi 0, 35, 35, 1919; CHECK-32-NEXT: xxinsertw 34, 0, 0920; CHECK-32-NEXT: blr921entry:922 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 2, i32 5, i32 6, i32 7>923 ret <4 x float> %vecins924}925 926define <4 x float> @_Z7testInsILj0ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {927; CHECK-64-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_r:928; CHECK-64: # %bb.0: # %entry929; CHECK-64-NEXT: xxswapd 0, 35930; CHECK-64-NEXT: xxinsertw 34, 0, 0931; CHECK-64-NEXT: blr932;933; CHECK-32-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_r:934; CHECK-32: # %bb.0: # %entry935; CHECK-32-NEXT: xxswapd 0, 35936; CHECK-32-NEXT: xxinsertw 34, 0, 0937; CHECK-32-NEXT: blr938entry:939 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 3, i32 5, i32 6, i32 7>940 ret <4 x float> %vecins941}942 943define <4 x float> @_Z7testInsILj1ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {944; CHECK-64-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_r:945; CHECK-64: # %bb.0: # %entry946; CHECK-64-NEXT: xxsldwi 0, 35, 35, 3947; CHECK-64-NEXT: xxinsertw 34, 0, 4948; CHECK-64-NEXT: blr949;950; CHECK-32-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_r:951; CHECK-32: # %bb.0: # %entry952; CHECK-32-NEXT: xxsldwi 0, 35, 35, 3953; CHECK-32-NEXT: xxinsertw 34, 0, 4954; CHECK-32-NEXT: blr955entry:956 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 0, i32 6, i32 7>957 ret <4 x float> %vecins958}959 960define <4 x float> @_Z7testInsILj1ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {961; CHECK-64-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_r:962; CHECK-64: # %bb.0: # %entry963; CHECK-64-NEXT: xxinsertw 34, 35, 4964; CHECK-64-NEXT: blr965;966; CHECK-32-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_r:967; CHECK-32: # %bb.0: # %entry968; CHECK-32-NEXT: xxinsertw 34, 35, 4969; CHECK-32-NEXT: blr970entry:971 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 7>972 ret <4 x float> %vecins973}974 975define <4 x float> @_Z7testInsILj1ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {976; CHECK-64-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_r:977; CHECK-64: # %bb.0: # %entry978; CHECK-64-NEXT: xxsldwi 0, 35, 35, 1979; CHECK-64-NEXT: xxinsertw 34, 0, 4980; CHECK-64-NEXT: blr981;982; CHECK-32-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_r:983; CHECK-32: # %bb.0: # %entry984; CHECK-32-NEXT: xxsldwi 0, 35, 35, 1985; CHECK-32-NEXT: xxinsertw 34, 0, 4986; CHECK-32-NEXT: blr987entry:988 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 2, i32 6, i32 7>989 ret <4 x float> %vecins990}991 992define <4 x float> @_Z7testInsILj1ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {993; CHECK-64-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_r:994; CHECK-64: # %bb.0: # %entry995; CHECK-64-NEXT: xxswapd 0, 35996; CHECK-64-NEXT: xxinsertw 34, 0, 4997; CHECK-64-NEXT: blr998;999; CHECK-32-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_r:1000; CHECK-32: # %bb.0: # %entry1001; CHECK-32-NEXT: xxswapd 0, 351002; CHECK-32-NEXT: xxinsertw 34, 0, 41003; CHECK-32-NEXT: blr1004entry:1005 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 3, i32 6, i32 7>1006 ret <4 x float> %vecins1007}1008 1009define <4 x float> @_Z7testInsILj2ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {1010; CHECK-64-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_r:1011; CHECK-64: # %bb.0: # %entry1012; CHECK-64-NEXT: xxsldwi 0, 35, 35, 31013; CHECK-64-NEXT: xxinsertw 34, 0, 81014; CHECK-64-NEXT: blr1015;1016; CHECK-32-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_r:1017; CHECK-32: # %bb.0: # %entry1018; CHECK-32-NEXT: xxsldwi 0, 35, 35, 31019; CHECK-32-NEXT: xxinsertw 34, 0, 81020; CHECK-32-NEXT: blr1021entry:1022 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 0, i32 7>1023 ret <4 x float> %vecins1024}1025 1026define <4 x float> @_Z7testInsILj2ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {1027; CHECK-64-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_r:1028; CHECK-64: # %bb.0: # %entry1029; CHECK-64-NEXT: xxinsertw 34, 35, 81030; CHECK-64-NEXT: blr1031;1032; CHECK-32-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_r:1033; CHECK-32: # %bb.0: # %entry1034; CHECK-32-NEXT: xxinsertw 34, 35, 81035; CHECK-32-NEXT: blr1036entry:1037 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 7>1038 ret <4 x float> %vecins1039}1040 1041define <4 x float> @_Z7testInsILj2ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {1042; CHECK-64-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_r:1043; CHECK-64: # %bb.0: # %entry1044; CHECK-64-NEXT: xxsldwi 0, 35, 35, 11045; CHECK-64-NEXT: xxinsertw 34, 0, 81046; CHECK-64-NEXT: blr1047;1048; CHECK-32-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_r:1049; CHECK-32: # %bb.0: # %entry1050; CHECK-32-NEXT: xxsldwi 0, 35, 35, 11051; CHECK-32-NEXT: xxinsertw 34, 0, 81052; CHECK-32-NEXT: blr1053entry:1054 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 7>1055 ret <4 x float> %vecins1056}1057 1058define <4 x float> @_Z7testInsILj2ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {1059; CHECK-64-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_r:1060; CHECK-64: # %bb.0: # %entry1061; CHECK-64-NEXT: xxswapd 0, 351062; CHECK-64-NEXT: xxinsertw 34, 0, 81063; CHECK-64-NEXT: blr1064;1065; CHECK-32-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_r:1066; CHECK-32: # %bb.0: # %entry1067; CHECK-32-NEXT: xxswapd 0, 351068; CHECK-32-NEXT: xxinsertw 34, 0, 81069; CHECK-32-NEXT: blr1070entry:1071 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 3, i32 7>1072 ret <4 x float> %vecins1073}1074 1075define <4 x float> @_Z7testInsILj3ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {1076; CHECK-64-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_r:1077; CHECK-64: # %bb.0: # %entry1078; CHECK-64-NEXT: xxsldwi 0, 35, 35, 31079; CHECK-64-NEXT: xxinsertw 34, 0, 121080; CHECK-64-NEXT: blr1081;1082; CHECK-32-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_r:1083; CHECK-32: # %bb.0: # %entry1084; CHECK-32-NEXT: xxsldwi 0, 35, 35, 31085; CHECK-32-NEXT: xxinsertw 34, 0, 121086; CHECK-32-NEXT: blr1087entry:1088 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 0>1089 ret <4 x float> %vecins1090}1091 1092define <4 x float> @_Z7testInsILj3ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {1093; CHECK-64-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_r:1094; CHECK-64: # %bb.0: # %entry1095; CHECK-64-NEXT: xxinsertw 34, 35, 121096; CHECK-64-NEXT: blr1097;1098; CHECK-32-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_r:1099; CHECK-32: # %bb.0: # %entry1100; CHECK-32-NEXT: xxinsertw 34, 35, 121101; CHECK-32-NEXT: blr1102entry:1103 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 1>1104 ret <4 x float> %vecins1105}1106 1107define <4 x float> @_Z7testInsILj3ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {1108; CHECK-64-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_r:1109; CHECK-64: # %bb.0: # %entry1110; CHECK-64-NEXT: xxsldwi 0, 35, 35, 11111; CHECK-64-NEXT: xxinsertw 34, 0, 121112; CHECK-64-NEXT: blr1113;1114; CHECK-32-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_r:1115; CHECK-32: # %bb.0: # %entry1116; CHECK-32-NEXT: xxsldwi 0, 35, 35, 11117; CHECK-32-NEXT: xxinsertw 34, 0, 121118; CHECK-32-NEXT: blr1119entry:1120 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 2>1121 ret <4 x float> %vecins1122}1123 1124define <4 x float> @_Z7testInsILj3ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {1125; CHECK-64-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_r:1126; CHECK-64: # %bb.0: # %entry1127; CHECK-64-NEXT: xxswapd 0, 351128; CHECK-64-NEXT: xxinsertw 34, 0, 121129; CHECK-64-NEXT: blr1130;1131; CHECK-32-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_r:1132; CHECK-32: # %bb.0: # %entry1133; CHECK-32-NEXT: xxswapd 0, 351134; CHECK-32-NEXT: xxinsertw 34, 0, 121135; CHECK-32-NEXT: blr1136entry:1137 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 3>1138 ret <4 x float> %vecins1139}1140 1141define <4 x i32> @_Z7testInsILj0ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {1142; CHECK-64-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_r:1143; CHECK-64: # %bb.0: # %entry1144; CHECK-64-NEXT: xxsldwi 0, 35, 35, 31145; CHECK-64-NEXT: xxinsertw 34, 0, 01146; CHECK-64-NEXT: blr1147;1148; CHECK-32-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_r:1149; CHECK-32: # %bb.0: # %entry1150; CHECK-32-NEXT: xxsldwi 0, 35, 35, 31151; CHECK-32-NEXT: xxinsertw 34, 0, 01152; CHECK-32-NEXT: blr1153entry:1154 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>1155 ret <4 x i32> %vecins1156}1157 1158define <4 x i32> @_Z7testInsILj0ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {1159; CHECK-64-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_r:1160; CHECK-64: # %bb.0: # %entry1161; CHECK-64-NEXT: xxinsertw 34, 35, 01162; CHECK-64-NEXT: blr1163;1164; CHECK-32-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_r:1165; CHECK-32: # %bb.0: # %entry1166; CHECK-32-NEXT: xxinsertw 34, 35, 01167; CHECK-32-NEXT: blr1168entry:1169 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 1, i32 5, i32 6, i32 7>1170 ret <4 x i32> %vecins1171}1172 1173define <4 x i32> @_Z7testInsILj0ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {1174; CHECK-64-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_r:1175; CHECK-64: # %bb.0: # %entry1176; CHECK-64-NEXT: xxsldwi 0, 35, 35, 11177; CHECK-64-NEXT: xxinsertw 34, 0, 01178; CHECK-64-NEXT: blr1179;1180; CHECK-32-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_r:1181; CHECK-32: # %bb.0: # %entry1182; CHECK-32-NEXT: xxsldwi 0, 35, 35, 11183; CHECK-32-NEXT: xxinsertw 34, 0, 01184; CHECK-32-NEXT: blr1185entry:1186 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 2, i32 5, i32 6, i32 7>1187 ret <4 x i32> %vecins1188}1189 1190define <4 x i32> @_Z7testInsILj0ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {1191; CHECK-64-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_r:1192; CHECK-64: # %bb.0: # %entry1193; CHECK-64-NEXT: xxswapd 0, 351194; CHECK-64-NEXT: xxinsertw 34, 0, 01195; CHECK-64-NEXT: blr1196;1197; CHECK-32-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_r:1198; CHECK-32: # %bb.0: # %entry1199; CHECK-32-NEXT: xxswapd 0, 351200; CHECK-32-NEXT: xxinsertw 34, 0, 01201; CHECK-32-NEXT: blr1202entry:1203 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 3, i32 5, i32 6, i32 7>1204 ret <4 x i32> %vecins1205}1206 1207define <4 x i32> @_Z7testInsILj1ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {1208; CHECK-64-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_r:1209; CHECK-64: # %bb.0: # %entry1210; CHECK-64-NEXT: xxsldwi 0, 35, 35, 31211; CHECK-64-NEXT: xxinsertw 34, 0, 41212; CHECK-64-NEXT: blr1213;1214; CHECK-32-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_r:1215; CHECK-32: # %bb.0: # %entry1216; CHECK-32-NEXT: xxsldwi 0, 35, 35, 31217; CHECK-32-NEXT: xxinsertw 34, 0, 41218; CHECK-32-NEXT: blr1219entry:1220 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 0, i32 6, i32 7>1221 ret <4 x i32> %vecins1222}1223 1224define <4 x i32> @_Z7testInsILj1ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {1225; CHECK-64-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_r:1226; CHECK-64: # %bb.0: # %entry1227; CHECK-64-NEXT: xxinsertw 34, 35, 41228; CHECK-64-NEXT: blr1229;1230; CHECK-32-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_r:1231; CHECK-32: # %bb.0: # %entry1232; CHECK-32-NEXT: xxinsertw 34, 35, 41233; CHECK-32-NEXT: blr1234entry:1235 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 7>1236 ret <4 x i32> %vecins1237}1238 1239define <4 x i32> @_Z7testInsILj1ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {1240; CHECK-64-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_r:1241; CHECK-64: # %bb.0: # %entry1242; CHECK-64-NEXT: xxsldwi 0, 35, 35, 11243; CHECK-64-NEXT: xxinsertw 34, 0, 41244; CHECK-64-NEXT: blr1245;1246; CHECK-32-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_r:1247; CHECK-32: # %bb.0: # %entry1248; CHECK-32-NEXT: xxsldwi 0, 35, 35, 11249; CHECK-32-NEXT: xxinsertw 34, 0, 41250; CHECK-32-NEXT: blr1251entry:1252 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 2, i32 6, i32 7>1253 ret <4 x i32> %vecins1254}1255 1256define <4 x i32> @_Z7testInsILj1ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {1257; CHECK-64-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_r:1258; CHECK-64: # %bb.0: # %entry1259; CHECK-64-NEXT: xxswapd 0, 351260; CHECK-64-NEXT: xxinsertw 34, 0, 41261; CHECK-64-NEXT: blr1262;1263; CHECK-32-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_r:1264; CHECK-32: # %bb.0: # %entry1265; CHECK-32-NEXT: xxswapd 0, 351266; CHECK-32-NEXT: xxinsertw 34, 0, 41267; CHECK-32-NEXT: blr1268entry:1269 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 3, i32 6, i32 7>1270 ret <4 x i32> %vecins1271}1272 1273define <4 x i32> @_Z7testInsILj2ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {1274; CHECK-64-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_r:1275; CHECK-64: # %bb.0: # %entry1276; CHECK-64-NEXT: xxsldwi 0, 35, 35, 31277; CHECK-64-NEXT: xxinsertw 34, 0, 81278; CHECK-64-NEXT: blr1279;1280; CHECK-32-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_r:1281; CHECK-32: # %bb.0: # %entry1282; CHECK-32-NEXT: xxsldwi 0, 35, 35, 31283; CHECK-32-NEXT: xxinsertw 34, 0, 81284; CHECK-32-NEXT: blr1285entry:1286 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 0, i32 7>1287 ret <4 x i32> %vecins1288}1289 1290define <4 x i32> @_Z7testInsILj2ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {1291; CHECK-64-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_r:1292; CHECK-64: # %bb.0: # %entry1293; CHECK-64-NEXT: xxinsertw 34, 35, 81294; CHECK-64-NEXT: blr1295;1296; CHECK-32-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_r:1297; CHECK-32: # %bb.0: # %entry1298; CHECK-32-NEXT: xxinsertw 34, 35, 81299; CHECK-32-NEXT: blr1300entry:1301 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 7>1302 ret <4 x i32> %vecins1303}1304 1305define <4 x i32> @_Z7testInsILj2ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {1306; CHECK-64-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_r:1307; CHECK-64: # %bb.0: # %entry1308; CHECK-64-NEXT: xxsldwi 0, 35, 35, 11309; CHECK-64-NEXT: xxinsertw 34, 0, 81310; CHECK-64-NEXT: blr1311;1312; CHECK-32-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_r:1313; CHECK-32: # %bb.0: # %entry1314; CHECK-32-NEXT: xxsldwi 0, 35, 35, 11315; CHECK-32-NEXT: xxinsertw 34, 0, 81316; CHECK-32-NEXT: blr1317entry:1318 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 7>1319 ret <4 x i32> %vecins1320}1321 1322define <4 x i32> @_Z7testInsILj2ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {1323; CHECK-64-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_r:1324; CHECK-64: # %bb.0: # %entry1325; CHECK-64-NEXT: xxswapd 0, 351326; CHECK-64-NEXT: xxinsertw 34, 0, 81327; CHECK-64-NEXT: blr1328;1329; CHECK-32-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_r:1330; CHECK-32: # %bb.0: # %entry1331; CHECK-32-NEXT: xxswapd 0, 351332; CHECK-32-NEXT: xxinsertw 34, 0, 81333; CHECK-32-NEXT: blr1334entry:1335 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 3, i32 7>1336 ret <4 x i32> %vecins1337}1338 1339define <4 x i32> @_Z7testInsILj3ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {1340; CHECK-64-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_r:1341; CHECK-64: # %bb.0: # %entry1342; CHECK-64-NEXT: xxsldwi 0, 35, 35, 31343; CHECK-64-NEXT: xxinsertw 34, 0, 121344; CHECK-64-NEXT: blr1345;1346; CHECK-32-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_r:1347; CHECK-32: # %bb.0: # %entry1348; CHECK-32-NEXT: xxsldwi 0, 35, 35, 31349; CHECK-32-NEXT: xxinsertw 34, 0, 121350; CHECK-32-NEXT: blr1351entry:1352 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 0>1353 ret <4 x i32> %vecins1354}1355 1356define <4 x i32> @_Z7testInsILj3ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {1357; CHECK-64-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_r:1358; CHECK-64: # %bb.0: # %entry1359; CHECK-64-NEXT: xxinsertw 34, 35, 121360; CHECK-64-NEXT: blr1361;1362; CHECK-32-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_r:1363; CHECK-32: # %bb.0: # %entry1364; CHECK-32-NEXT: xxinsertw 34, 35, 121365; CHECK-32-NEXT: blr1366entry:1367 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 1>1368 ret <4 x i32> %vecins1369}1370 1371define <4 x i32> @_Z7testInsILj3ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {1372; CHECK-64-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_r:1373; CHECK-64: # %bb.0: # %entry1374; CHECK-64-NEXT: xxsldwi 0, 35, 35, 11375; CHECK-64-NEXT: xxinsertw 34, 0, 121376; CHECK-64-NEXT: blr1377;1378; CHECK-32-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_r:1379; CHECK-32: # %bb.0: # %entry1380; CHECK-32-NEXT: xxsldwi 0, 35, 35, 11381; CHECK-32-NEXT: xxinsertw 34, 0, 121382; CHECK-32-NEXT: blr1383entry:1384 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 2>1385 ret <4 x i32> %vecins1386}1387 1388define <4 x i32> @_Z7testInsILj3ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {1389; CHECK-64-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_r:1390; CHECK-64: # %bb.0: # %entry1391; CHECK-64-NEXT: xxswapd 0, 351392; CHECK-64-NEXT: xxinsertw 34, 0, 121393; CHECK-64-NEXT: blr1394;1395; CHECK-32-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_r:1396; CHECK-32: # %bb.0: # %entry1397; CHECK-32-NEXT: xxswapd 0, 351398; CHECK-32-NEXT: xxinsertw 34, 0, 121399; CHECK-32-NEXT: blr1400entry:1401 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 3>1402 ret <4 x i32> %vecins1403}1404define <4 x float> @testSameVecEl0BE(<4 x float> %a) {1405; CHECK-64-LABEL: testSameVecEl0BE:1406; CHECK-64: # %bb.0: # %entry1407; CHECK-64-NEXT: xxinsertw 34, 34, 01408; CHECK-64-NEXT: blr1409;1410; CHECK-32-LABEL: testSameVecEl0BE:1411; CHECK-32: # %bb.0: # %entry1412; CHECK-32-NEXT: xxinsertw 34, 34, 01413; CHECK-32-NEXT: blr1414entry:1415 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 5, i32 1, i32 2, i32 3>1416 ret <4 x float> %vecins1417}1418define <4 x float> @testSameVecEl2BE(<4 x float> %a) {1419; CHECK-64-LABEL: testSameVecEl2BE:1420; CHECK-64: # %bb.0: # %entry1421; CHECK-64-NEXT: xxinsertw 34, 34, 81422; CHECK-64-NEXT: blr1423;1424; CHECK-32-LABEL: testSameVecEl2BE:1425; CHECK-32: # %bb.0: # %entry1426; CHECK-32-NEXT: xxinsertw 34, 34, 81427; CHECK-32-NEXT: blr1428entry:1429 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 5, i32 3>1430 ret <4 x float> %vecins1431}1432define <4 x float> @testSameVecEl3BE(<4 x float> %a) {1433; CHECK-64-LABEL: testSameVecEl3BE:1434; CHECK-64: # %bb.0: # %entry1435; CHECK-64-NEXT: xxinsertw 34, 34, 121436; CHECK-64-NEXT: blr1437;1438; CHECK-32-LABEL: testSameVecEl3BE:1439; CHECK-32: # %bb.0: # %entry1440; CHECK-32-NEXT: xxinsertw 34, 34, 121441; CHECK-32-NEXT: blr1442entry:1443 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 5>1444 ret <4 x float> %vecins1445}1446define <4 x float> @testSameVecEl0LE(<4 x float> %a) {1447; CHECK-64-LABEL: testSameVecEl0LE:1448; CHECK-64: # %bb.0: # %entry1449; CHECK-64-NEXT: ld 3, L..C0(2) # %const.01450; CHECK-64-NEXT: lxv 0, 0(3)1451; CHECK-64-NEXT: xxperm 34, 34, 01452; CHECK-64-NEXT: blr1453;1454; CHECK-32-LABEL: testSameVecEl0LE:1455; CHECK-32: # %bb.0: # %entry1456; CHECK-32-NEXT: lwz 3, L..C0(2) # %const.01457; CHECK-32-NEXT: lxv 0, 0(3)1458; CHECK-32-NEXT: xxperm 34, 34, 01459; CHECK-32-NEXT: blr1460entry:1461 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 6, i32 1, i32 2, i32 3>1462 ret <4 x float> %vecins1463}1464define <4 x float> @testSameVecEl1LE(<4 x float> %a) {1465; CHECK-64-LABEL: testSameVecEl1LE:1466; CHECK-64: # %bb.0: # %entry1467; CHECK-64-NEXT: ld 3, L..C1(2) # %const.01468; CHECK-64-NEXT: lxv 0, 0(3)1469; CHECK-64-NEXT: xxperm 34, 34, 01470; CHECK-64-NEXT: blr1471;1472; CHECK-32-LABEL: testSameVecEl1LE:1473; CHECK-32: # %bb.0: # %entry1474; CHECK-32-NEXT: lwz 3, L..C1(2) # %const.01475; CHECK-32-NEXT: lxv 0, 0(3)1476; CHECK-32-NEXT: xxperm 34, 34, 01477; CHECK-32-NEXT: blr1478entry:1479 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 6, i32 2, i32 3>1480 ret <4 x float> %vecins1481}1482define <4 x float> @testSameVecEl3LE(<4 x float> %a) {1483; CHECK-64-LABEL: testSameVecEl3LE:1484; CHECK-64: # %bb.0: # %entry1485; CHECK-64-NEXT: ld 3, L..C2(2) # %const.01486; CHECK-64-NEXT: lxv 0, 0(3)1487; CHECK-64-NEXT: xxperm 34, 34, 01488; CHECK-64-NEXT: blr1489;1490; CHECK-32-LABEL: testSameVecEl3LE:1491; CHECK-32: # %bb.0: # %entry1492; CHECK-32-NEXT: lwz 3, L..C2(2) # %const.01493; CHECK-32-NEXT: lxv 0, 0(3)1494; CHECK-32-NEXT: xxperm 34, 34, 01495; CHECK-32-NEXT: blr1496entry:1497 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 6>1498 ret <4 x float> %vecins1499}1500define <4 x float> @insertVarF(<4 x float> %a, float %f, i32 %el) {1501; CHECK-64-LABEL: insertVarF:1502; CHECK-64: # %bb.0: # %entry1503; CHECK-64-NEXT: rlwinm 3, 4, 2, 28, 291504; CHECK-64-NEXT: addi 4, 1, -161505; CHECK-64-NEXT: stxv 34, -16(1)1506; CHECK-64-NEXT: stfsx 1, 4, 31507; CHECK-64-NEXT: lxv 34, -16(1)1508; CHECK-64-NEXT: blr1509;1510; CHECK-32-LABEL: insertVarF:1511; CHECK-32: # %bb.0: # %entry1512; CHECK-32-NEXT: rlwinm 3, 4, 2, 28, 291513; CHECK-32-NEXT: addi 4, 1, -161514; CHECK-32-NEXT: stxv 34, -16(1)1515; CHECK-32-NEXT: stfsx 1, 4, 31516; CHECK-32-NEXT: lxv 34, -16(1)1517; CHECK-32-NEXT: blr1518entry:1519 %vecins = insertelement <4 x float> %a, float %f, i32 %el1520 ret <4 x float> %vecins1521}1522define <4 x i32> @insertVarI(<4 x i32> %a, i32 %i, i32 %el) {1523; CHECK-64-LABEL: insertVarI:1524; CHECK-64: # %bb.0: # %entry1525; CHECK-64-NEXT: addi 5, 1, -161526; CHECK-64-NEXT: rlwinm 4, 4, 2, 28, 291527; CHECK-64-NEXT: stxv 34, -16(1)1528; CHECK-64-NEXT: stwx 3, 5, 41529; CHECK-64-NEXT: lxv 34, -16(1)1530; CHECK-64-NEXT: blr1531;1532; CHECK-32-LABEL: insertVarI:1533; CHECK-32: # %bb.0: # %entry1534; CHECK-32-NEXT: addi 5, 1, -161535; CHECK-32-NEXT: rlwinm 4, 4, 2, 28, 291536; CHECK-32-NEXT: stxv 34, -16(1)1537; CHECK-32-NEXT: stwx 3, 5, 41538; CHECK-32-NEXT: lxv 34, -16(1)1539; CHECK-32-NEXT: blr1540entry:1541 %vecins = insertelement <4 x i32> %a, i32 %i, i32 %el1542 ret <4 x i32> %vecins1543}1544define <4 x i32> @intrinsicInsertTest(<4 x i32> %a, <2 x i64> %b) {1545; CHECK-64-LABEL: intrinsicInsertTest:1546; CHECK-64: # %bb.0: # %entry1547; CHECK-64-NEXT: xxinsertw 34, 35, 31548; CHECK-64-NEXT: blr1549;1550; CHECK-32-LABEL: intrinsicInsertTest:1551; CHECK-32: # %bb.0: # %entry1552; CHECK-32-NEXT: xxinsertw 34, 35, 31553; CHECK-32-NEXT: blr1554entry:1555 %ans = tail call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> %a, <2 x i64> %b, i32 3)1556 ret <4 x i32> %ans1557}1558declare <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32>, <2 x i64>, i32)1559define <2 x i64> @intrinsicExtractTest(<2 x i64> %a) {1560; CHECK-64-LABEL: intrinsicExtractTest:1561; CHECK-64: # %bb.0: # %entry1562; CHECK-64-NEXT: xxextractuw 34, 34, 51563; CHECK-64-NEXT: blr1564;1565; CHECK-32-LABEL: intrinsicExtractTest:1566; CHECK-32: # %bb.0: # %entry1567; CHECK-32-NEXT: xxextractuw 34, 34, 51568; CHECK-32-NEXT: blr1569entry:1570 %ans = tail call <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64> %a, i32 5)1571 ret <2 x i64> %ans1572}1573declare <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64>, i32)1574