397 lines · plain
1; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \2; RUN: --code-model=small < %s | FileCheck %s --check-prefixes=SMALL64,SMALL3; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \4; RUN: --code-model=large < %s | FileCheck %s --check-prefixes=LARGE64,LARGE5; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \6; RUN: --code-model=small < %s | FileCheck %s --check-prefixes=SMALL32,SMALL7; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \8; RUN: --code-model=large < %s | FileCheck %s --check-prefixes=LARGE32,LARGE9; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \10; RUN: --code-model=small -O0 < %s | FileCheck %s --check-prefixes=WITHDUP11; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \12; RUN: --code-model=small -O1 < %s | FileCheck %s --check-prefixes=NODUP13 14@TGInit = thread_local(localdynamic) global i32 42, align 415@TGUninit = thread_local(localdynamic) global i32 0, align 416@TIInit = internal thread_local(localdynamic) global i32 42, align 417@TIUninit = internal thread_local(localdynamic) global i32 0, align 418@TWInit = weak thread_local(localdynamic) global i32 42, align 419@TWUninit = weak thread_local(localdynamic) global i32 0, align 420@x = thread_local(localdynamic) global i32 42, align 421@y = thread_local(localdynamic) global i32 42, align 422 23define i32 @loadTGInit() {24; SMALL-LABEL: loadTGInit:25; SMALL64: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2)26; SMALL32: lwz [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2)27; SMALL: bla .__tls_get_mod[PR]28; SMALL64: ld [[OffsetR:[0-9]+]], [[TGInitL:L..C[0-9]+]](2)29; SMALL32: lwz [[OffsetR:[0-9]+]], [[TGInitL:L..C[0-9]+]](2)30; SMALL: lwzx [[TGInitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]]31;32; LARGE-LABEL: loadTGInit:33; LARGE64: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2)34; LARGE: addis [[OffsetHR:[0-9]+]], [[TGInitL:L..C[0-9]+]]@u(2)35; LARGE32: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2)36; LARGE64: ld [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]])37; LARGE32: lwz [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]])38; LARGE: bla .__tls_get_mod[PR]39; LARGE64: ld [[OffsetR:[0-9]+]], [[TGInitL:L..C[0-9]+]]@l([[OffsetHR]])40; LARGE32: lwz [[OffsetR:[0-9]+]], [[TGInitL:L..C[0-9]+]]@l([[OffsetHR]])41; LARGE: lwzx [[TGInitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]]42entry:43 %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @TGInit)44 %1 = load i32, ptr %0, align 445 ret i32 %146}47 48define void @storeTGInit(i32 noundef signext %i) {49; SMALL-LABEL: storeTGInit:50; SMALL64: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2)51; SMALL32: lwz [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2)52; SMALL: bla .__tls_get_mod[PR]53; SMALL64: ld [[OffsetR:[0-9]+]], [[TGInitL:L..C[0-9]+]](2)54; SMALL32: lwz [[OffsetR:[0-9]+]], [[TGInitL:L..C[0-9]+]](2)55; SMALL: stwx [[TGInitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]]56;57; LARGE-LABEL: storeTGInit:58; LARGE64: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2)59; LARGE: addis [[OffsetHR:[0-9]+]], [[TGInitL:L..C[0-9]+]]@u(2)60; LARGE32: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2)61; LARGE64: ld [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]])62; LARGE32: lwz [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]])63; LARGE: bla .__tls_get_mod[PR]64; LARGE64: ld [[OffsetR:[0-9]+]], [[TGInitL:L..C[0-9]+]]@l([[OffsetHR]])65; LARGE32: lwz [[OffsetR:[0-9]+]], [[TGInitL:L..C[0-9]+]]@l([[OffsetHR]])66; LARGE: stwx [[TGInitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]]67entry:68 %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @TGInit)69 store i32 %i, ptr %0, align 470 ret void71}72 73define i32 @loadTGUninit() {74; SMALL-LABEL: loadTGUninit:75; SMALL64: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2)76; SMALL32: lwz [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2)77; SMALL: bla .__tls_get_mod[PR]78; SMALL64: ld [[OffsetR:[0-9]+]], [[TGUninitL:L..C[0-9]+]](2)79; SMALL32: lwz [[OffsetR:[0-9]+]], [[TGUninitL:L..C[0-9]+]](2)80; SMALL: lwzx [[TGInitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]]81;82; LARGE-LABEL: loadTGUninit:83; LARGE64: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2)84; LARGE: addis [[OffsetHR:[0-9]+]], [[TGUninitL:L..C[0-9]+]]@u(2)85; LARGE32: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2)86; LARGE64: ld [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]])87; LARGE32: lwz [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]])88; LARGE: bla .__tls_get_mod[PR]89; LARGE64: ld [[OffsetR:[0-9]+]], [[TGUninitL:L..C[0-9]+]]@l([[OffsetHR]])90; LARGE32: lwz [[OffsetR:[0-9]+]], [[TGUninitL:L..C[0-9]+]]@l([[OffsetHR]])91; LARGE: lwzx [[TGUninitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]]92entry:93 %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @TGUninit)94 %1 = load i32, ptr %0, align 495 ret i32 %196}97 98define void @storeTGUninit(i32 noundef signext %i) {99; SMALL-LABEL: storeTGUninit:100; SMALL64: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2)101; SMALL32: lwz [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2)102; SMALL: bla .__tls_get_mod[PR]103; SMALL64: ld [[OffsetR:[0-9]+]], [[TGUninitL:L..C[0-9]+]](2)104; SMALL32: lwz [[OffsetR:[0-9]+]], [[TGUninitL:L..C[0-9]+]](2)105; SMALL: stwx [[TGUninitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]]106;107; LARGE-LABEL: storeTGUninit:108; LARGE64: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2)109; LARGE: addis [[OffsetHR:[0-9]+]], [[TGUninitL:L..C[0-9]+]]@u(2)110; LARGE32: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2)111; LARGE64: ld [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]])112; LARGE32: lwz [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]])113; LARGE: bla .__tls_get_mod[PR]114; LARGE64: ld [[OffsetR:[0-9]+]], [[TGUninitL:L..C[0-9]+]]@l([[OffsetHR]])115; LARGE32: lwz [[OffsetR:[0-9]+]], [[TGUninitL:L..C[0-9]+]]@l([[OffsetHR]])116; LARGE: stwx [[TGUninitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]]117entry:118 %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @TGUninit)119 store i32 %i, ptr %0, align 4120 ret void121}122 123define i32 @loadTIInit() {124; SMALL-LABEL: loadTIInit:125; SMALL64: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2)126; SMALL32: lwz [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2)127; SMALL: bla .__tls_get_mod[PR]128; SMALL64: ld [[OffsetR:[0-9]+]], [[TIInitL:L..C[0-9]+]](2)129; SMALL32: lwz [[OffsetR:[0-9]+]], [[TIInitL:L..C[0-9]+]](2)130; SMALL: lwzx [[TIInitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]]131;132; LARGE-LABEL: loadTIInit:133; LARGE64: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2)134; LARGE: addis [[OffsetHR:[0-9]+]], [[TIInitL:L..C[0-9]+]]@u(2)135; LARGE32: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2)136; LARGE64: ld [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]])137; LARGE32: lwz [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]])138; LARGE: bla .__tls_get_mod[PR]139; LARGE64: ld [[OffsetR:[0-9]+]], [[TIInitL:L..C[0-9]+]]@l([[OffsetHR]])140; LARGE32: lwz [[OffsetR:[0-9]+]], [[TIInitL:L..C[0-9]+]]@l([[OffsetHR]])141; LARGE: lwzx [[TIInitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]]142entry:143 %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @TIInit)144 %1 = load i32, ptr %0, align 4145 ret i32 %1146}147 148define void @storeTIInit(i32 noundef signext %i) {149; SMALL-LABEL: storeTIInit:150; SMALL64: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2)151; SMALL32: lwz [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2)152; SMALL: bla .__tls_get_mod[PR]153; SMALL64: ld [[OffsetR:[0-9]+]], [[TIInitL:L..C[0-9]+]](2)154; SMALL32: lwz [[OffsetR:[0-9]+]], [[TIInitL:L..C[0-9]+]](2)155; SMALL: stwx [[TIInitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]]156;157; LARGE-LABEL: storeTIInit:158; LARGE64: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2)159; LARGE: addis [[OffsetHR:[0-9]+]], [[TIInitL:L..C[0-9]+]]@u(2)160; LARGE32: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2)161; LARGE64: ld [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]])162; LARGE32: lwz [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]])163; LARGE: bla .__tls_get_mod[PR]164; LARGE64: ld [[OffsetR:[0-9]+]], [[TIInitL:L..C[0-9]+]]@l([[OffsetHR]])165; LARGE32: lwz [[OffsetR:[0-9]+]], [[TIInitL:L..C[0-9]+]]@l([[OffsetHR]])166; LARGE: stwx [[TIInitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]]167entry:168 %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @TIInit)169 store i32 %i, ptr %0, align 4170 ret void171}172 173define i32 @loadTIUninit() {174; SMALL-LABEL: loadTIUninit:175; SMALL64: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2)176; SMALL32: lwz [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2)177; SMALL: bla .__tls_get_mod[PR]178; SMALL64: ld [[OffsetR:[0-9]+]], [[TIUninitL:L..C[0-9]+]](2)179; SMALL32: lwz [[OffsetR:[0-9]+]], [[TIUninitL:L..C[0-9]+]](2)180; SMALL: lwzx [[TIUninitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]]181;182; LARGE-LABEL: loadTIUninit:183; LARGE64: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2)184; LARGE: addis [[OffsetHR:[0-9]+]], [[TIUninitL:L..C[0-9]+]]@u(2)185; LARGE32: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2)186; LARGE64: ld [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]])187; LARGE32: lwz [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]])188; LARGE: bla .__tls_get_mod[PR]189; LARGE64: ld [[OffsetR:[0-9]+]], [[TIUninitL:L..C[0-9]+]]@l([[OffsetHR]])190; LARGE32: lwz [[OffsetR:[0-9]+]], [[TIUninitL:L..C[0-9]+]]@l([[OffsetHR]])191; LARGE: lwzx [[TIUninitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]]192entry:193 %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @TIUninit)194 %1 = load i32, ptr %0, align 4195 ret i32 %1196}197 198define void @storeTIUninit(i32 noundef signext %i) {199; SMALL-LABEL: storeTIUninit:200; SMALL64: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2)201; SMALL32: lwz [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2)202; SMALL: bla .__tls_get_mod[PR]203; SMALL64: ld [[OffsetR:[0-9]+]], [[TIUninitL:L..C[0-9]+]](2)204; SMALL32: lwz [[OffsetR:[0-9]+]], [[TIUninitL:L..C[0-9]+]](2)205; SMALL: stwx [[TIUninitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]]206;207; LARGE-LABEL: storeTIUninit:208; LARGE64: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2)209; LARGE: addis [[OffsetHR:[0-9]+]], [[TIUninitL:L..C[0-9]+]]@u(2)210; LARGE32: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2)211; LARGE64: ld [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]])212; LARGE32: lwz [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]])213; LARGE: bla .__tls_get_mod[PR]214; LARGE64: ld [[OffsetR:[0-9]+]], [[TIUninitL:L..C[0-9]+]]@l([[OffsetHR]])215; LARGE32: lwz [[OffsetR:[0-9]+]], [[TIUninitL:L..C[0-9]+]]@l([[OffsetHR]])216; LARGE: stwx [[TIUninitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]]217entry:218 %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @TIUninit)219 store i32 %i, ptr %0, align 4220 ret void221}222 223define i32 @loadTWInit() {224; SMALL-LABEL: loadTWInit:225; SMALL64: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2)226; SMALL32: lwz [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2)227; SMALL: bla .__tls_get_mod[PR]228; SMALL64: ld [[OffsetR:[0-9]+]], [[TWInitL:L..C[0-9]+]](2)229; SMALL32: lwz [[OffsetR:[0-9]+]], [[TWInitL:L..C[0-9]+]](2)230; SMALL: lwzx [[TWInitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]]231;232; LARGE-LABEL: loadTWInit:233; LARGE64: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2)234; LARGE: addis [[OffsetHR:[0-9]+]], [[TWInitL:L..C[0-9]+]]@u(2)235; LARGE32: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2)236; LARGE64: ld [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]])237; LARGE32: lwz [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]])238; LARGE: bla .__tls_get_mod[PR]239; LARGE64: ld [[OffsetR:[0-9]+]], [[TWInitL:L..C[0-9]+]]@l([[OffsetHR]])240; LARGE32: lwz [[OffsetR:[0-9]+]], [[TWInitL:L..C[0-9]+]]@l([[OffsetHR]])241; LARGE: lwzx [[TWInitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]]242entry:243 %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @TWInit)244 %1 = load i32, ptr %0, align 4245 ret i32 %1246}247 248define void @storeTWInit(i32 noundef signext %i) {249; SMALL-LABEL: storeTWInit:250; SMALL64: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2)251; SMALL32: lwz [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2)252; SMALL: bla .__tls_get_mod[PR]253; SMALL64: ld [[OffsetR:[0-9]+]], [[TWInitL:L..C[0-9]+]](2)254; SMALL32: lwz [[OffsetR:[0-9]+]], [[TWInitL:L..C[0-9]+]](2)255; SMALL: stwx [[TWInitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]]256;257; LARGE-LABEL: storeTWInit:258; LARGE64: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2)259; LARGE: addis [[OffsetHR:[0-9]+]], [[TWInitL:L..C[0-9]+]]@u(2)260; LARGE32: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2)261; LARGE64: ld [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]])262; LARGE32: lwz [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]])263; LARGE: bla .__tls_get_mod[PR]264; LARGE64: ld [[OffsetR:[0-9]+]], [[TWInitL:L..C[0-9]+]]@l([[OffsetHR]])265; LARGE32: lwz [[OffsetR:[0-9]+]], [[TWInitL:L..C[0-9]+]]@l([[OffsetHR]])266; LARGE: stwx [[TWInitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]]267entry:268 %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @TWInit)269 store i32 %i, ptr %0, align 4270 ret void271}272 273define i32 @loadTWUninit() {274; SMALL-LABEL: loadTWUninit:275; SMALL64: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2)276; SMALL32: lwz [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2)277; SMALL: bla .__tls_get_mod[PR]278; SMALL64: ld [[OffsetR:[0-9]+]], [[TWUninitL:L..C[0-9]+]](2)279; SMALL32: lwz [[OffsetR:[0-9]+]], [[TWUninitL:L..C[0-9]+]](2)280; SMALL: lwzx [[TWUninitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]]281;282; LARGE-LABEL: loadTWUninit:283; LARGE64: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2)284; LARGE: addis [[OffsetHR:[0-9]+]], [[TWUninitL:L..C[0-9]+]]@u(2)285; LARGE32: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2)286; LARGE64: ld [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]])287; LARGE32: lwz [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]])288; LARGE: bla .__tls_get_mod[PR]289; LARGE64: ld [[OffsetR:[0-9]+]], [[TWUninitL:L..C[0-9]+]]@l([[OffsetHR]])290; LARGE32: lwz [[OffsetR:[0-9]+]], [[TWUninitL:L..C[0-9]+]]@l([[OffsetHR]])291; LARGE: lwzx [[TWUninitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]]292entry:293 %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @TWUninit)294 %1 = load i32, ptr %0, align 4295 ret i32 %1296}297 298define void @storeTWUninit(i32 noundef signext %i) {299; SMALL-LABEL: storeTWUninit:300; SMALL64: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2)301; SMALL32: lwz [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2)302; SMALL: bla .__tls_get_mod[PR]303; SMALL64: ld [[OffsetR:[0-9]+]], [[TWUninitL:L..C[0-9]+]](2)304; SMALL32: lwz [[OffsetR:[0-9]+]], [[TWUninitL:L..C[0-9]+]](2)305; SMALL: stwx [[TWUninitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]]306;307; LARGE-LABEL: storeTWUninit:308; LARGE64: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2)309; LARGE: addis [[OffsetHR:[0-9]+]], [[TWUninitL:L..C[0-9]+]]@u(2)310; LARGE32: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2)311; LARGE64: ld [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]])312; LARGE32: lwz [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]])313; LARGE: bla .__tls_get_mod[PR]314; LARGE64: ld [[OffsetR:[0-9]+]], [[TWUninitL:L..C[0-9]+]]@l([[OffsetHR]])315; LARGE32: lwz [[OffsetR:[0-9]+]], [[TWUninitL:L..C[0-9]+]]@l([[OffsetHR]])316; LARGE: stwx [[TWUninitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]]317entry:318 %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @TWUninit)319 store i32 %i, ptr %0, align 4320 ret void321}322 323define i32 @DedupTlsGetMod() #0 {324; WITHDUP-LABEL: DedupTlsGetMod:325; WITHDUP: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2)326; WITHDUP-NEXT: bla .__tls_get_mod[PR]327; WITHDUP-NEXT: ld [[OffsetXR:[0-9]+]], [[X:L..C[0-9]+]](2)328; WITHDUP: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2)329; WITHDUP-NEXT: bla .__tls_get_mod[PR]330; WITHDUP: ld [[OffsetYR:[0-9]+]], [[Y:L..C[0-9]+]](2)331; WITHDUP-LABEL: L..DedupTlsGetMod0:332;333; NODUP-LABEL: DedupTlsGetMod:334; NODUP: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2)335; NODUP-NEXT: bla .__tls_get_mod[PR]336; NODUP-NEXT: ld [[OffsetXR:[0-9]+]], [[X:L..C[0-9]+]](2)337; NODUP-NEXT: ld [[OffsetYR:[0-9]+]], [[Y:L..C[0-9]+]](2)338; NODUP-NEXT: lwzx [[XValR:[0-9]+]], [[ModuleHandleR]], [[OffsetXR]]339; NODUP-NEXT: lwzx [[YValR:[0-9]+]], [[ModuleHandleR]], [[OffsetYR]]340; NODUP-LABEL: L..DedupTlsGetMod0:341entry:342 %retval = alloca i32, align 4343 store i32 0, ptr %retval, align 4344 %0 = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @x)345 %1 = load i32, ptr %0, align 4346 %2 = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @y)347 %3 = load i32, ptr %2, align 4348 %add = add nsw i32 %1, %3349 ret i32 %add350}351 352; SMALL: .extern .__tls_get_mod[PR]353; LARGE: .extern .__tls_get_mod[PR]354; SMALL-NOT: .extern _Renamed..5f24__TLSML[TC]355; LARGE-NOT: .extern _Renamed..5f24__TLSML[TC]356 357; SMALL: [[ModuleHandleL]]:358; SMALL-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml359; SMALL-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML"360; SMALL: [[TGInitL]]:361; SMALL-NEXT: .tc TGInit[TC],TGInit[TL]@ld362; SMALL: [[TGUninitL]]:363; SMALL-NEXT: .tc TGUninit[TC],TGUninit[TL]@ld364; SMALL: [[TIInitL]]:365; SMALL-NEXT: .tc TIInit[TC],TIInit[TL]@ld366; SMALL: [[TIUninitL]]:367; SMALL-NEXT: .tc TIUninit[TC],TIUninit[UL]@ld368; SMALL: [[TWInitL]]:369; SMALL-NEXT: .tc TWInit[TC],TWInit[TL]@ld370; SMALL: [[TWUninitL]]:371; SMALL-NEXT: .tc TWUninit[TC],TWUninit[TL]@ld372 373; LARGE64: [[ModuleHandleL]]:374; LARGE64-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml375; LARGE64-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML"376; LARGE64: [[TGInitL]]:377; LARGE64-NEXT: .tc TGInit[TE],TGInit[TL]@ld378;379; LARGE32: [[TGInitL]]:380; LARGE32-NEXT: .tc TGInit[TE],TGInit[TL]@ld381; LARGE32: [[ModuleHandleL]]:382; LARGE32-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml383; LARGE32-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML"384;385; LARGE: [[TGUninitL]]:386; LARGE-NEXT: .tc TGUninit[TE],TGUninit[TL]@ld387; LARGE: [[TIInitL]]:388; LARGE-NEXT: .tc TIInit[TE],TIInit[TL]@ld389; LARGE: [[TIUninitL]]:390; LARGE-NEXT: .tc TIUninit[TE],TIUninit[UL]@ld391; LARGE: [[TWInitL]]:392; LARGE-NEXT: .tc TWInit[TE],TWInit[TL]@ld393; LARGE: [[TWUninitL]]:394; LARGE-NEXT: .tc TWUninit[TE],TWUninit[TL]@ld395 396declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull)397