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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-643; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-324 5define zeroext i8 @test1(<16 x i8> %a, i32 signext %index) {6; CHECK-64-LABEL: test1:7; CHECK-64: # %bb.0: # %entry8; CHECK-64-NEXT: clrldi 3, 3, 329; CHECK-64-NEXT: vextublx 3, 3, 210; CHECK-64-NEXT: clrldi 3, 3, 5611; CHECK-64-NEXT: blr12;13; CHECK-32-LABEL: test1:14; CHECK-32: # %bb.0: # %entry15; CHECK-32-NEXT: addi 4, 1, -1616; CHECK-32-NEXT: clrlwi 3, 3, 2817; CHECK-32-NEXT: stxv 34, -16(1)18; CHECK-32-NEXT: lbzx 3, 4, 319; CHECK-32-NEXT: blr20entry:21 %vecext = extractelement <16 x i8> %a, i32 %index22 ret i8 %vecext23}24 25define signext i8 @test2(<16 x i8> %a, i32 signext %index) {26; CHECK-64-LABEL: test2:27; CHECK-64: # %bb.0: # %entry28; CHECK-64-NEXT: clrldi 3, 3, 3229; CHECK-64-NEXT: vextublx 3, 3, 230; CHECK-64-NEXT: extsb 3, 331; CHECK-64-NEXT: blr32;33; CHECK-32-LABEL: test2:34; CHECK-32: # %bb.0: # %entry35; CHECK-32-NEXT: addi 4, 1, -1636; CHECK-32-NEXT: clrlwi 3, 3, 2837; CHECK-32-NEXT: stxv 34, -16(1)38; CHECK-32-NEXT: lbzx 3, 4, 339; CHECK-32-NEXT: extsb 3, 340; CHECK-32-NEXT: blr41entry:42 %vecext = extractelement <16 x i8> %a, i32 %index43 ret i8 %vecext44}45 46define zeroext i16 @test3(<8 x i16> %a, i32 signext %index) {47; CHECK-64-LABEL: test3:48; CHECK-64: # %bb.0: # %entry49; CHECK-64-NEXT: clrldi 3, 3, 3250; CHECK-64-NEXT: rlwinm 3, 3, 1, 28, 3051; CHECK-64-NEXT: vextuhlx 3, 3, 252; CHECK-64-NEXT: clrldi 3, 3, 4853; CHECK-64-NEXT: blr54;55; CHECK-32-LABEL: test3:56; CHECK-32: # %bb.0: # %entry57; CHECK-32-NEXT: addi 4, 1, -1658; CHECK-32-NEXT: rlwinm 3, 3, 1, 28, 3059; CHECK-32-NEXT: stxv 34, -16(1)60; CHECK-32-NEXT: lhzx 3, 4, 361; CHECK-32-NEXT: blr62entry:63 %vecext = extractelement <8 x i16> %a, i32 %index64 ret i16 %vecext65}66 67define signext i16 @test4(<8 x i16> %a, i32 signext %index) {68; CHECK-64-LABEL: test4:69; CHECK-64: # %bb.0: # %entry70; CHECK-64-NEXT: clrldi 3, 3, 3271; CHECK-64-NEXT: rlwinm 3, 3, 1, 28, 3072; CHECK-64-NEXT: vextuhlx 3, 3, 273; CHECK-64-NEXT: extsh 3, 374; CHECK-64-NEXT: blr75;76; CHECK-32-LABEL: test4:77; CHECK-32: # %bb.0: # %entry78; CHECK-32-NEXT: addi 4, 1, -1679; CHECK-32-NEXT: rlwinm 3, 3, 1, 28, 3080; CHECK-32-NEXT: stxv 34, -16(1)81; CHECK-32-NEXT: lhax 3, 4, 382; CHECK-32-NEXT: blr83entry:84 %vecext = extractelement <8 x i16> %a, i32 %index85 ret i16 %vecext86}87 88define zeroext i32 @test5(<4 x i32> %a, i32 signext %index) {89; CHECK-64-LABEL: test5:90; CHECK-64: # %bb.0: # %entry91; CHECK-64-NEXT: clrldi 3, 3, 3292; CHECK-64-NEXT: rlwinm 3, 3, 2, 28, 2993; CHECK-64-NEXT: vextuwlx 3, 3, 294; CHECK-64-NEXT: blr95;96; CHECK-32-LABEL: test5:97; CHECK-32: # %bb.0: # %entry98; CHECK-32-NEXT: addi 4, 1, -1699; CHECK-32-NEXT: rlwinm 3, 3, 2, 28, 29100; CHECK-32-NEXT: stxv 34, -16(1)101; CHECK-32-NEXT: lwzx 3, 4, 3102; CHECK-32-NEXT: blr103entry:104 %vecext = extractelement <4 x i32> %a, i32 %index105 ret i32 %vecext106}107 108define signext i32 @test6(<4 x i32> %a, i32 signext %index) {109; CHECK-64-LABEL: test6:110; CHECK-64: # %bb.0: # %entry111; CHECK-64-NEXT: clrldi 3, 3, 32112; CHECK-64-NEXT: rlwinm 3, 3, 2, 28, 29113; CHECK-64-NEXT: vextuwlx 3, 3, 2114; CHECK-64-NEXT: extsw 3, 3115; CHECK-64-NEXT: blr116;117; CHECK-32-LABEL: test6:118; CHECK-32: # %bb.0: # %entry119; CHECK-32-NEXT: addi 4, 1, -16120; CHECK-32-NEXT: rlwinm 3, 3, 2, 28, 29121; CHECK-32-NEXT: stxv 34, -16(1)122; CHECK-32-NEXT: lwzx 3, 4, 3123; CHECK-32-NEXT: blr124entry:125 %vecext = extractelement <4 x i32> %a, i32 %index126 ret i32 %vecext127}128 129; Test with immediate index130define zeroext i8 @test7(<16 x i8> %a) {131; CHECK-64-LABEL: test7:132; CHECK-64: # %bb.0: # %entry133; CHECK-64-NEXT: li 3, 1134; CHECK-64-NEXT: vextublx 3, 3, 2135; CHECK-64-NEXT: clrldi 3, 3, 56136; CHECK-64-NEXT: blr137;138; CHECK-32-LABEL: test7:139; CHECK-32: # %bb.0: # %entry140; CHECK-32-NEXT: stxv 34, -16(1)141; CHECK-32-NEXT: lbz 3, -15(1)142; CHECK-32-NEXT: blr143entry:144 %vecext = extractelement <16 x i8> %a, i32 1145 ret i8 %vecext146}147 148define zeroext i16 @test8(<8 x i16> %a) {149; CHECK-64-LABEL: test8:150; CHECK-64: # %bb.0: # %entry151; CHECK-64-NEXT: li 3, 2152; CHECK-64-NEXT: vextuhlx 3, 3, 2153; CHECK-64-NEXT: clrldi 3, 3, 48154; CHECK-64-NEXT: blr155;156; CHECK-32-LABEL: test8:157; CHECK-32: # %bb.0: # %entry158; CHECK-32-NEXT: stxv 34, -16(1)159; CHECK-32-NEXT: lhz 3, -14(1)160; CHECK-32-NEXT: blr161entry:162 %vecext = extractelement <8 x i16> %a, i32 1163 ret i16 %vecext164}165 166define zeroext i32 @test9(<4 x i32> %a) {167; CHECK-64-LABEL: test9:168; CHECK-64: # %bb.0:169; CHECK-64-NEXT: li 3, 12170; CHECK-64-NEXT: vextuwlx 3, 3, 2171; CHECK-64-NEXT: blr172;173; CHECK-32-LABEL: test9:174; CHECK-32: # %bb.0:175; CHECK-32-NEXT: stxv 34, -16(1)176; CHECK-32-NEXT: lwz 3, -4(1)177; CHECK-32-NEXT: blr178 %vecext = extractelement <4 x i32> %a, i32 3179 ret i32 %vecext180}181