278 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-643; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-324 5define zeroext i8 @test_add1(<16 x i8> %a, i32 signext %index, i8 zeroext %c) {6; CHECK-64-LABEL: test_add1:7; CHECK-64: # %bb.0: # %entry8; CHECK-64-NEXT: clrldi 3, 3, 329; CHECK-64-NEXT: vextublx 3, 3, 210; CHECK-64-NEXT: add 3, 3, 411; CHECK-64-NEXT: clrldi 3, 3, 5612; CHECK-64-NEXT: blr13;14; CHECK-32-LABEL: test_add1:15; CHECK-32: # %bb.0: # %entry16; CHECK-32-NEXT: addi 5, 1, -1617; CHECK-32-NEXT: clrlwi 3, 3, 2818; CHECK-32-NEXT: stxv 34, -16(1)19; CHECK-32-NEXT: lbzx 3, 5, 320; CHECK-32-NEXT: add 3, 3, 421; CHECK-32-NEXT: clrlwi 3, 3, 2422; CHECK-32-NEXT: blr23entry:24 %vecext = extractelement <16 x i8> %a, i32 %index25 %conv = zext i8 %vecext to i3226 %conv1 = zext i8 %c to i3227 %add = add nuw nsw i32 %conv, %conv128 %conv2 = trunc i32 %add to i829 ret i8 %conv230}31 32define signext i8 @test_add2(<16 x i8> %a, i32 signext %index, i8 signext %c) {33; CHECK-64-LABEL: test_add2:34; CHECK-64: # %bb.0: # %entry35; CHECK-64-NEXT: clrldi 3, 3, 3236; CHECK-64-NEXT: vextublx 3, 3, 237; CHECK-64-NEXT: add 3, 3, 438; CHECK-64-NEXT: extsb 3, 339; CHECK-64-NEXT: blr40;41; CHECK-32-LABEL: test_add2:42; CHECK-32: # %bb.0: # %entry43; CHECK-32-NEXT: addi 5, 1, -1644; CHECK-32-NEXT: clrlwi 3, 3, 2845; CHECK-32-NEXT: stxv 34, -16(1)46; CHECK-32-NEXT: lbzx 3, 5, 347; CHECK-32-NEXT: add 3, 3, 448; CHECK-32-NEXT: extsb 3, 349; CHECK-32-NEXT: blr50entry:51 %vecext = extractelement <16 x i8> %a, i32 %index52 %conv3 = zext i8 %vecext to i3253 %conv14 = zext i8 %c to i3254 %add = add nuw nsw i32 %conv3, %conv1455 %conv2 = trunc i32 %add to i856 ret i8 %conv257}58 59define zeroext i16 @test_add3(<8 x i16> %a, i32 signext %index, i16 zeroext %c) {60; CHECK-64-LABEL: test_add3:61; CHECK-64: # %bb.0: # %entry62; CHECK-64-NEXT: clrldi 3, 3, 3263; CHECK-64-NEXT: rlwinm 3, 3, 1, 28, 3064; CHECK-64-NEXT: vextuhlx 3, 3, 265; CHECK-64-NEXT: add 3, 3, 466; CHECK-64-NEXT: clrldi 3, 3, 4867; CHECK-64-NEXT: blr68;69; CHECK-32-LABEL: test_add3:70; CHECK-32: # %bb.0: # %entry71; CHECK-32-NEXT: addi 5, 1, -1672; CHECK-32-NEXT: rlwinm 3, 3, 1, 28, 3073; CHECK-32-NEXT: stxv 34, -16(1)74; CHECK-32-NEXT: lhzx 3, 5, 375; CHECK-32-NEXT: add 3, 3, 476; CHECK-32-NEXT: clrlwi 3, 3, 1677; CHECK-32-NEXT: blr78entry:79 %vecext = extractelement <8 x i16> %a, i32 %index80 %conv = zext i16 %vecext to i3281 %conv1 = zext i16 %c to i3282 %add = add nuw nsw i32 %conv, %conv183 %conv2 = trunc i32 %add to i1684 ret i16 %conv285}86 87define signext i16 @test_add4(<8 x i16> %a, i32 signext %index, i16 signext %c) {88; CHECK-64-LABEL: test_add4:89; CHECK-64: # %bb.0: # %entry90; CHECK-64-NEXT: clrldi 3, 3, 3291; CHECK-64-NEXT: rlwinm 3, 3, 1, 28, 3092; CHECK-64-NEXT: vextuhlx 3, 3, 293; CHECK-64-NEXT: add 3, 3, 494; CHECK-64-NEXT: extsh 3, 395; CHECK-64-NEXT: blr96;97; CHECK-32-LABEL: test_add4:98; CHECK-32: # %bb.0: # %entry99; CHECK-32-NEXT: addi 5, 1, -16100; CHECK-32-NEXT: rlwinm 3, 3, 1, 28, 30101; CHECK-32-NEXT: stxv 34, -16(1)102; CHECK-32-NEXT: lhzx 3, 5, 3103; CHECK-32-NEXT: add 3, 3, 4104; CHECK-32-NEXT: extsh 3, 3105; CHECK-32-NEXT: blr106entry:107 %vecext = extractelement <8 x i16> %a, i32 %index108 %conv5 = zext i16 %vecext to i32109 %conv16 = zext i16 %c to i32110 %add = add nuw nsw i32 %conv5, %conv16111 %conv2 = trunc i32 %add to i16112 ret i16 %conv2113}114 115define zeroext i32 @test_add5(<4 x i32> %a, i32 signext %index, i32 zeroext %c) {116; CHECK-64-LABEL: test_add5:117; CHECK-64: # %bb.0: # %entry118; CHECK-64-NEXT: clrldi 3, 3, 32119; CHECK-64-NEXT: rlwinm 3, 3, 2, 28, 29120; CHECK-64-NEXT: vextuwlx 3, 3, 2121; CHECK-64-NEXT: add 3, 3, 4122; CHECK-64-NEXT: clrldi 3, 3, 32123; CHECK-64-NEXT: blr124;125; CHECK-32-LABEL: test_add5:126; CHECK-32: # %bb.0: # %entry127; CHECK-32-NEXT: addi 5, 1, -16128; CHECK-32-NEXT: rlwinm 3, 3, 2, 28, 29129; CHECK-32-NEXT: stxv 34, -16(1)130; CHECK-32-NEXT: lwzx 3, 5, 3131; CHECK-32-NEXT: add 3, 3, 4132; CHECK-32-NEXT: blr133entry:134 %vecext = extractelement <4 x i32> %a, i32 %index135 %add = add i32 %vecext, %c136 ret i32 %add137}138 139define signext i32 @test_add6(<4 x i32> %a, i32 signext %index, i32 signext %c) {140; CHECK-64-LABEL: test_add6:141; CHECK-64: # %bb.0: # %entry142; CHECK-64-NEXT: clrldi 3, 3, 32143; CHECK-64-NEXT: rlwinm 3, 3, 2, 28, 29144; CHECK-64-NEXT: vextuwlx 3, 3, 2145; CHECK-64-NEXT: add 3, 3, 4146; CHECK-64-NEXT: extsw 3, 3147; CHECK-64-NEXT: blr148;149; CHECK-32-LABEL: test_add6:150; CHECK-32: # %bb.0: # %entry151; CHECK-32-NEXT: addi 5, 1, -16152; CHECK-32-NEXT: rlwinm 3, 3, 2, 28, 29153; CHECK-32-NEXT: stxv 34, -16(1)154; CHECK-32-NEXT: lwzx 3, 5, 3155; CHECK-32-NEXT: add 3, 3, 4156; CHECK-32-NEXT: blr157entry:158 %vecext = extractelement <4 x i32> %a, i32 %index159 %add = add nsw i32 %vecext, %c160 ret i32 %add161}162 163; When extracting word element 2 on LE, it's better to use mfvsrwz rather than vextuwrx164define zeroext i32 @test7(<4 x i32> %a) {165; CHECK-64-LABEL: test7:166; CHECK-64: # %bb.0: # %entry167; CHECK-64-NEXT: li 3, 8168; CHECK-64-NEXT: vextuwlx 3, 3, 2169; CHECK-64-NEXT: blr170;171; CHECK-32-LABEL: test7:172; CHECK-32: # %bb.0: # %entry173; CHECK-32-NEXT: stxv 34, -16(1)174; CHECK-32-NEXT: lwz 3, -8(1)175; CHECK-32-NEXT: blr176entry:177 %vecext = extractelement <4 x i32> %a, i32 2178 ret i32 %vecext179}180 181define zeroext i32 @testadd_7(<4 x i32> %a, i32 zeroext %c) {182; CHECK-64-LABEL: testadd_7:183; CHECK-64: # %bb.0: # %entry184; CHECK-64-NEXT: li 4, 8185; CHECK-64-NEXT: vextuwlx 4, 4, 2186; CHECK-64-NEXT: add 3, 4, 3187; CHECK-64-NEXT: clrldi 3, 3, 32188; CHECK-64-NEXT: blr189;190; CHECK-32-LABEL: testadd_7:191; CHECK-32: # %bb.0: # %entry192; CHECK-32-NEXT: stxv 34, -16(1)193; CHECK-32-NEXT: lwz 4, -8(1)194; CHECK-32-NEXT: add 3, 4, 3195; CHECK-32-NEXT: blr196entry:197 %vecext = extractelement <4 x i32> %a, i32 2198 %add = add i32 %vecext, %c199 ret i32 %add200}201 202define signext i32 @test8(<4 x i32> %a) {203; CHECK-64-LABEL: test8:204; CHECK-64: # %bb.0: # %entry205; CHECK-64-NEXT: li 3, 8206; CHECK-64-NEXT: vextuwlx 3, 3, 2207; CHECK-64-NEXT: extsw 3, 3208; CHECK-64-NEXT: blr209;210; CHECK-32-LABEL: test8:211; CHECK-32: # %bb.0: # %entry212; CHECK-32-NEXT: stxv 34, -16(1)213; CHECK-32-NEXT: lwz 3, -8(1)214; CHECK-32-NEXT: blr215entry:216 %vecext = extractelement <4 x i32> %a, i32 2217 ret i32 %vecext218}219 220define signext i32 @testadd_8(<4 x i32> %a, i32 signext %c) {221; CHECK-64-LABEL: testadd_8:222; CHECK-64: # %bb.0: # %entry223; CHECK-64-NEXT: li 4, 8224; CHECK-64-NEXT: vextuwlx 4, 4, 2225; CHECK-64-NEXT: add 3, 4, 3226; CHECK-64-NEXT: extsw 3, 3227; CHECK-64-NEXT: blr228;229; CHECK-32-LABEL: testadd_8:230; CHECK-32: # %bb.0: # %entry231; CHECK-32-NEXT: stxv 34, -16(1)232; CHECK-32-NEXT: lwz 4, -8(1)233; CHECK-32-NEXT: add 3, 4, 3234; CHECK-32-NEXT: blr235entry:236 %vecext = extractelement <4 x i32> %a, i32 2237 %add = add nsw i32 %vecext, %c238 ret i32 %add239}240 241; When extracting word element 1 on BE, it's better to use mfvsrwz rather than vextuwlx242define signext i32 @test9(<4 x i32> %a) {243; CHECK-64-LABEL: test9:244; CHECK-64: # %bb.0: # %entry245; CHECK-64-NEXT: mfvsrwz 3, 34246; CHECK-64-NEXT: extsw 3, 3247; CHECK-64-NEXT: blr248;249; CHECK-32-LABEL: test9:250; CHECK-32: # %bb.0: # %entry251; CHECK-32-NEXT: stxv 34, -16(1)252; CHECK-32-NEXT: lwz 3, -12(1)253; CHECK-32-NEXT: blr254entry:255 %vecext = extractelement <4 x i32> %a, i32 1256 ret i32 %vecext257}258 259define signext i32 @testadd_9(<4 x i32> %a, i32 signext %c) {260; CHECK-64-LABEL: testadd_9:261; CHECK-64: # %bb.0: # %entry262; CHECK-64-NEXT: mfvsrwz 4, 34263; CHECK-64-NEXT: add 3, 4, 3264; CHECK-64-NEXT: extsw 3, 3265; CHECK-64-NEXT: blr266;267; CHECK-32-LABEL: testadd_9:268; CHECK-32: # %bb.0: # %entry269; CHECK-32-NEXT: stxv 34, -16(1)270; CHECK-32-NEXT: lwz 4, -12(1)271; CHECK-32-NEXT: add 3, 4, 3272; CHECK-32-NEXT: blr273entry:274 %vecext = extractelement <4 x i32> %a, i32 1275 %add = add nsw i32 %vecext, %c276 ret i32 %add277}278