904 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-643; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-324; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr10 < %s | FileCheck %s -check-prefix=CHECK-64-P105; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -vec-extabi -mcpu=pwr10 < %s | FileCheck %s -check-prefix=CHECK-32-P106 7; Byte indexed8 9define <16 x i8> @testByte(<16 x i8> %a, i64 %b, i64 %idx) {10; CHECK-64-LABEL: testByte:11; CHECK-64: # %bb.0: # %entry12; CHECK-64-NEXT: addi 5, 1, -1613; CHECK-64-NEXT: clrldi 4, 4, 6014; CHECK-64-NEXT: stxv 34, -16(1)15; CHECK-64-NEXT: stbx 3, 5, 416; CHECK-64-NEXT: lxv 34, -16(1)17; CHECK-64-NEXT: blr18;19; CHECK-32-LABEL: testByte:20; CHECK-32: # %bb.0: # %entry21; CHECK-32-NEXT: addi 5, 1, -1622; CHECK-32-NEXT: clrlwi 3, 6, 2823; CHECK-32-NEXT: stxv 34, -16(1)24; CHECK-32-NEXT: stbx 4, 5, 325; CHECK-32-NEXT: lxv 34, -16(1)26; CHECK-32-NEXT: blr27;28; CHECK-64-P10-LABEL: testByte:29; CHECK-64-P10: # %bb.0: # %entry30; CHECK-64-P10-NEXT: vinsblx 2, 4, 331; CHECK-64-P10-NEXT: blr32;33; CHECK-32-P10-LABEL: testByte:34; CHECK-32-P10: # %bb.0: # %entry35; CHECK-32-P10-NEXT: vinsblx 2, 6, 436; CHECK-32-P10-NEXT: blr37entry:38 %conv = trunc i64 %b to i839 %vecins = insertelement <16 x i8> %a, i8 %conv, i64 %idx40 ret <16 x i8> %vecins41}42 43; Halfword indexed44 45define <8 x i16> @testHalf(<8 x i16> %a, i64 %b, i64 %idx) {46; CHECK-64-LABEL: testHalf:47; CHECK-64: # %bb.0: # %entry48; CHECK-64-NEXT: addi 5, 1, -1649; CHECK-64-NEXT: rlwinm 4, 4, 1, 28, 3050; CHECK-64-NEXT: stxv 34, -16(1)51; CHECK-64-NEXT: sthx 3, 5, 452; CHECK-64-NEXT: lxv 34, -16(1)53; CHECK-64-NEXT: blr54;55; CHECK-32-LABEL: testHalf:56; CHECK-32: # %bb.0: # %entry57; CHECK-32-NEXT: addi 5, 1, -1658; CHECK-32-NEXT: rlwinm 3, 6, 1, 28, 3059; CHECK-32-NEXT: stxv 34, -16(1)60; CHECK-32-NEXT: sthx 4, 5, 361; CHECK-32-NEXT: lxv 34, -16(1)62; CHECK-32-NEXT: blr63;64; CHECK-64-P10-LABEL: testHalf:65; CHECK-64-P10: # %bb.0: # %entry66; CHECK-64-P10-NEXT: slwi 4, 4, 167; CHECK-64-P10-NEXT: vinshlx 2, 4, 368; CHECK-64-P10-NEXT: blr69;70; CHECK-32-P10-LABEL: testHalf:71; CHECK-32-P10: # %bb.0: # %entry72; CHECK-32-P10-NEXT: slwi 3, 6, 173; CHECK-32-P10-NEXT: vinshlx 2, 3, 474; CHECK-32-P10-NEXT: blr75entry:76 %conv = trunc i64 %b to i1677 %vecins = insertelement <8 x i16> %a, i16 %conv, i64 %idx78 ret <8 x i16> %vecins79}80 81; Word indexed82 83define <4 x i32> @testWord(<4 x i32> %a, i64 %b, i64 %idx) {84; CHECK-64-LABEL: testWord:85; CHECK-64: # %bb.0: # %entry86; CHECK-64-NEXT: addi 5, 1, -1687; CHECK-64-NEXT: rlwinm 4, 4, 2, 28, 2988; CHECK-64-NEXT: stxv 34, -16(1)89; CHECK-64-NEXT: stwx 3, 5, 490; CHECK-64-NEXT: lxv 34, -16(1)91; CHECK-64-NEXT: blr92;93; CHECK-32-LABEL: testWord:94; CHECK-32: # %bb.0: # %entry95; CHECK-32-NEXT: addi 5, 1, -1696; CHECK-32-NEXT: rlwinm 3, 6, 2, 28, 2997; CHECK-32-NEXT: stxv 34, -16(1)98; CHECK-32-NEXT: stwx 4, 5, 399; CHECK-32-NEXT: lxv 34, -16(1)100; CHECK-32-NEXT: blr101;102; CHECK-64-P10-LABEL: testWord:103; CHECK-64-P10: # %bb.0: # %entry104; CHECK-64-P10-NEXT: slwi 4, 4, 2105; CHECK-64-P10-NEXT: vinswlx 2, 4, 3106; CHECK-64-P10-NEXT: blr107;108; CHECK-32-P10-LABEL: testWord:109; CHECK-32-P10: # %bb.0: # %entry110; CHECK-32-P10-NEXT: slwi 3, 6, 2111; CHECK-32-P10-NEXT: vinswlx 2, 3, 4112; CHECK-32-P10-NEXT: blr113entry:114 %conv = trunc i64 %b to i32115 %vecins = insertelement <4 x i32> %a, i32 %conv, i64 %idx116 ret <4 x i32> %vecins117}118 119; Word immediate120 121define <4 x i32> @testWordImm(<4 x i32> %a, i64 %b) {122; CHECK-64-LABEL: testWordImm:123; CHECK-64: # %bb.0: # %entry124; CHECK-64-NEXT: mtfprwz 0, 3125; CHECK-64-NEXT: xxinsertw 34, 0, 4126; CHECK-64-NEXT: xxinsertw 34, 0, 12127; CHECK-64-NEXT: blr128;129; CHECK-32-LABEL: testWordImm:130; CHECK-32: # %bb.0: # %entry131; CHECK-32-NEXT: mtfprwz 0, 4132; CHECK-32-NEXT: xxinsertw 34, 0, 4133; CHECK-32-NEXT: xxinsertw 34, 0, 12134; CHECK-32-NEXT: blr135;136; CHECK-64-P10-LABEL: testWordImm:137; CHECK-64-P10: # %bb.0: # %entry138; CHECK-64-P10-NEXT: vinsw 2, 3, 4139; CHECK-64-P10-NEXT: vinsw 2, 3, 12140; CHECK-64-P10-NEXT: blr141;142; CHECK-32-P10-LABEL: testWordImm:143; CHECK-32-P10: # %bb.0: # %entry144; CHECK-32-P10-NEXT: vinsw 2, 4, 4145; CHECK-32-P10-NEXT: vinsw 2, 4, 12146; CHECK-32-P10-NEXT: blr147entry:148 %conv = trunc i64 %b to i32149 %vecins = insertelement <4 x i32> %a, i32 %conv, i32 1150 %vecins2 = insertelement <4 x i32> %vecins, i32 %conv, i32 3151 ret <4 x i32> %vecins2152}153 154; Doubleword indexed155 156define <2 x i64> @testDoubleword(<2 x i64> %a, i64 %b, i64 %idx) {157; CHECK-64-LABEL: testDoubleword:158; CHECK-64: # %bb.0: # %entry159; CHECK-64-NEXT: addi 5, 1, -16160; CHECK-64-NEXT: rlwinm 4, 4, 3, 28, 28161; CHECK-64-NEXT: stxv 34, -16(1)162; CHECK-64-NEXT: stdx 3, 5, 4163; CHECK-64-NEXT: lxv 34, -16(1)164; CHECK-64-NEXT: blr165;166; CHECK-32-LABEL: testDoubleword:167; CHECK-32: # %bb.0: # %entry168; CHECK-32-NEXT: add 5, 6, 6169; CHECK-32-NEXT: addi 7, 1, -32170; CHECK-32-NEXT: stxv 34, -32(1)171; CHECK-32-NEXT: rlwinm 6, 5, 2, 28, 29172; CHECK-32-NEXT: stwx 3, 7, 6173; CHECK-32-NEXT: addi 3, 5, 1174; CHECK-32-NEXT: addi 5, 1, -16175; CHECK-32-NEXT: lxv 0, -32(1)176; CHECK-32-NEXT: rlwinm 3, 3, 2, 28, 29177; CHECK-32-NEXT: stxv 0, -16(1)178; CHECK-32-NEXT: stwx 4, 5, 3179; CHECK-32-NEXT: lxv 34, -16(1)180; CHECK-32-NEXT: blr181;182; CHECK-64-P10-LABEL: testDoubleword:183; CHECK-64-P10: # %bb.0: # %entry184; CHECK-64-P10-NEXT: rlwinm 4, 4, 3, 0, 28185; CHECK-64-P10-NEXT: vinsdlx 2, 4, 3186; CHECK-64-P10-NEXT: blr187;188; CHECK-32-P10-LABEL: testDoubleword:189; CHECK-32-P10: # %bb.0: # %entry190; CHECK-32-P10-NEXT: add 5, 6, 6191; CHECK-32-P10-NEXT: slwi 6, 5, 2192; CHECK-32-P10-NEXT: vinswlx 2, 6, 3193; CHECK-32-P10-NEXT: addi 3, 5, 1194; CHECK-32-P10-NEXT: slwi 3, 3, 2195; CHECK-32-P10-NEXT: vinswlx 2, 3, 4196; CHECK-32-P10-NEXT: blr197entry:198 %vecins = insertelement <2 x i64> %a, i64 %b, i64 %idx199 ret <2 x i64> %vecins200}201 202; Doubleword immediate203 204define <2 x i64> @testDoublewordImm(<2 x i64> %a, i64 %b) {205; CHECK-64-LABEL: testDoublewordImm:206; CHECK-64: # %bb.0: # %entry207; CHECK-64-NEXT: mtfprd 0, 3208; CHECK-64-NEXT: xxmrghd 34, 34, 0209; CHECK-64-NEXT: blr210;211; CHECK-32-LABEL: testDoublewordImm:212; CHECK-32: # %bb.0: # %entry213; CHECK-32-NEXT: mtfprwz 0, 3214; CHECK-32-NEXT: xxinsertw 34, 0, 8215; CHECK-32-NEXT: mtfprwz 0, 4216; CHECK-32-NEXT: xxinsertw 34, 0, 12217; CHECK-32-NEXT: blr218;219; CHECK-64-P10-LABEL: testDoublewordImm:220; CHECK-64-P10: # %bb.0: # %entry221; CHECK-64-P10-NEXT: vinsd 2, 3, 8222; CHECK-64-P10-NEXT: blr223;224; CHECK-32-P10-LABEL: testDoublewordImm:225; CHECK-32-P10: # %bb.0: # %entry226; CHECK-32-P10-NEXT: vinsw 2, 3, 8227; CHECK-32-P10-NEXT: vinsw 2, 4, 12228; CHECK-32-P10-NEXT: blr229entry:230 %vecins = insertelement <2 x i64> %a, i64 %b, i32 1231 ret <2 x i64> %vecins232}233 234define <2 x i64> @testDoublewordImm2(<2 x i64> %a, i64 %b) {235; CHECK-64-LABEL: testDoublewordImm2:236; CHECK-64: # %bb.0: # %entry237; CHECK-64-NEXT: mtfprd 0, 3238; CHECK-64-NEXT: xxpermdi 34, 0, 34, 1239; CHECK-64-NEXT: blr240;241; CHECK-32-LABEL: testDoublewordImm2:242; CHECK-32: # %bb.0: # %entry243; CHECK-32-NEXT: mtfprwz 0, 3244; CHECK-32-NEXT: xxinsertw 34, 0, 0245; CHECK-32-NEXT: mtfprwz 0, 4246; CHECK-32-NEXT: xxinsertw 34, 0, 4247; CHECK-32-NEXT: blr248;249; CHECK-64-P10-LABEL: testDoublewordImm2:250; CHECK-64-P10: # %bb.0: # %entry251; CHECK-64-P10-NEXT: vinsd 2, 3, 0252; CHECK-64-P10-NEXT: blr253;254; CHECK-32-P10-LABEL: testDoublewordImm2:255; CHECK-32-P10: # %bb.0: # %entry256; CHECK-32-P10-NEXT: vinsw 2, 3, 0257; CHECK-32-P10-NEXT: vinsw 2, 4, 4258; CHECK-32-P10-NEXT: blr259entry:260 %vecins = insertelement <2 x i64> %a, i64 %b, i32 0261 ret <2 x i64> %vecins262}263 264; Float indexed265 266define <4 x float> @testFloat1(<4 x float> %a, float %b, i32 zeroext %idx1) {267; CHECK-64-LABEL: testFloat1:268; CHECK-64: # %bb.0: # %entry269; CHECK-64-NEXT: rlwinm 3, 4, 2, 28, 29270; CHECK-64-NEXT: addi 4, 1, -16271; CHECK-64-NEXT: stxv 34, -16(1)272; CHECK-64-NEXT: stfsx 1, 4, 3273; CHECK-64-NEXT: lxv 34, -16(1)274; CHECK-64-NEXT: blr275;276; CHECK-32-LABEL: testFloat1:277; CHECK-32: # %bb.0: # %entry278; CHECK-32-NEXT: rlwinm 3, 4, 2, 28, 29279; CHECK-32-NEXT: addi 4, 1, -16280; CHECK-32-NEXT: stxv 34, -16(1)281; CHECK-32-NEXT: stfsx 1, 4, 3282; CHECK-32-NEXT: lxv 34, -16(1)283; CHECK-32-NEXT: blr284;285; CHECK-64-P10-LABEL: testFloat1:286; CHECK-64-P10: # %bb.0: # %entry287; CHECK-64-P10-NEXT: xscvdpspn 35, 1288; CHECK-64-P10-NEXT: slwi 3, 4, 2289; CHECK-64-P10-NEXT: vinswvlx 2, 3, 3290; CHECK-64-P10-NEXT: blr291;292; CHECK-32-P10-LABEL: testFloat1:293; CHECK-32-P10: # %bb.0: # %entry294; CHECK-32-P10-NEXT: xscvdpspn 35, 1295; CHECK-32-P10-NEXT: slwi 3, 4, 2296; CHECK-32-P10-NEXT: vinswvlx 2, 3, 3297; CHECK-32-P10-NEXT: blr298entry:299 %vecins = insertelement <4 x float> %a, float %b, i32 %idx1300 ret <4 x float> %vecins301}302 303define <4 x float> @testFloat2(<4 x float> %a, ptr %b, i32 zeroext %idx1, i32 zeroext %idx2) {304; CHECK-64-LABEL: testFloat2:305; CHECK-64: # %bb.0: # %entry306; CHECK-64-NEXT: lwz 6, 0(3)307; CHECK-64-NEXT: addi 7, 1, -16308; CHECK-64-NEXT: rlwinm 4, 4, 2, 28, 29309; CHECK-64-NEXT: stxv 34, -16(1)310; CHECK-64-NEXT: rlwinm 5, 5, 2, 28, 29311; CHECK-64-NEXT: stwx 6, 7, 4312; CHECK-64-NEXT: addi 4, 1, -32313; CHECK-64-NEXT: lxv 0, -16(1)314; CHECK-64-NEXT: lwz 3, 1(3)315; CHECK-64-NEXT: stxv 0, -32(1)316; CHECK-64-NEXT: stwx 3, 4, 5317; CHECK-64-NEXT: lxv 34, -32(1)318; CHECK-64-NEXT: blr319;320; CHECK-32-LABEL: testFloat2:321; CHECK-32: # %bb.0: # %entry322; CHECK-32-NEXT: lwz 6, 0(3)323; CHECK-32-NEXT: addi 7, 1, -16324; CHECK-32-NEXT: rlwinm 4, 4, 2, 28, 29325; CHECK-32-NEXT: stxv 34, -16(1)326; CHECK-32-NEXT: rlwinm 5, 5, 2, 28, 29327; CHECK-32-NEXT: stwx 6, 7, 4328; CHECK-32-NEXT: addi 4, 1, -48329; CHECK-32-NEXT: lxv 0, -16(1)330; CHECK-32-NEXT: lwz 3, 1(3)331; CHECK-32-NEXT: stxv 0, -48(1)332; CHECK-32-NEXT: stwx 3, 4, 5333; CHECK-32-NEXT: lxv 34, -48(1)334; CHECK-32-NEXT: blr335;336; CHECK-64-P10-LABEL: testFloat2:337; CHECK-64-P10: # %bb.0: # %entry338; CHECK-64-P10-NEXT: lwz 6, 0(3)339; CHECK-64-P10-NEXT: lwz 3, 1(3)340; CHECK-64-P10-NEXT: slwi 4, 4, 2341; CHECK-64-P10-NEXT: vinswlx 2, 4, 6342; CHECK-64-P10-NEXT: slwi 4, 5, 2343; CHECK-64-P10-NEXT: vinswlx 2, 4, 3344; CHECK-64-P10-NEXT: blr345;346; CHECK-32-P10-LABEL: testFloat2:347; CHECK-32-P10: # %bb.0: # %entry348; CHECK-32-P10-NEXT: lwz 6, 0(3)349; CHECK-32-P10-NEXT: lwz 3, 1(3)350; CHECK-32-P10-NEXT: slwi 4, 4, 2351; CHECK-32-P10-NEXT: vinswlx 2, 4, 6352; CHECK-32-P10-NEXT: slwi 4, 5, 2353; CHECK-32-P10-NEXT: vinswlx 2, 4, 3354; CHECK-32-P10-NEXT: blr355entry:356 %add.ptr1 = getelementptr inbounds i8, ptr %b, i64 1357 %0 = load float, ptr %b, align 4358 %vecins = insertelement <4 x float> %a, float %0, i32 %idx1359 %1 = load float, ptr %add.ptr1, align 4360 %vecins2 = insertelement <4 x float> %vecins, float %1, i32 %idx2361 ret <4 x float> %vecins2362}363 364define <4 x float> @testFloat3(<4 x float> %a, ptr %b, i32 zeroext %idx1, i32 zeroext %idx2) {365; CHECK-64-LABEL: testFloat3:366; CHECK-64: # %bb.0: # %entry367; CHECK-64-NEXT: lis 6, 1368; CHECK-64-NEXT: addi 7, 1, -16369; CHECK-64-NEXT: rlwinm 4, 4, 2, 28, 29370; CHECK-64-NEXT: rlwinm 5, 5, 2, 28, 29371; CHECK-64-NEXT: lwzx 6, 3, 6372; CHECK-64-NEXT: stxv 34, -16(1)373; CHECK-64-NEXT: stwx 6, 7, 4374; CHECK-64-NEXT: li 4, 1375; CHECK-64-NEXT: lxv 0, -16(1)376; CHECK-64-NEXT: rldic 4, 4, 36, 27377; CHECK-64-NEXT: lwzx 3, 3, 4378; CHECK-64-NEXT: addi 4, 1, -32379; CHECK-64-NEXT: stxv 0, -32(1)380; CHECK-64-NEXT: stwx 3, 4, 5381; CHECK-64-NEXT: lxv 34, -32(1)382; CHECK-64-NEXT: blr383;384; CHECK-32-LABEL: testFloat3:385; CHECK-32: # %bb.0: # %entry386; CHECK-32-NEXT: lis 6, 1387; CHECK-32-NEXT: addi 7, 1, -16388; CHECK-32-NEXT: rlwinm 4, 4, 2, 28, 29389; CHECK-32-NEXT: rlwinm 5, 5, 2, 28, 29390; CHECK-32-NEXT: lwzx 6, 3, 6391; CHECK-32-NEXT: stxv 34, -16(1)392; CHECK-32-NEXT: stwx 6, 7, 4393; CHECK-32-NEXT: addi 4, 1, -48394; CHECK-32-NEXT: lxv 0, -16(1)395; CHECK-32-NEXT: lwz 3, 0(3)396; CHECK-32-NEXT: stxv 0, -48(1)397; CHECK-32-NEXT: stwx 3, 4, 5398; CHECK-32-NEXT: lxv 34, -48(1)399; CHECK-32-NEXT: blr400;401; CHECK-64-P10-LABEL: testFloat3:402; CHECK-64-P10: # %bb.0: # %entry403; CHECK-64-P10-NEXT: plwz 6, 65536(3), 0404; CHECK-64-P10-NEXT: slwi 4, 4, 2405; CHECK-64-P10-NEXT: vinswlx 2, 4, 6406; CHECK-64-P10-NEXT: li 4, 1407; CHECK-64-P10-NEXT: rldic 4, 4, 36, 27408; CHECK-64-P10-NEXT: lwzx 3, 3, 4409; CHECK-64-P10-NEXT: slwi 4, 5, 2410; CHECK-64-P10-NEXT: vinswlx 2, 4, 3411; CHECK-64-P10-NEXT: blr412;413; CHECK-32-P10-LABEL: testFloat3:414; CHECK-32-P10: # %bb.0: # %entry415; CHECK-32-P10-NEXT: plwz 6, 65536(3), 0416; CHECK-32-P10-NEXT: lwz 3, 0(3)417; CHECK-32-P10-NEXT: slwi 4, 4, 2418; CHECK-32-P10-NEXT: vinswlx 2, 4, 6419; CHECK-32-P10-NEXT: slwi 4, 5, 2420; CHECK-32-P10-NEXT: vinswlx 2, 4, 3421; CHECK-32-P10-NEXT: blr422entry:423 %add.ptr = getelementptr inbounds i8, ptr %b, i64 65536424 %add.ptr1 = getelementptr inbounds i8, ptr %b, i64 68719476736425 %0 = load float, ptr %add.ptr, align 4426 %vecins = insertelement <4 x float> %a, float %0, i32 %idx1427 %1 = load float, ptr %add.ptr1, align 4428 %vecins2 = insertelement <4 x float> %vecins, float %1, i32 %idx2429 ret <4 x float> %vecins2430}431 432; Float immediate433 434define <4 x float> @testFloatImm1(<4 x float> %a, float %b) {435; CHECK-64-LABEL: testFloatImm1:436; CHECK-64: # %bb.0: # %entry437; CHECK-64-NEXT: xscvdpspn 0, 1438; CHECK-64-NEXT: xxinsertw 34, 0, 0439; CHECK-64-NEXT: xxinsertw 34, 0, 8440; CHECK-64-NEXT: blr441;442; CHECK-32-LABEL: testFloatImm1:443; CHECK-32: # %bb.0: # %entry444; CHECK-32-NEXT: xscvdpspn 0, 1445; CHECK-32-NEXT: xxinsertw 34, 0, 0446; CHECK-32-NEXT: xxinsertw 34, 0, 8447; CHECK-32-NEXT: blr448;449; CHECK-64-P10-LABEL: testFloatImm1:450; CHECK-64-P10: # %bb.0: # %entry451; CHECK-64-P10-NEXT: xscvdpspn 0, 1452; CHECK-64-P10-NEXT: xxinsertw 34, 0, 0453; CHECK-64-P10-NEXT: xxinsertw 34, 0, 8454; CHECK-64-P10-NEXT: blr455;456; CHECK-32-P10-LABEL: testFloatImm1:457; CHECK-32-P10: # %bb.0: # %entry458; CHECK-32-P10-NEXT: xscvdpspn 0, 1459; CHECK-32-P10-NEXT: xxinsertw 34, 0, 0460; CHECK-32-P10-NEXT: xxinsertw 34, 0, 8461; CHECK-32-P10-NEXT: blr462entry:463 %vecins = insertelement <4 x float> %a, float %b, i32 0464 %vecins1 = insertelement <4 x float> %vecins, float %b, i32 2465 ret <4 x float> %vecins1466}467 468define <4 x float> @testFloatImm2(<4 x float> %a, ptr %b) {469; CHECK-64-LABEL: testFloatImm2:470; CHECK-64: # %bb.0: # %entry471; CHECK-64-NEXT: lwz 4, 0(3)472; CHECK-64-NEXT: lwz 3, 4(3)473; CHECK-64-NEXT: mtfprwz 0, 4474; CHECK-64-NEXT: xxinsertw 34, 0, 0475; CHECK-64-NEXT: mtfprwz 0, 3476; CHECK-64-NEXT: xxinsertw 34, 0, 8477; CHECK-64-NEXT: blr478;479; CHECK-32-LABEL: testFloatImm2:480; CHECK-32: # %bb.0: # %entry481; CHECK-32-NEXT: lwz 4, 0(3)482; CHECK-32-NEXT: lwz 3, 4(3)483; CHECK-32-NEXT: mtfprwz 0, 4484; CHECK-32-NEXT: xxinsertw 34, 0, 0485; CHECK-32-NEXT: mtfprwz 0, 3486; CHECK-32-NEXT: xxinsertw 34, 0, 8487; CHECK-32-NEXT: blr488;489; CHECK-64-P10-LABEL: testFloatImm2:490; CHECK-64-P10: # %bb.0: # %entry491; CHECK-64-P10-NEXT: lwz 4, 0(3)492; CHECK-64-P10-NEXT: lwz 3, 4(3)493; CHECK-64-P10-NEXT: vinsw 2, 4, 0494; CHECK-64-P10-NEXT: vinsw 2, 3, 8495; CHECK-64-P10-NEXT: blr496;497; CHECK-32-P10-LABEL: testFloatImm2:498; CHECK-32-P10: # %bb.0: # %entry499; CHECK-32-P10-NEXT: lwz 4, 0(3)500; CHECK-32-P10-NEXT: lwz 3, 4(3)501; CHECK-32-P10-NEXT: vinsw 2, 4, 0502; CHECK-32-P10-NEXT: vinsw 2, 3, 8503; CHECK-32-P10-NEXT: blr504entry:505 %add.ptr1 = getelementptr inbounds i32, ptr %b, i64 1506 %0 = load float, ptr %b, align 4507 %vecins = insertelement <4 x float> %a, float %0, i32 0508 %1 = load float, ptr %add.ptr1, align 4509 %vecins2 = insertelement <4 x float> %vecins, float %1, i32 2510 ret <4 x float> %vecins2511}512 513define <4 x float> @testFloatImm3(<4 x float> %a, ptr %b) {514; CHECK-64-LABEL: testFloatImm3:515; CHECK-64: # %bb.0: # %entry516; CHECK-64-NEXT: lis 4, 4517; CHECK-64-NEXT: lwzx 4, 3, 4518; CHECK-64-NEXT: mtfprwz 0, 4519; CHECK-64-NEXT: li 4, 1520; CHECK-64-NEXT: rldic 4, 4, 38, 25521; CHECK-64-NEXT: xxinsertw 34, 0, 0522; CHECK-64-NEXT: lwzx 3, 3, 4523; CHECK-64-NEXT: mtfprwz 0, 3524; CHECK-64-NEXT: xxinsertw 34, 0, 8525; CHECK-64-NEXT: blr526;527; CHECK-32-LABEL: testFloatImm3:528; CHECK-32: # %bb.0: # %entry529; CHECK-32-NEXT: lis 4, 4530; CHECK-32-NEXT: lwzx 4, 3, 4531; CHECK-32-NEXT: lwz 3, 0(3)532; CHECK-32-NEXT: mtfprwz 0, 4533; CHECK-32-NEXT: xxinsertw 34, 0, 0534; CHECK-32-NEXT: mtfprwz 0, 3535; CHECK-32-NEXT: xxinsertw 34, 0, 8536; CHECK-32-NEXT: blr537;538; CHECK-64-P10-LABEL: testFloatImm3:539; CHECK-64-P10: # %bb.0: # %entry540; CHECK-64-P10-NEXT: plwz 4, 262144(3), 0541; CHECK-64-P10-NEXT: vinsw 2, 4, 0542; CHECK-64-P10-NEXT: li 4, 1543; CHECK-64-P10-NEXT: rldic 4, 4, 38, 25544; CHECK-64-P10-NEXT: lwzx 3, 3, 4545; CHECK-64-P10-NEXT: vinsw 2, 3, 8546; CHECK-64-P10-NEXT: blr547;548; CHECK-32-P10-LABEL: testFloatImm3:549; CHECK-32-P10: # %bb.0: # %entry550; CHECK-32-P10-NEXT: plwz 4, 262144(3), 0551; CHECK-32-P10-NEXT: lwz 3, 0(3)552; CHECK-32-P10-NEXT: vinsw 2, 4, 0553; CHECK-32-P10-NEXT: vinsw 2, 3, 8554; CHECK-32-P10-NEXT: blr555entry:556 %add.ptr = getelementptr inbounds i32, ptr %b, i64 65536557 %add.ptr1 = getelementptr inbounds i32, ptr %b, i64 68719476736558 %0 = load float, ptr %add.ptr, align 4559 %vecins = insertelement <4 x float> %a, float %0, i32 0560 %1 = load float, ptr %add.ptr1, align 4561 %vecins2 = insertelement <4 x float> %vecins, float %1, i32 2562 ret <4 x float> %vecins2563}564 565; Double indexed566 567define <2 x double> @testDouble1(<2 x double> %a, double %b, i32 zeroext %idx1) {568; CHECK-64-LABEL: testDouble1:569; CHECK-64: # %bb.0: # %entry570; CHECK-64-NEXT: rlwinm 3, 4, 3, 28, 28571; CHECK-64-NEXT: addi 4, 1, -16572; CHECK-64-NEXT: stxv 34, -16(1)573; CHECK-64-NEXT: stfdx 1, 4, 3574; CHECK-64-NEXT: lxv 34, -16(1)575; CHECK-64-NEXT: blr576;577; CHECK-32-LABEL: testDouble1:578; CHECK-32: # %bb.0: # %entry579; CHECK-32-NEXT: addi 4, 1, -16580; CHECK-32-NEXT: rlwinm 3, 5, 3, 28, 28581; CHECK-32-NEXT: stxv 34, -16(1)582; CHECK-32-NEXT: stfdx 1, 4, 3583; CHECK-32-NEXT: lxv 34, -16(1)584; CHECK-32-NEXT: blr585;586; CHECK-64-P10-LABEL: testDouble1:587; CHECK-64-P10: # %bb.0: # %entry588; CHECK-64-P10-NEXT: mffprd 3, 1589; CHECK-64-P10-NEXT: rlwinm 4, 4, 3, 0, 28590; CHECK-64-P10-NEXT: vinsdlx 2, 4, 3591; CHECK-64-P10-NEXT: blr592;593; CHECK-32-P10-LABEL: testDouble1:594; CHECK-32-P10: # %bb.0: # %entry595; CHECK-32-P10-NEXT: addi 4, 1, -16596; CHECK-32-P10-NEXT: rlwinm 3, 5, 3, 28, 28597; CHECK-32-P10-NEXT: stxv 34, -16(1)598; CHECK-32-P10-NEXT: stfdx 1, 4, 3599; CHECK-32-P10-NEXT: lxv 34, -16(1)600; CHECK-32-P10-NEXT: blr601entry:602 %vecins = insertelement <2 x double> %a, double %b, i32 %idx1603 ret <2 x double> %vecins604}605 606define <2 x double> @testDouble2(<2 x double> %a, ptr %b, i32 zeroext %idx1, i32 zeroext %idx2) {607; CHECK-64-LABEL: testDouble2:608; CHECK-64: # %bb.0: # %entry609; CHECK-64-NEXT: ld 6, 0(3)610; CHECK-64-NEXT: addi 7, 1, -32611; CHECK-64-NEXT: rlwinm 4, 4, 3, 28, 28612; CHECK-64-NEXT: stxv 34, -32(1)613; CHECK-64-NEXT: rlwinm 5, 5, 3, 28, 28614; CHECK-64-NEXT: stdx 6, 7, 4615; CHECK-64-NEXT: li 4, 1616; CHECK-64-NEXT: lxv 0, -32(1)617; CHECK-64-NEXT: ldx 3, 3, 4618; CHECK-64-NEXT: addi 4, 1, -16619; CHECK-64-NEXT: stxv 0, -16(1)620; CHECK-64-NEXT: stdx 3, 4, 5621; CHECK-64-NEXT: lxv 34, -16(1)622; CHECK-64-NEXT: blr623;624; CHECK-32-LABEL: testDouble2:625; CHECK-32: # %bb.0: # %entry626; CHECK-32-NEXT: lfd 0, 0(3)627; CHECK-32-NEXT: addi 6, 1, -32628; CHECK-32-NEXT: rlwinm 4, 4, 3, 28, 28629; CHECK-32-NEXT: stxv 34, -32(1)630; CHECK-32-NEXT: rlwinm 5, 5, 3, 28, 28631; CHECK-32-NEXT: stfdx 0, 6, 4632; CHECK-32-NEXT: lxv 0, -32(1)633; CHECK-32-NEXT: lfd 1, 1(3)634; CHECK-32-NEXT: addi 3, 1, -16635; CHECK-32-NEXT: stxv 0, -16(1)636; CHECK-32-NEXT: stfdx 1, 3, 5637; CHECK-32-NEXT: lxv 34, -16(1)638; CHECK-32-NEXT: blr639;640; CHECK-64-P10-LABEL: testDouble2:641; CHECK-64-P10: # %bb.0: # %entry642; CHECK-64-P10-NEXT: ld 6, 0(3)643; CHECK-64-P10-NEXT: pld 3, 1(3), 0644; CHECK-64-P10-NEXT: rlwinm 4, 4, 3, 0, 28645; CHECK-64-P10-NEXT: vinsdlx 2, 4, 6646; CHECK-64-P10-NEXT: rlwinm 4, 5, 3, 0, 28647; CHECK-64-P10-NEXT: vinsdlx 2, 4, 3648; CHECK-64-P10-NEXT: blr649;650; CHECK-32-P10-LABEL: testDouble2:651; CHECK-32-P10: # %bb.0: # %entry652; CHECK-32-P10-NEXT: lfd 0, 0(3)653; CHECK-32-P10-NEXT: addi 6, 1, -32654; CHECK-32-P10-NEXT: rlwinm 4, 4, 3, 28, 28655; CHECK-32-P10-NEXT: stxv 34, -32(1)656; CHECK-32-P10-NEXT: rlwinm 5, 5, 3, 28, 28657; CHECK-32-P10-NEXT: stfdx 0, 6, 4658; CHECK-32-P10-NEXT: lxv 0, -32(1)659; CHECK-32-P10-NEXT: plfd 1, 1(3), 0660; CHECK-32-P10-NEXT: addi 3, 1, -16661; CHECK-32-P10-NEXT: stxv 0, -16(1)662; CHECK-32-P10-NEXT: stfdx 1, 3, 5663; CHECK-32-P10-NEXT: lxv 34, -16(1)664; CHECK-32-P10-NEXT: blr665entry:666 %add.ptr1 = getelementptr inbounds i8, ptr %b, i64 1667 %0 = load double, ptr %b, align 8668 %vecins = insertelement <2 x double> %a, double %0, i32 %idx1669 %1 = load double, ptr %add.ptr1, align 8670 %vecins2 = insertelement <2 x double> %vecins, double %1, i32 %idx2671 ret <2 x double> %vecins2672}673 674define <2 x double> @testDouble3(<2 x double> %a, ptr %b, i32 zeroext %idx1, i32 zeroext %idx2) {675; CHECK-64-LABEL: testDouble3:676; CHECK-64: # %bb.0: # %entry677; CHECK-64-NEXT: lis 6, 1678; CHECK-64-NEXT: addi 7, 1, -32679; CHECK-64-NEXT: rlwinm 4, 4, 3, 28, 28680; CHECK-64-NEXT: rlwinm 5, 5, 3, 28, 28681; CHECK-64-NEXT: ldx 6, 3, 6682; CHECK-64-NEXT: stxv 34, -32(1)683; CHECK-64-NEXT: stdx 6, 7, 4684; CHECK-64-NEXT: li 4, 1685; CHECK-64-NEXT: lxv 0, -32(1)686; CHECK-64-NEXT: rldic 4, 4, 36, 27687; CHECK-64-NEXT: ldx 3, 3, 4688; CHECK-64-NEXT: addi 4, 1, -16689; CHECK-64-NEXT: stxv 0, -16(1)690; CHECK-64-NEXT: stdx 3, 4, 5691; CHECK-64-NEXT: lxv 34, -16(1)692; CHECK-64-NEXT: blr693;694; CHECK-32-LABEL: testDouble3:695; CHECK-32: # %bb.0: # %entry696; CHECK-32-NEXT: lis 6, 1697; CHECK-32-NEXT: rlwinm 4, 4, 3, 28, 28698; CHECK-32-NEXT: rlwinm 5, 5, 3, 28, 28699; CHECK-32-NEXT: lfdx 0, 3, 6700; CHECK-32-NEXT: addi 6, 1, -32701; CHECK-32-NEXT: stxv 34, -32(1)702; CHECK-32-NEXT: stfdx 0, 6, 4703; CHECK-32-NEXT: lxv 0, -32(1)704; CHECK-32-NEXT: lfd 1, 0(3)705; CHECK-32-NEXT: addi 3, 1, -16706; CHECK-32-NEXT: stxv 0, -16(1)707; CHECK-32-NEXT: stfdx 1, 3, 5708; CHECK-32-NEXT: lxv 34, -16(1)709; CHECK-32-NEXT: blr710;711; CHECK-64-P10-LABEL: testDouble3:712; CHECK-64-P10: # %bb.0: # %entry713; CHECK-64-P10-NEXT: pld 6, 65536(3), 0714; CHECK-64-P10-NEXT: rlwinm 4, 4, 3, 0, 28715; CHECK-64-P10-NEXT: vinsdlx 2, 4, 6716; CHECK-64-P10-NEXT: li 4, 1717; CHECK-64-P10-NEXT: rldic 4, 4, 36, 27718; CHECK-64-P10-NEXT: ldx 3, 3, 4719; CHECK-64-P10-NEXT: rlwinm 4, 5, 3, 0, 28720; CHECK-64-P10-NEXT: vinsdlx 2, 4, 3721; CHECK-64-P10-NEXT: blr722;723; CHECK-32-P10-LABEL: testDouble3:724; CHECK-32-P10: # %bb.0: # %entry725; CHECK-32-P10-NEXT: plfd 0, 65536(3), 0726; CHECK-32-P10-NEXT: addi 6, 1, -32727; CHECK-32-P10-NEXT: rlwinm 4, 4, 3, 28, 28728; CHECK-32-P10-NEXT: stxv 34, -32(1)729; CHECK-32-P10-NEXT: rlwinm 5, 5, 3, 28, 28730; CHECK-32-P10-NEXT: stfdx 0, 6, 4731; CHECK-32-P10-NEXT: lxv 0, -32(1)732; CHECK-32-P10-NEXT: lfd 1, 0(3)733; CHECK-32-P10-NEXT: addi 3, 1, -16734; CHECK-32-P10-NEXT: stxv 0, -16(1)735; CHECK-32-P10-NEXT: stfdx 1, 3, 5736; CHECK-32-P10-NEXT: lxv 34, -16(1)737; CHECK-32-P10-NEXT: blr738entry:739 %add.ptr = getelementptr inbounds i8, ptr %b, i64 65536740 %add.ptr1 = getelementptr inbounds i8, ptr %b, i64 68719476736741 %0 = load double, ptr %add.ptr, align 8742 %vecins = insertelement <2 x double> %a, double %0, i32 %idx1743 %1 = load double, ptr %add.ptr1, align 8744 %vecins2 = insertelement <2 x double> %vecins, double %1, i32 %idx2745 ret <2 x double> %vecins2746}747 748; Double immediate749 750define <2 x double> @testDoubleImm1(<2 x double> %a, double %b) {751; CHECK-64-LABEL: testDoubleImm1:752; CHECK-64: # %bb.0: # %entry753; CHECK-64-NEXT: xxpermdi 34, 1, 34, 1754; CHECK-64-NEXT: blr755;756; CHECK-32-LABEL: testDoubleImm1:757; CHECK-32: # %bb.0: # %entry758; CHECK-32-NEXT: xxpermdi 34, 1, 34, 1759; CHECK-32-NEXT: blr760;761; CHECK-64-P10-LABEL: testDoubleImm1:762; CHECK-64-P10: # %bb.0: # %entry763; CHECK-64-P10-NEXT: xxpermdi 34, 1, 34, 1764; CHECK-64-P10-NEXT: blr765;766; CHECK-32-P10-LABEL: testDoubleImm1:767; CHECK-32-P10: # %bb.0: # %entry768; CHECK-32-P10-NEXT: xxpermdi 34, 1, 34, 1769; CHECK-32-P10-NEXT: blr770entry:771 %vecins = insertelement <2 x double> %a, double %b, i32 0772 ret <2 x double> %vecins773}774 775define <2 x double> @testDoubleImm2(<2 x double> %a, ptr %b) {776; CHECK-64-LABEL: testDoubleImm2:777; CHECK-64: # %bb.0: # %entry778; CHECK-64-NEXT: lfd 0, 0(3)779; CHECK-64-NEXT: xxpermdi 34, 0, 34, 1780; CHECK-64-NEXT: blr781;782; CHECK-32-LABEL: testDoubleImm2:783; CHECK-32: # %bb.0: # %entry784; CHECK-32-NEXT: lfd 0, 0(3)785; CHECK-32-NEXT: xxpermdi 34, 0, 34, 1786; CHECK-32-NEXT: blr787;788; CHECK-64-P10-LABEL: testDoubleImm2:789; CHECK-64-P10: # %bb.0: # %entry790; CHECK-64-P10-NEXT: lfd 0, 0(3)791; CHECK-64-P10-NEXT: xxpermdi 34, 0, 34, 1792; CHECK-64-P10-NEXT: blr793;794; CHECK-32-P10-LABEL: testDoubleImm2:795; CHECK-32-P10: # %bb.0: # %entry796; CHECK-32-P10-NEXT: lfd 0, 0(3)797; CHECK-32-P10-NEXT: xxpermdi 34, 0, 34, 1798; CHECK-32-P10-NEXT: blr799entry:800 %0 = load double, ptr %b, align 8801 %vecins = insertelement <2 x double> %a, double %0, i32 0802 ret <2 x double> %vecins803}804 805define <2 x double> @testDoubleImm3(<2 x double> %a, ptr %b) {806; CHECK-64-LABEL: testDoubleImm3:807; CHECK-64: # %bb.0: # %entry808; CHECK-64-NEXT: lfd 0, 4(3)809; CHECK-64-NEXT: xxpermdi 34, 0, 34, 1810; CHECK-64-NEXT: blr811;812; CHECK-32-LABEL: testDoubleImm3:813; CHECK-32: # %bb.0: # %entry814; CHECK-32-NEXT: lfd 0, 4(3)815; CHECK-32-NEXT: xxpermdi 34, 0, 34, 1816; CHECK-32-NEXT: blr817;818; CHECK-64-P10-LABEL: testDoubleImm3:819; CHECK-64-P10: # %bb.0: # %entry820; CHECK-64-P10-NEXT: lfd 0, 4(3)821; CHECK-64-P10-NEXT: xxpermdi 34, 0, 34, 1822; CHECK-64-P10-NEXT: blr823;824; CHECK-32-P10-LABEL: testDoubleImm3:825; CHECK-32-P10: # %bb.0: # %entry826; CHECK-32-P10-NEXT: lfd 0, 4(3)827; CHECK-32-P10-NEXT: xxpermdi 34, 0, 34, 1828; CHECK-32-P10-NEXT: blr829entry:830 %add.ptr = getelementptr inbounds i32, ptr %b, i64 1831 %0 = load double, ptr %add.ptr, align 8832 %vecins = insertelement <2 x double> %a, double %0, i32 0833 ret <2 x double> %vecins834}835 836define <2 x double> @testDoubleImm4(<2 x double> %a, ptr %b) {837; CHECK-64-LABEL: testDoubleImm4:838; CHECK-64: # %bb.0: # %entry839; CHECK-64-NEXT: lis 4, 4840; CHECK-64-NEXT: lfdx 0, 3, 4841; CHECK-64-NEXT: xxpermdi 34, 0, 34, 1842; CHECK-64-NEXT: blr843;844; CHECK-32-LABEL: testDoubleImm4:845; CHECK-32: # %bb.0: # %entry846; CHECK-32-NEXT: lis 4, 4847; CHECK-32-NEXT: lfdx 0, 3, 4848; CHECK-32-NEXT: xxpermdi 34, 0, 34, 1849; CHECK-32-NEXT: blr850;851; CHECK-64-P10-LABEL: testDoubleImm4:852; CHECK-64-P10: # %bb.0: # %entry853; CHECK-64-P10-NEXT: plfd 0, 262144(3), 0854; CHECK-64-P10-NEXT: xxpermdi 34, 0, 34, 1855; CHECK-64-P10-NEXT: blr856;857; CHECK-32-P10-LABEL: testDoubleImm4:858; CHECK-32-P10: # %bb.0: # %entry859; CHECK-32-P10-NEXT: plfd 0, 262144(3), 0860; CHECK-32-P10-NEXT: xxpermdi 34, 0, 34, 1861; CHECK-32-P10-NEXT: blr862entry:863 %add.ptr = getelementptr inbounds i32, ptr %b, i64 65536864 %0 = load double, ptr %add.ptr, align 8865 %vecins = insertelement <2 x double> %a, double %0, i32 0866 ret <2 x double> %vecins867}868 869define <2 x double> @testDoubleImm5(<2 x double> %a, ptr %b) {870; CHECK-64-LABEL: testDoubleImm5:871; CHECK-64: # %bb.0: # %entry872; CHECK-64-NEXT: li 4, 1873; CHECK-64-NEXT: rldic 4, 4, 38, 25874; CHECK-64-NEXT: lfdx 0, 3, 4875; CHECK-64-NEXT: xxpermdi 34, 0, 34, 1876; CHECK-64-NEXT: blr877;878; CHECK-32-LABEL: testDoubleImm5:879; CHECK-32: # %bb.0: # %entry880; CHECK-32-NEXT: lfd 0, 0(3)881; CHECK-32-NEXT: xxpermdi 34, 0, 34, 1882; CHECK-32-NEXT: blr883;884; CHECK-64-P10-LABEL: testDoubleImm5:885; CHECK-64-P10: # %bb.0: # %entry886; CHECK-64-P10-NEXT: li 4, 1887; CHECK-64-P10-NEXT: rldic 4, 4, 38, 25888; CHECK-64-P10-NEXT: lfdx 0, 3, 4889; CHECK-64-P10-NEXT: xxpermdi 34, 0, 34, 1890; CHECK-64-P10-NEXT: blr891;892; CHECK-32-P10-LABEL: testDoubleImm5:893; CHECK-32-P10: # %bb.0: # %entry894; CHECK-32-P10-NEXT: lfd 0, 0(3)895; CHECK-32-P10-NEXT: xxpermdi 34, 0, 34, 1896; CHECK-32-P10-NEXT: blr897entry:898 %add.ptr = getelementptr inbounds i32, ptr %b, i64 68719476736899 %0 = load double, ptr %add.ptr, align 8900 %vecins = insertelement <2 x double> %a, double %0, i32 0901 ret <2 x double> %vecins902}903 904