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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; Test the generation of asm for the function:3; int foo(_Atomic int *cp, int *old, int c) {4; return atomic_compare_exchange_weak_explicit(cp, old, c, __ATOMIC_RELAXED, __ATOMIC_RELAXED);5; }6 7; RUN: llc < %s -ppc-asm-full-reg-names -mtriple=powerpc-ibm-aix -mcpu=pwr8 -verify-machineinstrs \8; RUN: | FileCheck %s --check-prefix=CHECK9; RUN: llc < %s -ppc-asm-full-reg-names -mtriple=powerpc64-ibm-aix -mcpu=pwr8 -verify-machineinstrs \10; RUN: | FileCheck %s --check-prefix=CHECK6411 12define i32 @foo(ptr noundef %cp, ptr noundef %old, i32 noundef %c) {13; CHECK-LABEL: foo:14; CHECK: # %bb.0: # %entry15; CHECK-NEXT: stw r3, -4(r1)16; CHECK-NEXT: stw r4, -8(r1)17; CHECK-NEXT: lwz r7, 0(r4)18; CHECK-NEXT: stw r5, -12(r1)19; CHECK-NEXT: stw r5, -16(r1)20; CHECK-NEXT: lwarx r6, 0, r321; CHECK-NEXT: cmplw r6, r722; CHECK-NEXT: bne- cr0, L..BB0_523; CHECK-NEXT: # %bb.1: # %cmpxchg.fencedstore24; CHECK-NEXT: creqv 4*cr5+lt, 4*cr5+lt, 4*cr5+lt25; CHECK-NEXT: stwcx. r5, 0, r326; CHECK-NEXT: bne- cr0, L..BB0_527; CHECK-NEXT: # %bb.2: # %cmpxchg.end28; CHECK-NEXT: bc 12, 4*cr5+lt, L..BB0_429; CHECK-NEXT: L..BB0_3: # %cmpxchg.store_expected30; CHECK-NEXT: stw r6, 0(r4)31; CHECK-NEXT: L..BB0_4: # %cmpxchg.continue32; CHECK-NEXT: li r3, 033; CHECK-NEXT: li r4, 134; CHECK-NEXT: isel r3, r4, r3, 4*cr5+lt35; CHECK-NEXT: stb r3, -17(r1)36; CHECK-NEXT: blr37; CHECK-NEXT: L..BB0_5: # %cmpxchg.failure38; CHECK-NEXT: crxor 4*cr5+lt, 4*cr5+lt, 4*cr5+lt39; CHECK-NEXT: b L..BB0_340;41; CHECK64-LABEL: foo:42; CHECK64: # %bb.0: # %entry43; CHECK64-NEXT: std r3, -8(r1)44; CHECK64-NEXT: std r4, -16(r1)45; CHECK64-NEXT: lwz r7, 0(r4)46; CHECK64-NEXT: stw r5, -20(r1)47; CHECK64-NEXT: stw r5, -24(r1)48; CHECK64-NEXT: lwarx r6, 0, r349; CHECK64-NEXT: cmplw r6, r750; CHECK64-NEXT: bne- cr0, L..BB0_551; CHECK64-NEXT: # %bb.1: # %cmpxchg.fencedstore52; CHECK64-NEXT: creqv 4*cr5+lt, 4*cr5+lt, 4*cr5+lt53; CHECK64-NEXT: stwcx. r5, 0, r354; CHECK64-NEXT: bne- cr0, L..BB0_555; CHECK64-NEXT: # %bb.2: # %cmpxchg.end56; CHECK64-NEXT: bc 12, 4*cr5+lt, L..BB0_457; CHECK64-NEXT: L..BB0_3: # %cmpxchg.store_expected58; CHECK64-NEXT: stw r6, 0(r4)59; CHECK64-NEXT: L..BB0_4: # %cmpxchg.continue60; CHECK64-NEXT: li r3, 061; CHECK64-NEXT: li r4, 162; CHECK64-NEXT: isel r3, r4, r3, 4*cr5+lt63; CHECK64-NEXT: li r4, 164; CHECK64-NEXT: stb r3, -25(r1)65; CHECK64-NEXT: li r3, 066; CHECK64-NEXT: isel r3, r4, r3, 4*cr5+lt67; CHECK64-NEXT: blr68; CHECK64-NEXT: L..BB0_5: # %cmpxchg.failure69; CHECK64-NEXT: crxor 4*cr5+lt, 4*cr5+lt, 4*cr5+lt70; CHECK64-NEXT: b L..BB0_371entry:72 %cp.addr = alloca ptr, align 473 %old.addr = alloca ptr, align 474 %c.addr = alloca i32, align 475 %.atomictmp = alloca i32, align 476 %cmpxchg.bool = alloca i8, align 177 store ptr %cp, ptr %cp.addr, align 478 store ptr %old, ptr %old.addr, align 479 store i32 %c, ptr %c.addr, align 480 %0 = load ptr, ptr %cp.addr, align 481 %1 = load ptr, ptr %old.addr, align 482 %2 = load i32, ptr %c.addr, align 483 store i32 %2, ptr %.atomictmp, align 484 %3 = load i32, ptr %1, align 485 %4 = load i32, ptr %.atomictmp, align 486 %5 = cmpxchg weak ptr %0, i32 %3, i32 %4 monotonic monotonic, align 487 %6 = extractvalue { i32, i1 } %5, 088 %7 = extractvalue { i32, i1 } %5, 189 br i1 %7, label %cmpxchg.continue, label %cmpxchg.store_expected90 91cmpxchg.store_expected: ; preds = %entry92 store i32 %6, ptr %1, align 493 br label %cmpxchg.continue94 95cmpxchg.continue: ; preds = %cmpxchg.store_expected, %entry96 %storedv = zext i1 %7 to i897 store i8 %storedv, ptr %cmpxchg.bool, align 198 %8 = load i8, ptr %cmpxchg.bool, align 199 %loadedv = trunc i8 %8 to i1100 %conv = zext i1 %loadedv to i32101 ret i32 %conv102}103