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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -verify-machineinstrs -ppc-asm-full-reg-names | FileCheck %s --check-prefix=CHECK --check-prefix=PPC323; FIXME: -verify-machineinstrs currently fail on ppc64 (mismatched register/instruction).4; This is already checked for in Atomics-64.ll5; RUN: llc < %s -mcpu=ppc -mtriple=powerpc64-unknown-linux-gnu -ppc-asm-full-reg-names | FileCheck %s --check-prefix=CHECK --check-prefix=PPC646 7; In this file, we check that atomic load/store can make use of the indexed8; versions of the instructions.9 10; Indexed version of loads11define i8 @load_x_i8_seq_cst(ptr %mem) {12; PPC32-LABEL: load_x_i8_seq_cst:13; PPC32: # %bb.0:14; PPC32-NEXT: lis r4, 115; PPC32-NEXT: sync16; PPC32-NEXT: ori r4, r4, 2446417; PPC32-NEXT: lbzx r3, r3, r418; PPC32-NEXT: cmpw cr7, r3, r319; PPC32-NEXT: bne- cr7, .+420; PPC32-NEXT: isync21; PPC32-NEXT: blr22;23; PPC64-LABEL: load_x_i8_seq_cst:24; PPC64: # %bb.0:25; PPC64-NEXT: lis r4, 126; PPC64-NEXT: sync27; PPC64-NEXT: ori r4, r4, 2446428; PPC64-NEXT: lbzx r3, r3, r429; PPC64-NEXT: cmpd cr7, r3, r330; PPC64-NEXT: bne- cr7, .+431; PPC64-NEXT: isync32; PPC64-NEXT: blr33 %ptr = getelementptr inbounds [100000 x i8], ptr %mem, i64 0, i64 9000034 %val = load atomic i8, ptr %ptr seq_cst, align 135 ret i8 %val36}37define i16 @load_x_i16_acquire(ptr %mem) {38; PPC32-LABEL: load_x_i16_acquire:39; PPC32: # %bb.0:40; PPC32-NEXT: lis r4, 241; PPC32-NEXT: ori r4, r4, 4892842; PPC32-NEXT: lhzx r3, r3, r443; PPC32-NEXT: cmpw cr7, r3, r344; PPC32-NEXT: bne- cr7, .+445; PPC32-NEXT: isync46; PPC32-NEXT: blr47;48; PPC64-LABEL: load_x_i16_acquire:49; PPC64: # %bb.0:50; PPC64-NEXT: lis r4, 251; PPC64-NEXT: ori r4, r4, 4892852; PPC64-NEXT: lhzx r3, r3, r453; PPC64-NEXT: cmpd cr7, r3, r354; PPC64-NEXT: bne- cr7, .+455; PPC64-NEXT: isync56; PPC64-NEXT: blr57 %ptr = getelementptr inbounds [100000 x i16], ptr %mem, i64 0, i64 9000058 %val = load atomic i16, ptr %ptr acquire, align 259 ret i16 %val60}61define i32 @load_x_i32_monotonic(ptr %mem) {62; CHECK-LABEL: load_x_i32_monotonic:63; CHECK: # %bb.0:64; CHECK-NEXT: lis r4, 565; CHECK-NEXT: ori r4, r4, 3232066; CHECK-NEXT: lwzx r3, r3, r467; CHECK-NEXT: blr68 %ptr = getelementptr inbounds [100000 x i32], ptr %mem, i64 0, i64 9000069 %val = load atomic i32, ptr %ptr monotonic, align 470 ret i32 %val71}72define i64 @load_x_i64_unordered(ptr %mem) {73; PPC32-LABEL: load_x_i64_unordered:74; PPC32: # %bb.0:75; PPC32-NEXT: mflr r076; PPC32-NEXT: stwu r1, -16(r1)77; PPC32-NEXT: stw r0, 20(r1)78; PPC32-NEXT: .cfi_def_cfa_offset 1679; PPC32-NEXT: .cfi_offset lr, 480; PPC32-NEXT: addi r3, r3, -89681; PPC32-NEXT: addis r3, r3, 1182; PPC32-NEXT: li r4, 083; PPC32-NEXT: bl __atomic_load_884; PPC32-NEXT: lwz r0, 20(r1)85; PPC32-NEXT: addi r1, r1, 1686; PPC32-NEXT: mtlr r087; PPC32-NEXT: blr88;89; PPC64-LABEL: load_x_i64_unordered:90; PPC64: # %bb.0:91; PPC64-NEXT: lis r4, 1092; PPC64-NEXT: ori r4, r4, 6464093; PPC64-NEXT: ldx r3, r3, r494; PPC64-NEXT: blr95 %ptr = getelementptr inbounds [100000 x i64], ptr %mem, i64 0, i64 9000096 %val = load atomic i64, ptr %ptr unordered, align 897 ret i64 %val98}99 100; Indexed version of stores101define void @store_x_i8_seq_cst(ptr %mem) {102; CHECK-LABEL: store_x_i8_seq_cst:103; CHECK: # %bb.0:104; CHECK-NEXT: lis r4, 1105; CHECK-NEXT: ori r4, r4, 24464106; CHECK-NEXT: li r5, 42107; CHECK-NEXT: sync108; CHECK-NEXT: stbx r5, r3, r4109; CHECK-NEXT: blr110 %ptr = getelementptr inbounds [100000 x i8], ptr %mem, i64 0, i64 90000111 store atomic i8 42, ptr %ptr seq_cst, align 1112 ret void113}114define void @store_x_i16_release(ptr %mem) {115; CHECK-LABEL: store_x_i16_release:116; CHECK: # %bb.0:117; CHECK-NEXT: lis r4, 2118; CHECK-NEXT: ori r4, r4, 48928119; CHECK-NEXT: li r5, 42120; CHECK-NEXT: lwsync121; CHECK-NEXT: sthx r5, r3, r4122; CHECK-NEXT: blr123 %ptr = getelementptr inbounds [100000 x i16], ptr %mem, i64 0, i64 90000124 store atomic i16 42, ptr %ptr release, align 2125 ret void126}127define void @store_x_i32_monotonic(ptr %mem) {128; CHECK-LABEL: store_x_i32_monotonic:129; CHECK: # %bb.0:130; CHECK-NEXT: lis r4, 5131; CHECK-NEXT: ori r4, r4, 32320132; CHECK-NEXT: li r5, 42133; CHECK-NEXT: stwx r5, r3, r4134; CHECK-NEXT: blr135 %ptr = getelementptr inbounds [100000 x i32], ptr %mem, i64 0, i64 90000136 store atomic i32 42, ptr %ptr monotonic, align 4137 ret void138}139define void @store_x_i64_unordered(ptr %mem) {140; PPC32-LABEL: store_x_i64_unordered:141; PPC32: # %bb.0:142; PPC32-NEXT: mflr r0143; PPC32-NEXT: stwu r1, -16(r1)144; PPC32-NEXT: stw r0, 20(r1)145; PPC32-NEXT: .cfi_def_cfa_offset 16146; PPC32-NEXT: .cfi_offset lr, 4147; PPC32-NEXT: addi r3, r3, -896148; PPC32-NEXT: addis r3, r3, 11149; PPC32-NEXT: li r5, 0150; PPC32-NEXT: li r6, 42151; PPC32-NEXT: li r7, 0152; PPC32-NEXT: bl __atomic_store_8153; PPC32-NEXT: lwz r0, 20(r1)154; PPC32-NEXT: addi r1, r1, 16155; PPC32-NEXT: mtlr r0156; PPC32-NEXT: blr157;158; PPC64-LABEL: store_x_i64_unordered:159; PPC64: # %bb.0:160; PPC64-NEXT: lis r4, 10161; PPC64-NEXT: ori r4, r4, 64640162; PPC64-NEXT: li r5, 42163; PPC64-NEXT: stdx r5, r3, r4164; PPC64-NEXT: blr165 %ptr = getelementptr inbounds [100000 x i64], ptr %mem, i64 0, i64 90000166 store atomic i64 42, ptr %ptr unordered, align 8167 ret void168}169