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1; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s2target datalayout = "E-m:e-i64:64-n32:64"3target triple = "powerpc64-unknown-linux-gnu"4 5; Function Attrs: nounwind readnone6define zeroext i32 @bs4(i32 zeroext %a) #0 {7entry:8 %0 = tail call i32 @llvm.bswap.i32(i32 %a)9 ret i32 %010 11; CHECK-LABEL: @bs412; CHECK: rotlwi [[REG1:[0-9]+]], 3, 813; CHECK: rlwimi [[REG1]], 3, 24, 16, 2314; CHECK: rlwimi [[REG1]], 3, 24, 0, 715; CHECK: mr 3, [[REG1]]16; CHECK: blr17}18 19define i64 @bs8(i64 %x) #0 {20entry:21 %0 = tail call i64 @llvm.bswap.i64(i64 %x)22 ret i64 %023 24; CHECK-LABEL: @bs825; CHECK-DAG: rotldi [[REG1:[0-9]+]], 3, 1626; CHECK-DAG: rotldi [[REG2:[0-9]+]], 3, 827; CHECK-DAG: rotldi [[REG3:[0-9]+]], 3, 2428; CHECK-DAG: rldimi [[REG2]], [[REG1]], 8, 4829; CHECK-DAG: rotldi [[REG4:[0-9]+]], 3, 3230; CHECK-DAG: rldimi [[REG2]], [[REG3]], 16, 4031; CHECK-DAG: rotldi [[REG5:[0-9]+]], 3, 4832; CHECK-DAG: rldimi [[REG2]], [[REG4]], 24, 3233; CHECK-DAG: rotldi [[REG6:[0-9]+]], 3, 5634; CHECK-DAG: rldimi [[REG2]], [[REG5]], 40, 1635; CHECK-DAG: rldimi [[REG2]], [[REG6]], 48, 836; CHECK-DAG: rldimi [[REG2]], 3, 56, 037; CHECK: mr 3, [[REG2]]38; CHECK: blr39}40 41define i64 @test1(i64 %i0, i64 %i1) #0 {42entry:43 %0 = lshr i64 %i1, 844 %and = and i64 %0, 596377600045 ret i64 %and46 47; CHECK-LABEL: @test148; CHECK-DAG: li [[REG1:[0-9]+]], 1137549; CHECK-DAG: rotldi [[REG3:[0-9]+]], 4, 5650; CHECK-DAG: rldic [[REG2:[0-9]+]], [[REG1]], 19, 3151; CHECK: and 3, [[REG3]], [[REG2]]52; CHECK: blr53}54 55define i64 @test2(i64 %i0, i64 %i1) #0 {56entry:57 %0 = lshr i64 %i1, 658 %and = and i64 %0, 13343480867035545659 ret i64 %and60 61; CHECK-LABEL: @test262; CHECK-DAG: lis [[REG1:[0-9]+]], 763; CHECK-DAG: rotldi [[REG5:[0-9]+]], 4, 5864; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 2668165; CHECK-DAG: rldic [[REG3:[0-9]+]], [[REG2]], 38, 766; CHECK-DAG: oris [[REG4:[0-9]+]], [[REG3]], 2546467; CHECK: and 3, [[REG5]], [[REG4]]68; CHECK: blr69}70 71define i64 @test3(i64 %i0, i64 %i1) #0 {72entry:73 %0 = shl i64 %i0, 3474 %and = and i64 %0, 19179573315266150475 ret i64 %and76 77; CHECK-LABEL: @test378; CHECK-DAG: lis [[REG1:[0-9]+]], 17079; CHECK-DAG: rotldi [[REG4:[0-9]+]], 3, 3480; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 2286181; CHECK-DAG: rldic [[REG3:[0-9]+]], [[REG2]], 34, 682; CHECK: and 3, [[REG4]], [[REG3]]83; CHECK: blr84}85 86define i64 @test4(i64 %i0, i64 %i1) #0 {87entry:88 %0 = lshr i64 %i1, 1589 %and = and i64 %0, 5819596890 ret i64 %and91 92; CHECK-LABEL: @test493; CHECK: rotldi [[REG1:[0-9]+]], 4, 4994; CHECK: andis. 3, [[REG1]], 88895; CHECK: blr96}97 98define i64 @test5(i64 %i0, i64 %i1) #0 {99entry:100 %0 = shl i64 %i1, 12101 %and = and i64 %0, 127252959854592102 ret i64 %and103 104; CHECK-LABEL: @test5105; CHECK-DAG: lis [[REG1:[0-9]+]], 3703106; CHECK-DAG: rotldi [[REG4:[0-9]+]], 4, 12107; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 35951108; CHECK-DAG: rldic [[REG3:[0-9]+]], [[REG2]], 19, 17109; CHECK: and 3, [[REG4]], [[REG3]]110; CHECK: blr111}112 113; Function Attrs: nounwind readnone114define zeroext i32 @test6(i32 zeroext %x) #0 {115entry:116 %and = lshr i32 %x, 16117 %shr = and i32 %and, 255118 %and1 = shl i32 %x, 16119 %shl = and i32 %and1, 16711680120 %or = or i32 %shr, %shl121 ret i32 %or122 123; CHECK-LABEL: @test6124; CHECK: rlwinm [[REG1:[0-9]+]], 3, 16, 24, 31125; CHECK: rlwimi [[REG1]], 3, 16, 8, 15126; CHECK: mr 3, [[REG1]]127; CHECK: blr128}129 130define i64 @test7(i64 %i0, i64 %i1) #0 {131entry:132 %0 = lshr i64 %i0, 5133 %and = and i64 %0, 58195968134 ret i64 %and135 136; CHECK-LABEL: @test7137; CHECK: rlwinm [[REG1:[0-9]+]], 3, 27, 9, 12138; CHECK: rlwimi [[REG1]], 3, 27, 6, 7139; CHECK: mr 3, [[REG1]]140; CHECK: blr141}142 143define i64 @test8(i64 %i0, i64 %i1) #0 {144entry:145 %0 = lshr i64 %i0, 1146 %and = and i64 %0, 169172533248147 ret i64 %and148 149; CHECK-LABEL: @test8150; CHECK-DAG: lis [[REG1:[0-9]+]], 4151; CHECK-DAG: rotldi [[REG4:[0-9]+]], 3, 63152; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 60527153; CHECK-DAG: rldic [[REG3:[0-9]+]], [[REG2]], 19, 26154; CHECK: and 3, [[REG4]], [[REG3]]155; CHECK: blr156}157 158define i64 @test9(i64 %i0, i64 %i1) #0 {159entry:160 %0 = lshr i64 %i1, 14161 %and = and i64 %0, 18848677888162 %1 = shl i64 %i1, 51163 %and3 = and i64 %1, 405323966463344640164 %or4 = or i64 %and, %and3165 ret i64 %or4166 167; CHECK-LABEL: @test9168; CHECK-DAG: lis [[REG1:[0-9]+]], 360169; CHECK-DAG: rotldi [[REG5:[0-9]+]], 4, 62170; CHECK-DAG: rotldi [[REG6:[0-9]+]], 4, 50171; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 1172; CHECK-DAG: rldimi [[REG6]], [[REG5]], 53, 0173; CHECK-DAG: rldic [[REG3:[0-9]+]], [[REG2]], 34, 5174; CHECK-DAG: oris [[REG4:[0-9]+]], [[REG3]], 25464175; CHECK: and 3, [[REG6]], [[REG4]]176; CHECK: blr177}178 179define i64 @test10(i64 %i0, i64 %i1) #0 {180entry:181 %0 = shl i64 %i0, 37182 %and = and i64 %0, 15881483390550016183 %1 = shl i64 %i0, 25184 %and3 = and i64 %1, 2473599172608185 %or4 = or i64 %and, %and3186 ret i64 %or4187 188; CHECK-LABEL: @test10189; CHECK-DAG: lis [[REG1:[0-9]+]], 1190; CHECK-DAG: rotldi [[REG6:[0-9]+]], 3, 25191; CHECK-DAG: rotldi [[REG7:[0-9]+]], 3, 37192; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 8183193; CHECK-DAG: li [[REG3:[0-9]+]], -15519194; CHECK-DAG: rldic [[REG4:[0-9]+]], [[REG2]], 25, 22195; CHECK-DAG: rldic [[REG5:[0-9]+]], [[REG3]], 37, 10196; CHECK-DAG: and [[REG8:[0-9]+]], [[REG6]], [[REG4]]197; CHECK-DAG: and [[REG9:[0-9]+]], [[REG7]], [[REG5]]198; CHECK: or 3, [[REG9]], [[REG8]]199; CHECK: blr200}201 202define i64 @test11(i64 %x) #0 {203entry:204 %and = and i64 %x, 4294967295205 %shl = shl i64 %x, 32206 %or = or i64 %and, %shl207 ret i64 %or208 209; CHECK-LABEL: @test11210; CHECK: rlwinm 3, 3, 0, 1, 0211; CHECK: blr212}213 214define i64 @test12(i64 %x) #0 {215entry:216 %and = and i64 %x, 4294905855217 %shl = shl i64 %x, 32218 %or = or i64 %and, %shl219 ret i64 %or220 221; CHECK-LABEL: @test12222; CHECK: rlwinm 3, 3, 0, 20, 15223; CHECK: blr224}225 226define i64 @test13(i64 %x) #0 {227entry:228 %shl = shl i64 %x, 4229 %and = and i64 %shl, 240230 %shr = lshr i64 %x, 28231 %and1 = and i64 %shr, 15232 %or = or i64 %and, %and1233 ret i64 %or234 235; CHECK-LABEL: @test13236; CHECK: rlwinm 3, 3, 4, 24, 31237; CHECK: blr238}239 240define i64 @test14(i64 %x) #0 {241entry:242 %shl = shl i64 %x, 4243 %and = and i64 %shl, 240244 %shr = lshr i64 %x, 28245 %and1 = and i64 %shr, 15246 %and2 = and i64 %x, -4294967296247 %or = or i64 %and1, %and2248 %or3 = or i64 %or, %and249 ret i64 %or3250 251; CHECK-LABEL: @test14252; CHECK: rldicr [[REG1:[0-9]+]], 3, 0, 31253; CHECK: rlwimi [[REG1]], 3, 4, 24, 31254; CHECK: mr 3, [[REG1]]255; CHECK: blr256}257 258define i64 @test15(i64 %x) #0 {259entry:260 %shl = shl i64 %x, 4261 %and = and i64 %shl, 240262 %shr = lshr i64 %x, 28263 %and1 = and i64 %shr, 15264 %and2 = and i64 %x, -256265 %or = or i64 %and1, %and2266 %or3 = or i64 %or, %and267 ret i64 %or3268 269; CHECK-LABEL: @test15270; CHECK: rlwimi 3, 3, 4, 24, 31271; CHECK: blr272}273 274define i64 @test16(i64 %a, i64 %b) #0 {275entry:276 %and = and i64 %a, 4294967295277 %shl = shl i64 %b, 32278 %or = or i64 %and, %shl279 ret i64 %or280 281; CHECK-LABEL: @test16282; CHECK: rldimi 3, 4, 32, 0283; CHECK: blr284}285 286; Function Attrs: nounwind readnone287declare i32 @llvm.bswap.i32(i32) #0288declare i64 @llvm.bswap.i64(i64) #0289 290attributes #0 = { nounwind readnone }291 292