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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mcpu=pwr7 -ppc-asm-full-reg-names -verify-machineinstrs \3; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \4; RUN: -check-prefix=P7BE5; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -verify-machineinstrs \6; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \7; RUN: -check-prefix=P8LE8; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -verify-machineinstrs \9; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \10; RUN: -check-prefix=P9LE11 12; FIXME: P7BE for i128 looks wrong.13define <1 x i128> @One1i128() {14; P7BE-LABEL: One1i128:15; P7BE: # %bb.0: # %entry16; P7BE-NEXT: li r3, -117; P7BE-NEXT: li r4, -118; P7BE-NEXT: blr19;20; P8LE-LABEL: One1i128:21; P8LE: # %bb.0: # %entry22; P8LE-NEXT: xxleqv vs34, vs34, vs3423; P8LE-NEXT: blr24;25; P9LE-LABEL: One1i128:26; P9LE: # %bb.0: # %entry27; P9LE-NEXT: xxleqv vs34, vs34, vs3428; P9LE-NEXT: blr29entry:30 ret <1 x i128> <i128 -1>31}32 33define <2 x i64> @One2i64() {34; P7BE-LABEL: One2i64:35; P7BE: # %bb.0: # %entry36; P7BE-NEXT: vspltisb v2, -137; P7BE-NEXT: blr38;39; P8LE-LABEL: One2i64:40; P8LE: # %bb.0: # %entry41; P8LE-NEXT: xxleqv vs34, vs34, vs3442; P8LE-NEXT: blr43;44; P9LE-LABEL: One2i64:45; P9LE: # %bb.0: # %entry46; P9LE-NEXT: xxleqv vs34, vs34, vs3447; P9LE-NEXT: blr48entry:49 ret <2 x i64> <i64 -1, i64 -1>50}51 52define <4 x i32> @One4i32() {53; P7BE-LABEL: One4i32:54; P7BE: # %bb.0: # %entry55; P7BE-NEXT: vspltisb v2, -156; P7BE-NEXT: blr57;58; P8LE-LABEL: One4i32:59; P8LE: # %bb.0: # %entry60; P8LE-NEXT: xxleqv vs34, vs34, vs3461; P8LE-NEXT: blr62;63; P9LE-LABEL: One4i32:64; P9LE: # %bb.0: # %entry65; P9LE-NEXT: xxleqv vs34, vs34, vs3466; P9LE-NEXT: blr67entry:68 ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>69}70 71define <8 x i16> @One8i16() {72; P7BE-LABEL: One8i16:73; P7BE: # %bb.0: # %entry74; P7BE-NEXT: vspltisb v2, -175; P7BE-NEXT: blr76;77; P8LE-LABEL: One8i16:78; P8LE: # %bb.0: # %entry79; P8LE-NEXT: xxleqv vs34, vs34, vs3480; P8LE-NEXT: blr81;82; P9LE-LABEL: One8i16:83; P9LE: # %bb.0: # %entry84; P9LE-NEXT: xxleqv vs34, vs34, vs3485; P9LE-NEXT: blr86entry:87 ret <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>88}89 90define <16 x i8> @One16i8() {91; P7BE-LABEL: One16i8:92; P7BE: # %bb.0: # %entry93; P7BE-NEXT: vspltisb v2, -194; P7BE-NEXT: blr95;96; P8LE-LABEL: One16i8:97; P8LE: # %bb.0: # %entry98; P8LE-NEXT: xxleqv vs34, vs34, vs3499; P8LE-NEXT: blr100;101; P9LE-LABEL: One16i8:102; P9LE: # %bb.0: # %entry103; P9LE-NEXT: xxleqv vs34, vs34, vs34104; P9LE-NEXT: blr105entry:106 ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>107}108