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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mcpu=pwr7 < %s | FileCheck --check-prefix=PWR7-BE %s3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mcpu=pwr8 < %s | FileCheck --check-prefix=PWR8-BE %s4; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- -mcpu=pwr7 < %s | FileCheck --check-prefix=PWR7-LE %s5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- -mcpu=pwr8 < %s | FileCheck --check-prefix=PWR8-LE %s6 7define <2 x i64> @build_v2i64_extload_0(ptr nocapture noundef readonly %p) {8; PWR7-BE-LABEL: build_v2i64_extload_0:9; PWR7-BE: # %bb.0: # %entry10; PWR7-BE-NEXT: lwz 3, 0(3)11; PWR7-BE-NEXT: li 4, 012; PWR7-BE-NEXT: std 4, -8(1)13; PWR7-BE-NEXT: std 3, -16(1)14; PWR7-BE-NEXT: addi 3, 1, -1615; PWR7-BE-NEXT: lxvd2x 34, 0, 316; PWR7-BE-NEXT: blr17;18; PWR8-BE-LABEL: build_v2i64_extload_0:19; PWR8-BE: # %bb.0: # %entry20; PWR8-BE-NEXT: lwz 3, 0(3)21; PWR8-BE-NEXT: li 4, 022; PWR8-BE-NEXT: mtfprd 0, 423; PWR8-BE-NEXT: mtfprd 1, 324; PWR8-BE-NEXT: xxmrghd 34, 1, 025; PWR8-BE-NEXT: blr26;27; PWR7-LE-LABEL: build_v2i64_extload_0:28; PWR7-LE: # %bb.0: # %entry29; PWR7-LE-NEXT: lfiwzx 0, 0, 330; PWR7-LE-NEXT: addis 3, 2, .LCPI0_0@toc@ha31; PWR7-LE-NEXT: xxlxor 36, 36, 3632; PWR7-LE-NEXT: addi 3, 3, .LCPI0_0@toc@l33; PWR7-LE-NEXT: xxspltw 34, 0, 134; PWR7-LE-NEXT: lxvd2x 0, 0, 335; PWR7-LE-NEXT: xxswapd 35, 036; PWR7-LE-NEXT: vperm 2, 4, 2, 337; PWR7-LE-NEXT: blr38;39; PWR8-LE-LABEL: build_v2i64_extload_0:40; PWR8-LE: # %bb.0: # %entry41; PWR8-LE-NEXT: lwz 3, 0(3)42; PWR8-LE-NEXT: li 4, 043; PWR8-LE-NEXT: rldimi 3, 4, 32, 044; PWR8-LE-NEXT: rldimi 4, 4, 32, 045; PWR8-LE-NEXT: mtfprd 0, 346; PWR8-LE-NEXT: mtfprd 1, 447; PWR8-LE-NEXT: xxmrghd 34, 1, 048; PWR8-LE-NEXT: blr49entry:50 %0 = load i32, ptr %p, align 451 %conv = zext i32 %0 to i6452 %vecinit1 = insertelement <2 x i64> <i64 0, i64 0>, i64 %conv, i64 053 ret <2 x i64> %vecinit154}55 56define <2 x i64> @build_v2i64_extload_1(ptr nocapture noundef readonly %p) {57; PWR7-BE-LABEL: build_v2i64_extload_1:58; PWR7-BE: # %bb.0: # %entry59; PWR7-BE-NEXT: lwz 3, 0(3)60; PWR7-BE-NEXT: li 4, 061; PWR7-BE-NEXT: std 4, -16(1)62; PWR7-BE-NEXT: std 3, -8(1)63; PWR7-BE-NEXT: addi 3, 1, -1664; PWR7-BE-NEXT: lxvd2x 34, 0, 365; PWR7-BE-NEXT: blr66;67; PWR8-BE-LABEL: build_v2i64_extload_1:68; PWR8-BE: # %bb.0: # %entry69; PWR8-BE-NEXT: lwz 3, 0(3)70; PWR8-BE-NEXT: li 4, 071; PWR8-BE-NEXT: mtfprd 0, 472; PWR8-BE-NEXT: mtfprd 1, 373; PWR8-BE-NEXT: xxmrghd 34, 0, 174; PWR8-BE-NEXT: blr75;76; PWR7-LE-LABEL: build_v2i64_extload_1:77; PWR7-LE: # %bb.0: # %entry78; PWR7-LE-NEXT: lwz 3, 0(3)79; PWR7-LE-NEXT: li 4, 080; PWR7-LE-NEXT: std 4, -16(1)81; PWR7-LE-NEXT: std 3, -8(1)82; PWR7-LE-NEXT: addi 3, 1, -1683; PWR7-LE-NEXT: lxvd2x 0, 0, 384; PWR7-LE-NEXT: xxswapd 34, 085; PWR7-LE-NEXT: blr86;87; PWR8-LE-LABEL: build_v2i64_extload_1:88; PWR8-LE: # %bb.0: # %entry89; PWR8-LE-NEXT: lwz 3, 0(3)90; PWR8-LE-NEXT: li 4, 091; PWR8-LE-NEXT: mtfprd 0, 492; PWR8-LE-NEXT: mtfprd 1, 393; PWR8-LE-NEXT: xxmrghd 34, 1, 094; PWR8-LE-NEXT: blr95entry:96 %0 = load i32, ptr %p, align 497 %conv = zext i32 %0 to i6498 %vecinit1 = insertelement <2 x i64> <i64 0, i64 0>, i64 %conv, i64 199 ret <2 x i64> %vecinit1100}101 102define <2 x double> @build_v2f64_extload_0(ptr nocapture noundef readonly %p) {103; PWR7-BE-LABEL: build_v2f64_extload_0:104; PWR7-BE: # %bb.0: # %entry105; PWR7-BE-NEXT: lfs 0, 0(3)106; PWR7-BE-NEXT: xxlxor 1, 1, 1107; PWR7-BE-NEXT: xxmrghd 34, 0, 1108; PWR7-BE-NEXT: blr109;110; PWR8-BE-LABEL: build_v2f64_extload_0:111; PWR8-BE: # %bb.0: # %entry112; PWR8-BE-NEXT: lfs 0, 0(3)113; PWR8-BE-NEXT: xxlxor 1, 1, 1114; PWR8-BE-NEXT: xxmrghd 34, 0, 1115; PWR8-BE-NEXT: blr116;117; PWR7-LE-LABEL: build_v2f64_extload_0:118; PWR7-LE: # %bb.0: # %entry119; PWR7-LE-NEXT: lfs 0, 0(3)120; PWR7-LE-NEXT: xxlxor 1, 1, 1121; PWR7-LE-NEXT: xxmrghd 34, 1, 0122; PWR7-LE-NEXT: blr123;124; PWR8-LE-LABEL: build_v2f64_extload_0:125; PWR8-LE: # %bb.0: # %entry126; PWR8-LE-NEXT: lfs 0, 0(3)127; PWR8-LE-NEXT: xxlxor 1, 1, 1128; PWR8-LE-NEXT: xxmrghd 34, 1, 0129; PWR8-LE-NEXT: blr130entry:131 %0 = load float, ptr %p, align 4132 %conv = fpext float %0 to double133 %vecinit1 = insertelement <2 x double> <double 0.000000e+00, double 0.000000e+00>, double %conv, i64 0134 ret <2 x double> %vecinit1135}136 137define <2 x double> @build_v2f64_extload_1(ptr nocapture noundef readonly %p) {138; PWR7-BE-LABEL: build_v2f64_extload_1:139; PWR7-BE: # %bb.0: # %entry140; PWR7-BE-NEXT: lfs 0, 0(3)141; PWR7-BE-NEXT: xxlxor 1, 1, 1142; PWR7-BE-NEXT: xxmrghd 34, 1, 0143; PWR7-BE-NEXT: blr144;145; PWR8-BE-LABEL: build_v2f64_extload_1:146; PWR8-BE: # %bb.0: # %entry147; PWR8-BE-NEXT: lfs 0, 0(3)148; PWR8-BE-NEXT: xxlxor 1, 1, 1149; PWR8-BE-NEXT: xxmrghd 34, 1, 0150; PWR8-BE-NEXT: blr151;152; PWR7-LE-LABEL: build_v2f64_extload_1:153; PWR7-LE: # %bb.0: # %entry154; PWR7-LE-NEXT: lfs 0, 0(3)155; PWR7-LE-NEXT: xxlxor 1, 1, 1156; PWR7-LE-NEXT: xxmrghd 34, 0, 1157; PWR7-LE-NEXT: blr158;159; PWR8-LE-LABEL: build_v2f64_extload_1:160; PWR8-LE: # %bb.0: # %entry161; PWR8-LE-NEXT: lfs 0, 0(3)162; PWR8-LE-NEXT: xxlxor 1, 1, 1163; PWR8-LE-NEXT: xxmrghd 34, 0, 1164; PWR8-LE-NEXT: blr165entry:166 %0 = load float, ptr %p, align 4167 %conv = fpext float %0 to double168 %vecinit1 = insertelement <2 x double> <double 0.000000e+00, double 0.000000e+00>, double %conv, i64 1169 ret <2 x double> %vecinit1170}171 172define <2 x double> @build_v2f64_load_0(ptr nocapture noundef readonly %p) {173; PWR7-BE-LABEL: build_v2f64_load_0:174; PWR7-BE: # %bb.0: # %entry175; PWR7-BE-NEXT: lfd 0, 0(3)176; PWR7-BE-NEXT: xxlxor 1, 1, 1177; PWR7-BE-NEXT: xxmrghd 34, 0, 1178; PWR7-BE-NEXT: blr179;180; PWR8-BE-LABEL: build_v2f64_load_0:181; PWR8-BE: # %bb.0: # %entry182; PWR8-BE-NEXT: lfd 0, 0(3)183; PWR8-BE-NEXT: xxlxor 1, 1, 1184; PWR8-BE-NEXT: xxmrghd 34, 0, 1185; PWR8-BE-NEXT: blr186;187; PWR7-LE-LABEL: build_v2f64_load_0:188; PWR7-LE: # %bb.0: # %entry189; PWR7-LE-NEXT: lfd 0, 0(3)190; PWR7-LE-NEXT: xxlxor 1, 1, 1191; PWR7-LE-NEXT: xxmrghd 34, 1, 0192; PWR7-LE-NEXT: blr193;194; PWR8-LE-LABEL: build_v2f64_load_0:195; PWR8-LE: # %bb.0: # %entry196; PWR8-LE-NEXT: lfd 0, 0(3)197; PWR8-LE-NEXT: xxlxor 1, 1, 1198; PWR8-LE-NEXT: xxmrghd 34, 1, 0199; PWR8-LE-NEXT: blr200entry:201 %0 = load double, ptr %p, align 8202 %vecinit1 = insertelement <2 x double> <double 0.000000e+00, double 0.000000e+00>, double %0, i64 0203 ret <2 x double> %vecinit1204}205 206define <2 x double> @build_v2f64_load_1(ptr nocapture noundef readonly %p) {207; PWR7-BE-LABEL: build_v2f64_load_1:208; PWR7-BE: # %bb.0: # %entry209; PWR7-BE-NEXT: lfd 0, 0(3)210; PWR7-BE-NEXT: xxlxor 1, 1, 1211; PWR7-BE-NEXT: xxmrghd 34, 1, 0212; PWR7-BE-NEXT: blr213;214; PWR8-BE-LABEL: build_v2f64_load_1:215; PWR8-BE: # %bb.0: # %entry216; PWR8-BE-NEXT: lfd 0, 0(3)217; PWR8-BE-NEXT: xxlxor 1, 1, 1218; PWR8-BE-NEXT: xxmrghd 34, 1, 0219; PWR8-BE-NEXT: blr220;221; PWR7-LE-LABEL: build_v2f64_load_1:222; PWR7-LE: # %bb.0: # %entry223; PWR7-LE-NEXT: lfd 0, 0(3)224; PWR7-LE-NEXT: xxlxor 1, 1, 1225; PWR7-LE-NEXT: xxmrghd 34, 0, 1226; PWR7-LE-NEXT: blr227;228; PWR8-LE-LABEL: build_v2f64_load_1:229; PWR8-LE: # %bb.0: # %entry230; PWR8-LE-NEXT: lfd 0, 0(3)231; PWR8-LE-NEXT: xxlxor 1, 1, 1232; PWR8-LE-NEXT: xxmrghd 34, 0, 1233; PWR8-LE-NEXT: blr234entry:235 %0 = load double, ptr %p, align 8236 %vecinit1 = insertelement <2 x double> <double 0.000000e+00, double 0.000000e+00>, double %0, i64 1237 ret <2 x double> %vecinit1238}239 240define <2 x i64> @build_v2i64_load_0(ptr nocapture noundef readonly %p) {241; PWR7-BE-LABEL: build_v2i64_load_0:242; PWR7-BE: # %bb.0: # %entry243; PWR7-BE-NEXT: ld 3, 0(3)244; PWR7-BE-NEXT: li 4, 0245; PWR7-BE-NEXT: std 4, -8(1)246; PWR7-BE-NEXT: std 3, -16(1)247; PWR7-BE-NEXT: addi 3, 1, -16248; PWR7-BE-NEXT: lxvd2x 34, 0, 3249; PWR7-BE-NEXT: blr250;251; PWR8-BE-LABEL: build_v2i64_load_0:252; PWR8-BE: # %bb.0: # %entry253; PWR8-BE-NEXT: ld 3, 0(3)254; PWR8-BE-NEXT: li 4, 0255; PWR8-BE-NEXT: mtfprd 0, 4256; PWR8-BE-NEXT: mtfprd 1, 3257; PWR8-BE-NEXT: xxmrghd 34, 1, 0258; PWR8-BE-NEXT: blr259;260; PWR7-LE-LABEL: build_v2i64_load_0:261; PWR7-LE: # %bb.0: # %entry262; PWR7-LE-NEXT: ld 3, 0(3)263; PWR7-LE-NEXT: li 4, 0264; PWR7-LE-NEXT: std 4, -8(1)265; PWR7-LE-NEXT: std 3, -16(1)266; PWR7-LE-NEXT: addi 3, 1, -16267; PWR7-LE-NEXT: lxvd2x 0, 0, 3268; PWR7-LE-NEXT: xxswapd 34, 0269; PWR7-LE-NEXT: blr270;271; PWR8-LE-LABEL: build_v2i64_load_0:272; PWR8-LE: # %bb.0: # %entry273; PWR8-LE-NEXT: ld 3, 0(3)274; PWR8-LE-NEXT: li 4, 0275; PWR8-LE-NEXT: mtfprd 0, 4276; PWR8-LE-NEXT: mtfprd 1, 3277; PWR8-LE-NEXT: xxmrghd 34, 0, 1278; PWR8-LE-NEXT: blr279entry:280 %0 = load i64, ptr %p, align 8281 %vecinit1 = insertelement <2 x i64> <i64 0, i64 0>, i64 %0, i64 0282 ret <2 x i64> %vecinit1283}284 285define <2 x i64> @build_v2i64_load_1(ptr nocapture noundef readonly %p) {286; PWR7-BE-LABEL: build_v2i64_load_1:287; PWR7-BE: # %bb.0: # %entry288; PWR7-BE-NEXT: ld 3, 0(3)289; PWR7-BE-NEXT: li 4, 0290; PWR7-BE-NEXT: std 4, -16(1)291; PWR7-BE-NEXT: std 3, -8(1)292; PWR7-BE-NEXT: addi 3, 1, -16293; PWR7-BE-NEXT: lxvd2x 34, 0, 3294; PWR7-BE-NEXT: blr295;296; PWR8-BE-LABEL: build_v2i64_load_1:297; PWR8-BE: # %bb.0: # %entry298; PWR8-BE-NEXT: ld 3, 0(3)299; PWR8-BE-NEXT: li 4, 0300; PWR8-BE-NEXT: mtfprd 0, 4301; PWR8-BE-NEXT: mtfprd 1, 3302; PWR8-BE-NEXT: xxmrghd 34, 0, 1303; PWR8-BE-NEXT: blr304;305; PWR7-LE-LABEL: build_v2i64_load_1:306; PWR7-LE: # %bb.0: # %entry307; PWR7-LE-NEXT: ld 3, 0(3)308; PWR7-LE-NEXT: li 4, 0309; PWR7-LE-NEXT: std 4, -16(1)310; PWR7-LE-NEXT: std 3, -8(1)311; PWR7-LE-NEXT: addi 3, 1, -16312; PWR7-LE-NEXT: lxvd2x 0, 0, 3313; PWR7-LE-NEXT: xxswapd 34, 0314; PWR7-LE-NEXT: blr315;316; PWR8-LE-LABEL: build_v2i64_load_1:317; PWR8-LE: # %bb.0: # %entry318; PWR8-LE-NEXT: ld 3, 0(3)319; PWR8-LE-NEXT: li 4, 0320; PWR8-LE-NEXT: mtfprd 0, 4321; PWR8-LE-NEXT: mtfprd 1, 3322; PWR8-LE-NEXT: xxmrghd 34, 1, 0323; PWR8-LE-NEXT: blr324entry:325 %0 = load i64, ptr %p, align 8326 %vecinit1 = insertelement <2 x i64> <i64 0, i64 0>, i64 %0, i64 1327 ret <2 x i64> %vecinit1328}329 330define <4 x i32> @build_v4i32_load_0(ptr nocapture noundef readonly %p) {331; PWR7-BE-LABEL: build_v4i32_load_0:332; PWR7-BE: # %bb.0: # %entry333; PWR7-BE-NEXT: lfiwzx 0, 0, 3334; PWR7-BE-NEXT: addis 3, 2, .LCPI8_0@toc@ha335; PWR7-BE-NEXT: xxlxor 36, 36, 36336; PWR7-BE-NEXT: addi 3, 3, .LCPI8_0@toc@l337; PWR7-BE-NEXT: lxvw4x 35, 0, 3338; PWR7-BE-NEXT: xxspltw 34, 0, 1339; PWR7-BE-NEXT: vperm 2, 2, 4, 3340; PWR7-BE-NEXT: blr341;342; PWR8-BE-LABEL: build_v4i32_load_0:343; PWR8-BE: # %bb.0: # %entry344; PWR8-BE-NEXT: lwz 3, 0(3)345; PWR8-BE-NEXT: li 4, 0346; PWR8-BE-NEXT: li 5, 0347; PWR8-BE-NEXT: rldimi 4, 4, 32, 0348; PWR8-BE-NEXT: rldimi 5, 3, 32, 0349; PWR8-BE-NEXT: mtfprd 1, 4350; PWR8-BE-NEXT: mtfprd 0, 5351; PWR8-BE-NEXT: xxmrghd 34, 0, 1352; PWR8-BE-NEXT: blr353;354; PWR7-LE-LABEL: build_v4i32_load_0:355; PWR7-LE: # %bb.0: # %entry356; PWR7-LE-NEXT: lfiwzx 0, 0, 3357; PWR7-LE-NEXT: addis 3, 2, .LCPI8_0@toc@ha358; PWR7-LE-NEXT: xxlxor 36, 36, 36359; PWR7-LE-NEXT: addi 3, 3, .LCPI8_0@toc@l360; PWR7-LE-NEXT: xxspltw 34, 0, 1361; PWR7-LE-NEXT: lxvd2x 0, 0, 3362; PWR7-LE-NEXT: xxswapd 35, 0363; PWR7-LE-NEXT: vperm 2, 4, 2, 3364; PWR7-LE-NEXT: blr365;366; PWR8-LE-LABEL: build_v4i32_load_0:367; PWR8-LE: # %bb.0: # %entry368; PWR8-LE-NEXT: lwz 3, 0(3)369; PWR8-LE-NEXT: li 4, 0370; PWR8-LE-NEXT: rldimi 3, 4, 32, 0371; PWR8-LE-NEXT: rldimi 4, 4, 32, 0372; PWR8-LE-NEXT: mtfprd 0, 3373; PWR8-LE-NEXT: mtfprd 1, 4374; PWR8-LE-NEXT: xxmrghd 34, 1, 0375; PWR8-LE-NEXT: blr376entry:377 %0 = load i32, ptr %p, align 4378 %vecinit1 = insertelement <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i32 %0, i32 0379 ret <4 x i32> %vecinit1380}381 382define <4 x i32> @build_v4i32_load_1(ptr nocapture noundef readonly %p) {383; PWR7-BE-LABEL: build_v4i32_load_1:384; PWR7-BE: # %bb.0: # %entry385; PWR7-BE-NEXT: lfiwzx 0, 0, 3386; PWR7-BE-NEXT: addis 3, 2, .LCPI9_0@toc@ha387; PWR7-BE-NEXT: xxlxor 36, 36, 36388; PWR7-BE-NEXT: addi 3, 3, .LCPI9_0@toc@l389; PWR7-BE-NEXT: lxvw4x 35, 0, 3390; PWR7-BE-NEXT: xxspltw 34, 0, 1391; PWR7-BE-NEXT: vperm 2, 4, 2, 3392; PWR7-BE-NEXT: blr393;394; PWR8-BE-LABEL: build_v4i32_load_1:395; PWR8-BE: # %bb.0: # %entry396; PWR8-BE-NEXT: lwz 3, 0(3)397; PWR8-BE-NEXT: li 4, 0398; PWR8-BE-NEXT: rldimi 3, 4, 32, 0399; PWR8-BE-NEXT: rldimi 4, 4, 32, 0400; PWR8-BE-NEXT: mtfprd 0, 3401; PWR8-BE-NEXT: mtfprd 1, 4402; PWR8-BE-NEXT: xxmrghd 34, 0, 1403; PWR8-BE-NEXT: blr404;405; PWR7-LE-LABEL: build_v4i32_load_1:406; PWR7-LE: # %bb.0: # %entry407; PWR7-LE-NEXT: lfiwzx 0, 0, 3408; PWR7-LE-NEXT: addis 3, 2, .LCPI9_0@toc@ha409; PWR7-LE-NEXT: xxlxor 36, 36, 36410; PWR7-LE-NEXT: addi 3, 3, .LCPI9_0@toc@l411; PWR7-LE-NEXT: xxspltw 34, 0, 1412; PWR7-LE-NEXT: lxvd2x 0, 0, 3413; PWR7-LE-NEXT: xxswapd 35, 0414; PWR7-LE-NEXT: vperm 2, 2, 4, 3415; PWR7-LE-NEXT: blr416;417; PWR8-LE-LABEL: build_v4i32_load_1:418; PWR8-LE: # %bb.0: # %entry419; PWR8-LE-NEXT: lwz 3, 0(3)420; PWR8-LE-NEXT: li 4, 0421; PWR8-LE-NEXT: li 5, 0422; PWR8-LE-NEXT: rldimi 4, 4, 32, 0423; PWR8-LE-NEXT: rldimi 5, 3, 32, 0424; PWR8-LE-NEXT: mtfprd 1, 4425; PWR8-LE-NEXT: mtfprd 0, 5426; PWR8-LE-NEXT: xxmrghd 34, 1, 0427; PWR8-LE-NEXT: blr428entry:429 %0 = load i32, ptr %p, align 4430 %vecinit1 = insertelement <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i32 %0, i32 1431 ret <4 x i32> %vecinit1432}433 434define <4 x i32> @build_v4i32_load_2(ptr nocapture noundef readonly %p) {435; PWR7-BE-LABEL: build_v4i32_load_2:436; PWR7-BE: # %bb.0: # %entry437; PWR7-BE-NEXT: lfiwzx 0, 0, 3438; PWR7-BE-NEXT: addis 3, 2, .LCPI10_0@toc@ha439; PWR7-BE-NEXT: xxlxor 36, 36, 36440; PWR7-BE-NEXT: addi 3, 3, .LCPI10_0@toc@l441; PWR7-BE-NEXT: lxvw4x 35, 0, 3442; PWR7-BE-NEXT: xxspltw 34, 0, 1443; PWR7-BE-NEXT: vperm 2, 4, 2, 3444; PWR7-BE-NEXT: blr445;446; PWR8-BE-LABEL: build_v4i32_load_2:447; PWR8-BE: # %bb.0: # %entry448; PWR8-BE-NEXT: lwz 3, 0(3)449; PWR8-BE-NEXT: li 4, 0450; PWR8-BE-NEXT: li 5, 0451; PWR8-BE-NEXT: rldimi 4, 4, 32, 0452; PWR8-BE-NEXT: rldimi 5, 3, 32, 0453; PWR8-BE-NEXT: mtfprd 1, 4454; PWR8-BE-NEXT: mtfprd 0, 5455; PWR8-BE-NEXT: xxmrghd 34, 1, 0456; PWR8-BE-NEXT: blr457;458; PWR7-LE-LABEL: build_v4i32_load_2:459; PWR7-LE: # %bb.0: # %entry460; PWR7-LE-NEXT: lfiwzx 0, 0, 3461; PWR7-LE-NEXT: addis 3, 2, .LCPI10_0@toc@ha462; PWR7-LE-NEXT: xxlxor 36, 36, 36463; PWR7-LE-NEXT: addi 3, 3, .LCPI10_0@toc@l464; PWR7-LE-NEXT: xxspltw 34, 0, 1465; PWR7-LE-NEXT: lxvd2x 0, 0, 3466; PWR7-LE-NEXT: xxswapd 35, 0467; PWR7-LE-NEXT: vperm 2, 2, 4, 3468; PWR7-LE-NEXT: blr469;470; PWR8-LE-LABEL: build_v4i32_load_2:471; PWR8-LE: # %bb.0: # %entry472; PWR8-LE-NEXT: lwz 3, 0(3)473; PWR8-LE-NEXT: li 4, 0474; PWR8-LE-NEXT: rldimi 3, 4, 32, 0475; PWR8-LE-NEXT: rldimi 4, 4, 32, 0476; PWR8-LE-NEXT: mtfprd 0, 3477; PWR8-LE-NEXT: mtfprd 1, 4478; PWR8-LE-NEXT: xxmrghd 34, 0, 1479; PWR8-LE-NEXT: blr480entry:481 %0 = load i32, ptr %p, align 4482 %vecinit1 = insertelement <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i32 %0, i32 2483 ret <4 x i32> %vecinit1484}485 486define <4 x i32> @build_v4i32_load_3(ptr nocapture noundef readonly %p) {487; PWR7-BE-LABEL: build_v4i32_load_3:488; PWR7-BE: # %bb.0: # %entry489; PWR7-BE-NEXT: lfiwzx 0, 0, 3490; PWR7-BE-NEXT: addis 3, 2, .LCPI11_0@toc@ha491; PWR7-BE-NEXT: xxlxor 36, 36, 36492; PWR7-BE-NEXT: addi 3, 3, .LCPI11_0@toc@l493; PWR7-BE-NEXT: lxvw4x 35, 0, 3494; PWR7-BE-NEXT: xxspltw 34, 0, 1495; PWR7-BE-NEXT: vperm 2, 4, 2, 3496; PWR7-BE-NEXT: blr497;498; PWR8-BE-LABEL: build_v4i32_load_3:499; PWR8-BE: # %bb.0: # %entry500; PWR8-BE-NEXT: lwz 3, 0(3)501; PWR8-BE-NEXT: li 4, 0502; PWR8-BE-NEXT: rldimi 3, 4, 32, 0503; PWR8-BE-NEXT: rldimi 4, 4, 32, 0504; PWR8-BE-NEXT: mtfprd 0, 3505; PWR8-BE-NEXT: mtfprd 1, 4506; PWR8-BE-NEXT: xxmrghd 34, 1, 0507; PWR8-BE-NEXT: blr508;509; PWR7-LE-LABEL: build_v4i32_load_3:510; PWR7-LE: # %bb.0: # %entry511; PWR7-LE-NEXT: lfiwzx 0, 0, 3512; PWR7-LE-NEXT: addis 3, 2, .LCPI11_0@toc@ha513; PWR7-LE-NEXT: xxlxor 36, 36, 36514; PWR7-LE-NEXT: addi 3, 3, .LCPI11_0@toc@l515; PWR7-LE-NEXT: xxspltw 34, 0, 1516; PWR7-LE-NEXT: lxvd2x 0, 0, 3517; PWR7-LE-NEXT: xxswapd 35, 0518; PWR7-LE-NEXT: vperm 2, 2, 4, 3519; PWR7-LE-NEXT: blr520;521; PWR8-LE-LABEL: build_v4i32_load_3:522; PWR8-LE: # %bb.0: # %entry523; PWR8-LE-NEXT: lwz 3, 0(3)524; PWR8-LE-NEXT: li 4, 0525; PWR8-LE-NEXT: li 5, 0526; PWR8-LE-NEXT: rldimi 4, 4, 32, 0527; PWR8-LE-NEXT: rldimi 5, 3, 32, 0528; PWR8-LE-NEXT: mtfprd 1, 4529; PWR8-LE-NEXT: mtfprd 0, 5530; PWR8-LE-NEXT: xxmrghd 34, 0, 1531; PWR8-LE-NEXT: blr532entry:533 %0 = load i32, ptr %p, align 4534 %vecinit1 = insertelement <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i32 %0, i32 3535 ret <4 x i32> %vecinit1536}537 538define <4 x float> @build_v4f32_load_0(ptr nocapture noundef readonly %p) {539; PWR7-BE-LABEL: build_v4f32_load_0:540; PWR7-BE: # %bb.0: # %entry541; PWR7-BE-NEXT: lwz 3, 0(3)542; PWR7-BE-NEXT: li 4, 0543; PWR7-BE-NEXT: stw 4, -16(1)544; PWR7-BE-NEXT: stw 3, -32(1)545; PWR7-BE-NEXT: addis 3, 2, .LCPI12_0@toc@ha546; PWR7-BE-NEXT: addi 3, 3, .LCPI12_0@toc@l547; PWR7-BE-NEXT: lxvw4x 34, 0, 3548; PWR7-BE-NEXT: addi 3, 1, -16549; PWR7-BE-NEXT: lxvw4x 35, 0, 3550; PWR7-BE-NEXT: addi 3, 1, -32551; PWR7-BE-NEXT: lxvw4x 36, 0, 3552; PWR7-BE-NEXT: vperm 2, 4, 3, 2553; PWR7-BE-NEXT: blr554;555; PWR8-BE-LABEL: build_v4f32_load_0:556; PWR8-BE: # %bb.0: # %entry557; PWR8-BE-NEXT: lfs 0, 0(3)558; PWR8-BE-NEXT: xxlxor 1, 1, 1559; PWR8-BE-NEXT: xxmrghd 0, 0, 1560; PWR8-BE-NEXT: xxspltd 1, 1, 0561; PWR8-BE-NEXT: xvcvdpsp 34, 0562; PWR8-BE-NEXT: xvcvdpsp 35, 1563; PWR8-BE-NEXT: vmrgew 2, 2, 3564; PWR8-BE-NEXT: blr565;566; PWR7-LE-LABEL: build_v4f32_load_0:567; PWR7-LE: # %bb.0: # %entry568; PWR7-LE-NEXT: li 4, 0569; PWR7-LE-NEXT: lwz 3, 0(3)570; PWR7-LE-NEXT: stw 4, -16(1)571; PWR7-LE-NEXT: addis 4, 2, .LCPI12_0@toc@ha572; PWR7-LE-NEXT: addi 4, 4, .LCPI12_0@toc@l573; PWR7-LE-NEXT: stw 3, -32(1)574; PWR7-LE-NEXT: addi 3, 1, -32575; PWR7-LE-NEXT: lxvd2x 0, 0, 4576; PWR7-LE-NEXT: addi 4, 1, -16577; PWR7-LE-NEXT: lxvd2x 1, 0, 4578; PWR7-LE-NEXT: xxswapd 34, 0579; PWR7-LE-NEXT: lxvd2x 0, 0, 3580; PWR7-LE-NEXT: xxswapd 35, 1581; PWR7-LE-NEXT: xxswapd 36, 0582; PWR7-LE-NEXT: vperm 2, 3, 4, 2583; PWR7-LE-NEXT: blr584;585; PWR8-LE-LABEL: build_v4f32_load_0:586; PWR8-LE: # %bb.0: # %entry587; PWR8-LE-NEXT: lfs 0, 0(3)588; PWR8-LE-NEXT: xxlxor 1, 1, 1589; PWR8-LE-NEXT: xxmrghd 0, 1, 0590; PWR8-LE-NEXT: xxspltd 1, 1, 0591; PWR8-LE-NEXT: xvcvdpsp 34, 0592; PWR8-LE-NEXT: xvcvdpsp 35, 1593; PWR8-LE-NEXT: vmrgew 2, 3, 2594; PWR8-LE-NEXT: blr595entry:596 %0 = load float, ptr %p, align 4597 %vecinit1 = insertelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %0, i32 0598 ret <4 x float> %vecinit1599}600 601define <4 x float> @build_v4f32_load_1(ptr nocapture noundef readonly %p) {602; PWR7-BE-LABEL: build_v4f32_load_1:603; PWR7-BE: # %bb.0: # %entry604; PWR7-BE-NEXT: lwz 3, 0(3)605; PWR7-BE-NEXT: li 4, 0606; PWR7-BE-NEXT: stw 4, -32(1)607; PWR7-BE-NEXT: stw 3, -16(1)608; PWR7-BE-NEXT: addis 3, 2, .LCPI13_0@toc@ha609; PWR7-BE-NEXT: addi 3, 3, .LCPI13_0@toc@l610; PWR7-BE-NEXT: lxvw4x 34, 0, 3611; PWR7-BE-NEXT: addi 3, 1, -32612; PWR7-BE-NEXT: lxvw4x 35, 0, 3613; PWR7-BE-NEXT: addi 3, 1, -16614; PWR7-BE-NEXT: lxvw4x 36, 0, 3615; PWR7-BE-NEXT: vperm 2, 3, 4, 2616; PWR7-BE-NEXT: blr617;618; PWR8-BE-LABEL: build_v4f32_load_1:619; PWR8-BE: # %bb.0: # %entry620; PWR8-BE-NEXT: lfs 0, 0(3)621; PWR8-BE-NEXT: xxlxor 1, 1, 1622; PWR8-BE-NEXT: xxmrghd 0, 0, 1623; PWR8-BE-NEXT: xxspltd 1, 1, 0624; PWR8-BE-NEXT: xvcvdpsp 34, 0625; PWR8-BE-NEXT: xvcvdpsp 35, 1626; PWR8-BE-NEXT: vmrgew 2, 3, 2627; PWR8-BE-NEXT: blr628;629; PWR7-LE-LABEL: build_v4f32_load_1:630; PWR7-LE: # %bb.0: # %entry631; PWR7-LE-NEXT: li 4, 0632; PWR7-LE-NEXT: lwz 3, 0(3)633; PWR7-LE-NEXT: stw 4, -32(1)634; PWR7-LE-NEXT: addis 4, 2, .LCPI13_0@toc@ha635; PWR7-LE-NEXT: addi 4, 4, .LCPI13_0@toc@l636; PWR7-LE-NEXT: stw 3, -16(1)637; PWR7-LE-NEXT: addi 3, 1, -16638; PWR7-LE-NEXT: lxvd2x 0, 0, 4639; PWR7-LE-NEXT: addi 4, 1, -32640; PWR7-LE-NEXT: lxvd2x 1, 0, 4641; PWR7-LE-NEXT: xxswapd 34, 0642; PWR7-LE-NEXT: lxvd2x 0, 0, 3643; PWR7-LE-NEXT: xxswapd 35, 1644; PWR7-LE-NEXT: xxswapd 36, 0645; PWR7-LE-NEXT: vperm 2, 4, 3, 2646; PWR7-LE-NEXT: blr647;648; PWR8-LE-LABEL: build_v4f32_load_1:649; PWR8-LE: # %bb.0: # %entry650; PWR8-LE-NEXT: lfs 0, 0(3)651; PWR8-LE-NEXT: xxlxor 1, 1, 1652; PWR8-LE-NEXT: xxmrghd 0, 1, 0653; PWR8-LE-NEXT: xxspltd 1, 1, 0654; PWR8-LE-NEXT: xvcvdpsp 34, 0655; PWR8-LE-NEXT: xvcvdpsp 35, 1656; PWR8-LE-NEXT: vmrgew 2, 2, 3657; PWR8-LE-NEXT: blr658entry:659 %0 = load float, ptr %p, align 4660 %vecinit1 = insertelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %0, i32 1661 ret <4 x float> %vecinit1662}663 664define <4 x float> @build_v4f32_load_2(ptr nocapture noundef readonly %p) {665; PWR7-BE-LABEL: build_v4f32_load_2:666; PWR7-BE: # %bb.0: # %entry667; PWR7-BE-NEXT: lwz 3, 0(3)668; PWR7-BE-NEXT: li 4, 0669; PWR7-BE-NEXT: stw 4, -32(1)670; PWR7-BE-NEXT: stw 3, -16(1)671; PWR7-BE-NEXT: addis 3, 2, .LCPI14_0@toc@ha672; PWR7-BE-NEXT: addi 3, 3, .LCPI14_0@toc@l673; PWR7-BE-NEXT: lxvw4x 34, 0, 3674; PWR7-BE-NEXT: addi 3, 1, -32675; PWR7-BE-NEXT: lxvw4x 35, 0, 3676; PWR7-BE-NEXT: addi 3, 1, -16677; PWR7-BE-NEXT: lxvw4x 36, 0, 3678; PWR7-BE-NEXT: vperm 2, 3, 4, 2679; PWR7-BE-NEXT: blr680;681; PWR8-BE-LABEL: build_v4f32_load_2:682; PWR8-BE: # %bb.0: # %entry683; PWR8-BE-NEXT: lfs 0, 0(3)684; PWR8-BE-NEXT: xxlxor 1, 1, 1685; PWR8-BE-NEXT: xxmrghd 0, 1, 0686; PWR8-BE-NEXT: xxspltd 1, 1, 0687; PWR8-BE-NEXT: xvcvdpsp 34, 0688; PWR8-BE-NEXT: xvcvdpsp 35, 1689; PWR8-BE-NEXT: vmrgew 2, 2, 3690; PWR8-BE-NEXT: blr691;692; PWR7-LE-LABEL: build_v4f32_load_2:693; PWR7-LE: # %bb.0: # %entry694; PWR7-LE-NEXT: li 4, 0695; PWR7-LE-NEXT: lwz 3, 0(3)696; PWR7-LE-NEXT: stw 4, -32(1)697; PWR7-LE-NEXT: addis 4, 2, .LCPI14_0@toc@ha698; PWR7-LE-NEXT: addi 4, 4, .LCPI14_0@toc@l699; PWR7-LE-NEXT: stw 3, -16(1)700; PWR7-LE-NEXT: addi 3, 1, -16701; PWR7-LE-NEXT: lxvd2x 0, 0, 4702; PWR7-LE-NEXT: addi 4, 1, -32703; PWR7-LE-NEXT: lxvd2x 1, 0, 4704; PWR7-LE-NEXT: xxswapd 34, 0705; PWR7-LE-NEXT: lxvd2x 0, 0, 3706; PWR7-LE-NEXT: xxswapd 35, 1707; PWR7-LE-NEXT: xxswapd 36, 0708; PWR7-LE-NEXT: vperm 2, 4, 3, 2709; PWR7-LE-NEXT: blr710;711; PWR8-LE-LABEL: build_v4f32_load_2:712; PWR8-LE: # %bb.0: # %entry713; PWR8-LE-NEXT: lfs 0, 0(3)714; PWR8-LE-NEXT: xxlxor 1, 1, 1715; PWR8-LE-NEXT: xxmrghd 0, 0, 1716; PWR8-LE-NEXT: xxspltd 1, 1, 0717; PWR8-LE-NEXT: xvcvdpsp 34, 0718; PWR8-LE-NEXT: xvcvdpsp 35, 1719; PWR8-LE-NEXT: vmrgew 2, 3, 2720; PWR8-LE-NEXT: blr721entry:722 %0 = load float, ptr %p, align 4723 %vecinit1 = insertelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %0, i32 2724 ret <4 x float> %vecinit1725}726 727define <4 x float> @build_v4f32_load_3(ptr nocapture noundef readonly %p) {728; PWR7-BE-LABEL: build_v4f32_load_3:729; PWR7-BE: # %bb.0: # %entry730; PWR7-BE-NEXT: lwz 3, 0(3)731; PWR7-BE-NEXT: li 4, 0732; PWR7-BE-NEXT: stw 4, -32(1)733; PWR7-BE-NEXT: stw 3, -16(1)734; PWR7-BE-NEXT: addis 3, 2, .LCPI15_0@toc@ha735; PWR7-BE-NEXT: addi 3, 3, .LCPI15_0@toc@l736; PWR7-BE-NEXT: lxvw4x 34, 0, 3737; PWR7-BE-NEXT: addi 3, 1, -32738; PWR7-BE-NEXT: lxvw4x 35, 0, 3739; PWR7-BE-NEXT: addi 3, 1, -16740; PWR7-BE-NEXT: lxvw4x 36, 0, 3741; PWR7-BE-NEXT: vperm 2, 3, 4, 2742; PWR7-BE-NEXT: blr743;744; PWR8-BE-LABEL: build_v4f32_load_3:745; PWR8-BE: # %bb.0: # %entry746; PWR8-BE-NEXT: lfs 0, 0(3)747; PWR8-BE-NEXT: xxlxor 1, 1, 1748; PWR8-BE-NEXT: xxmrghd 0, 1, 0749; PWR8-BE-NEXT: xxspltd 1, 1, 0750; PWR8-BE-NEXT: xvcvdpsp 34, 0751; PWR8-BE-NEXT: xvcvdpsp 35, 1752; PWR8-BE-NEXT: vmrgew 2, 3, 2753; PWR8-BE-NEXT: blr754;755; PWR7-LE-LABEL: build_v4f32_load_3:756; PWR7-LE: # %bb.0: # %entry757; PWR7-LE-NEXT: li 4, 0758; PWR7-LE-NEXT: lwz 3, 0(3)759; PWR7-LE-NEXT: stw 4, -32(1)760; PWR7-LE-NEXT: addis 4, 2, .LCPI15_0@toc@ha761; PWR7-LE-NEXT: addi 4, 4, .LCPI15_0@toc@l762; PWR7-LE-NEXT: stw 3, -16(1)763; PWR7-LE-NEXT: addi 3, 1, -16764; PWR7-LE-NEXT: lxvd2x 0, 0, 4765; PWR7-LE-NEXT: addi 4, 1, -32766; PWR7-LE-NEXT: lxvd2x 1, 0, 4767; PWR7-LE-NEXT: xxswapd 34, 0768; PWR7-LE-NEXT: lxvd2x 0, 0, 3769; PWR7-LE-NEXT: xxswapd 35, 1770; PWR7-LE-NEXT: xxswapd 36, 0771; PWR7-LE-NEXT: vperm 2, 4, 3, 2772; PWR7-LE-NEXT: blr773;774; PWR8-LE-LABEL: build_v4f32_load_3:775; PWR8-LE: # %bb.0: # %entry776; PWR8-LE-NEXT: lfs 0, 0(3)777; PWR8-LE-NEXT: xxlxor 1, 1, 1778; PWR8-LE-NEXT: xxmrghd 0, 0, 1779; PWR8-LE-NEXT: xxspltd 1, 1, 0780; PWR8-LE-NEXT: xvcvdpsp 34, 0781; PWR8-LE-NEXT: xvcvdpsp 35, 1782; PWR8-LE-NEXT: vmrgew 2, 2, 3783; PWR8-LE-NEXT: blr784entry:785 %0 = load float, ptr %p, align 4786 %vecinit1 = insertelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %0, i32 3787 ret <4 x float> %vecinit1788}789