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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \3; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \4; RUN: -check-prefix=P9BE -implicit-check-not frsp5; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \6; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \7; RUN: -check-prefix=P9LE -implicit-check-not frsp8; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \9; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \10; RUN: -check-prefix=P8BE -implicit-check-not frsp11; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \12; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \13; RUN: -check-prefix=P8LE -implicit-check-not frsp14 15; This test case comes from the following C test case (included as it may be16; slightly more readable than the LLVM IR.17 18;/* This test case provides various ways of building vectors to ensure we19; produce optimal code for all cases. The cases are (for each type):20; - All zeros21; - All ones - split to build-vector-allones.ll22; - Splat of a constant23; - From different values already in registers24; - From different constants25; - From different values in memory26; - Splat of a value in register27; - Splat of a value in memory28; - Inserting element into existing vector29; - Inserting element from existing vector into existing vector30;31; With conversions (float <-> int)32; - Splat of a constant33; - From different values already in registers34; - From different constants35; - From different values in memory36; - Splat of a value in register37; - Splat of a value in memory38; - Inserting element into existing vector39; - Inserting element from existing vector into existing vector40;*/41;42;/*=================================== int ===================================*/43;// P8: xxlxor //44;// P9: xxlxor //45;vector int allZeroi() { //46; return (vector int)0; //47;} //48;// P8: vspltisb -1 //49;// P9: xxspltisb 255 //50;vector int spltConst1i() { //51; return (vector int)1; //52;} //53;// P8: vspltisw -15; vsrw //54;// P9: vspltisw -15; vsrw //55;vector int spltConst16ki() { //56; return (vector int)((1<<15) - 1); //57;} //58;// P8: vspltisw -16; vsrw //59;// P9: vspltisw -16; vsrw //60;vector int spltConst32ki() { //61; return (vector int)((1<<16) - 1); //62;} //63;// P8: 4 x mtvsrwz, 2 x xxmrgh, vmrgow //64;// P9: 2 x mtvsrdd, vmrgow //65;vector int fromRegsi(int a, int b, int c, int d) { //66; return (vector int){ a, b, c, d }; //67;} //68;// P8: lxvd2x, xxswapd //69;// P9: lxvx (or even lxv) //70;vector int fromDiffConstsi() { //71; return (vector int) { 242, -113, 889, 19 }; //72;} //73;// P8: lxvd2x, xxswapd //74;// P9: lxvx //75;vector int fromDiffMemConsAi(int *arr) { //76; return (vector int) { arr[0], arr[1], arr[2], arr[3] }; //77;} //78;// P8: 2 x lxvd2x, 2 x xxswapd, vperm //79;// P9: 2 x lxvx, vperm //80;vector int fromDiffMemConsDi(int *arr) { //81; return (vector int) { arr[3], arr[2], arr[1], arr[0] }; //82;} //83;// P8: sldi 2, lxvd2x, xxswapd //84;// P9: sldi 2, lxvx //85;vector int fromDiffMemVarAi(int *arr, int elem) { //86; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; //87;} //88;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm //89;// P9: sldi 2, 2 x lxvx, vperm //90;vector int fromDiffMemVarDi(int *arr, int elem) { //91; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; //92;} //93;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow //94;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow //95;vector int fromRandMemConsi(int *arr) { //96; return (vector int) { arr[4], arr[18], arr[2], arr[88] }; //97;} //98;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow //99;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow //100;vector int fromRandMemVari(int *arr, int elem) { //101; return (vector int) { arr[elem+4], arr[elem+1], arr[elem+2], arr[elem+8] };//102;} //103;// P8: mtvsrwz, xxspltw //104;// P9: mtvsrws //105;vector int spltRegVali(int val) { //106; return (vector int) val; //107;} //108;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw //109;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw //110;vector int spltMemVali(int *ptr) { //111; return (vector int)*ptr; //112;} //113;// P8: vspltisw //114;// P9: vspltisw //115;vector int spltCnstConvftoi() { //116; return (vector int) 4.74f; //117;} //118;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //119;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //120;vector int fromRegsConvftoi(float a, float b, float c, float d) { //121; return (vector int) { a, b, c, d }; //122;} //123;// P8: lxvd2x, xxswapd //124;// P9: lxvx (even lxv) //125;vector int fromDiffConstsConvftoi() { //126; return (vector int) { 24.46f, 234.f, 988.19f, 422.39f }; //127;} //128;// P8: lxvd2x, xxswapd, xvcvspsxws //129;// P9: lxvx, xvcvspsxws //130;vector int fromDiffMemConsAConvftoi(ptr ptr) { //131; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; //132;} //133;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspsxws //134;// P9: 2 x lxvx, vperm, xvcvspsxws //135;vector int fromDiffMemConsDConvftoi(ptr ptr) { //136; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; //137;} //138;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //139;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //140;// Note: if the consecutive loads learns to handle pre-inc, this can be: //141;// sldi 2, load, xvcvspuxws //142;vector int fromDiffMemVarAConvftoi(ptr arr, int elem) { //143; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; //144;} //145;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //146;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //147;// Note: if the consecutive loads learns to handle pre-inc, this can be: //148;// sldi 2, 2 x load, vperm, xvcvspuxws //149;vector int fromDiffMemVarDConvftoi(ptr arr, int elem) { //150; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; //151;} //152;// P8: xscvdpsxws, xxspltw //153;// P9: xscvdpsxws, xxspltw //154;vector int spltRegValConvftoi(float val) { //155; return (vector int) val; //156;} //157;// P8: lxsspx, xscvdpsxws, xxspltw //158;// P9: lxvwsx, xvcvspsxws //159;vector int spltMemValConvftoi(ptr ptr) { //160; return (vector int)*ptr; //161;} //162;// P8: vspltisw //163;// P9: vspltisw //164;vector int spltCnstConvdtoi() { //165; return (vector int) 4.74; //166;} //167;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //168;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //169;vector int fromRegsConvdtoi(double a, double b, double c, double d) { //170; return (vector int) { a, b, c, d }; //171;} //172;// P8: lxvd2x, xxswapd //173;// P9: lxvx (even lxv) //174;vector int fromDiffConstsConvdtoi() { //175; return (vector int) { 24.46, 234., 988.19, 422.39 }; //176;} //177;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew //178;// P9: 2 x lxvx, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew //179;vector int fromDiffMemConsAConvdtoi(ptr ptr) { //180; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; //181;} //182;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //183;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //184;vector int fromDiffMemConsDConvdtoi(ptr ptr) { //185; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; //186;} //187;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //188;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //189;vector int fromDiffMemVarAConvdtoi(ptr arr, int elem) { //190; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; //191;} //192;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //193;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //194;vector int fromDiffMemVarDConvdtoi(ptr arr, int elem) { //195; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; //196;} //197;// P8: xscvdpsxws, xxspltw //198;// P9: xscvdpsxws, xxspltw //199;vector int spltRegValConvdtoi(double val) { //200; return (vector int) val; //201;} //202;// P8: lxsdx, xscvdpsxws, xxspltw //203;// P9: lxssp, xscvdpsxws, xxspltw //204;vector int spltMemValConvdtoi(ptr ptr) { //205; return (vector int)*ptr; //206;} //207;/*=================================== int ===================================*/208;/*=============================== unsigned int ==============================*/209;// P8: xxlxor //210;// P9: xxlxor //211;vector unsigned int allZeroui() { //212; return (vector unsigned int)0; //213;} //214;// P8: vspltisb -1 //215;// P9: xxspltisb 255 //216;vector unsigned int spltConst1ui() { //217; return (vector unsigned int)1; //218;} //219;// P8: vspltisw -15; vsrw //220;// P9: vspltisw -15; vsrw //221;vector unsigned int spltConst16kui() { //222; return (vector unsigned int)((1<<15) - 1); //223;} //224;// P8: vspltisw -16; vsrw //225;// P9: vspltisw -16; vsrw //226;vector unsigned int spltConst32kui() { //227; return (vector unsigned int)((1<<16) - 1); //228;} //229;// P8: 4 x mtvsrwz, 2 x xxmrghd, vmrgow //230;// P9: 2 x mtvsrdd, vmrgow //231;vector unsigned int fromRegsui(unsigned int a, unsigned int b, //232; unsigned int c, unsigned int d) { //233; return (vector unsigned int){ a, b, c, d }; //234;} //235;// P8: lxvd2x, xxswapd //236;// P9: lxvx (or even lxv) //237;vector unsigned int fromDiffConstsui() { //238; return (vector unsigned int) { 242, -113, 889, 19 }; //239;} //240;// P8: lxvd2x, xxswapd //241;// P9: lxvx //242;vector unsigned int fromDiffMemConsAui(unsigned int *arr) { //243; return (vector unsigned int) { arr[0], arr[1], arr[2], arr[3] }; //244;} //245;// P8: 2 x lxvd2x, 2 x xxswapd, vperm //246;// P9: 2 x lxvx, vperm //247;vector unsigned int fromDiffMemConsDui(unsigned int *arr) { //248; return (vector unsigned int) { arr[3], arr[2], arr[1], arr[0] }; //249;} //250;// P8: sldi 2, lxvd2x, xxswapd //251;// P9: sldi 2, lxvx //252;vector unsigned int fromDiffMemVarAui(unsigned int *arr, int elem) { //253; return (vector unsigned int) { arr[elem], arr[elem+1], //254; arr[elem+2], arr[elem+3] }; //255;} //256;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm //257;// P9: sldi 2, 2 x lxvx, vperm //258;vector unsigned int fromDiffMemVarDui(unsigned int *arr, int elem) { //259; return (vector unsigned int) { arr[elem], arr[elem-1], //260; arr[elem-2], arr[elem-3] }; //261;} //262;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow //263;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow //264;vector unsigned int fromRandMemConsui(unsigned int *arr) { //265; return (vector unsigned int) { arr[4], arr[18], arr[2], arr[88] }; //266;} //267;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow //268;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow //269;vector unsigned int fromRandMemVarui(unsigned int *arr, int elem) { //270; return (vector unsigned int) { arr[elem+4], arr[elem+1], //271; arr[elem+2], arr[elem+8] }; //272;} //273;// P8: mtvsrwz, xxspltw //274;// P9: mtvsrws //275;vector unsigned int spltRegValui(unsigned int val) { //276; return (vector unsigned int) val; //277;} //278;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw //279;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw //280;vector unsigned int spltMemValui(unsigned int *ptr) { //281; return (vector unsigned int)*ptr; //282;} //283;// P8: vspltisw //284;// P9: vspltisw //285;vector unsigned int spltCnstConvftoui() { //286; return (vector unsigned int) 4.74f; //287;} //288;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //289;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //290;vector unsigned int fromRegsConvftoui(float a, float b, float c, float d) { //291; return (vector unsigned int) { a, b, c, d }; //292;} //293;// P8: lxvd2x, xxswapd //294;// P9: lxvx (even lxv) //295;vector unsigned int fromDiffConstsConvftoui() { //296; return (vector unsigned int) { 24.46f, 234.f, 988.19f, 422.39f }; //297;} //298;// P8: lxvd2x, xxswapd, xvcvspuxws //299;// P9: lxvx, xvcvspuxws //300;vector unsigned int fromDiffMemConsAConvftoui(ptr ptr) { //301; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; //302;} //303;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspuxws //304;// P9: 2 x lxvx, vperm, xvcvspuxws //305;vector unsigned int fromDiffMemConsDConvftoui(ptr ptr) { //306; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; //307;} //308;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //309;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //310;// Note: if the consecutive loads learns to handle pre-inc, this can be: //311;// sldi 2, load, xvcvspuxws //312;vector unsigned int fromDiffMemVarAConvftoui(ptr arr, int elem) { //313; return (vector unsigned int) { arr[elem], arr[elem+1], //314; arr[elem+2], arr[elem+3] }; //315;} //316;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //317;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //318;// Note: if the consecutive loads learns to handle pre-inc, this can be: //319;// sldi 2, 2 x load, vperm, xvcvspuxws //320;vector unsigned int fromDiffMemVarDConvftoui(ptr arr, int elem) { //321; return (vector unsigned int) { arr[elem], arr[elem-1], //322; arr[elem-2], arr[elem-3] }; //323;} //324;// P8: xscvdpuxws, xxspltw //325;// P9: xscvdpuxws, xxspltw //326;vector unsigned int spltRegValConvftoui(float val) { //327; return (vector unsigned int) val; //328;} //329;// P8: lxsspx, xscvdpuxws, xxspltw //330;// P9: lxvwsx, xvcvspuxws //331;vector unsigned int spltMemValConvftoui(ptr ptr) { //332; return (vector unsigned int)*ptr; //333;} //334;// P8: vspltisw //335;// P9: vspltisw //336;vector unsigned int spltCnstConvdtoui() { //337; return (vector unsigned int) 4.74; //338;} //339;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //340;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //341;vector unsigned int fromRegsConvdtoui(double a, double b, //342; double c, double d) { //343; return (vector unsigned int) { a, b, c, d }; //344;} //345;// P8: lxvd2x, xxswapd //346;// P9: lxvx (even lxv) //347;vector unsigned int fromDiffConstsConvdtoui() { //348; return (vector unsigned int) { 24.46, 234., 988.19, 422.39 }; //349;} //350;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew //351;// P9: 2 x lxvx, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew //352;vector unsigned int fromDiffMemConsAConvdtoui(ptr ptr) { //353; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; //354;} //355;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //356;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //357;vector unsigned int fromDiffMemConsDConvdtoui(ptr ptr) { //358; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; //359;} //360;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //361;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //362;vector unsigned int fromDiffMemVarAConvdtoui(ptr arr, int elem) { //363; return (vector unsigned int) { arr[elem], arr[elem+1], //364; arr[elem+2], arr[elem+3] }; //365;} //366;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //367;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //368;vector unsigned int fromDiffMemVarDConvdtoui(ptr arr, int elem) { //369; return (vector unsigned int) { arr[elem], arr[elem-1], //370; arr[elem-2], arr[elem-3] }; //371;} //372;// P8: xscvdpuxws, xxspltw //373;// P9: xscvdpuxws, xxspltw //374;vector unsigned int spltRegValConvdtoui(double val) { //375; return (vector unsigned int) val; //376;} //377;// P8: lxsspx, xscvdpuxws, xxspltw //378;// P9: lfd, xscvdpuxws, xxspltw //379;vector unsigned int spltMemValConvdtoui(ptr ptr) { //380; return (vector unsigned int)*ptr; //381;} //382;/*=============================== unsigned int ==============================*/383;/*=============================== long long =================================*/384;// P8: xxlxor //385;// P9: xxlxor //386;vector long long allZeroll() { //387; return (vector long long)0; //388;} //389;// P8: vspltisb -1 //390;// P9: xxspltisb 255 //391;vector long long spltConst1ll() { //392; return (vector long long)1; //393;} //394;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //395;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //396;vector long long spltConst16kll() { //397; return (vector long long)((1<<15) - 1); //398;} //399;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //400;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //401;vector long long spltConst32kll() { //402; return (vector long long)((1<<16) - 1); //403;} //404;// P8: 2 x mtvsrd, xxmrghd //405;// P9: mtvsrdd //406;vector long long fromRegsll(long long a, long long b) { //407; return (vector long long){ a, b }; //408;} //409;// P8: lxvd2x, xxswapd //410;// P9: lxvx (or even lxv) //411;vector long long fromDiffConstsll() { //412; return (vector long long) { 242, -113 }; //413;} //414;// P8: lxvd2x, xxswapd //415;// P9: lxvx //416;vector long long fromDiffMemConsAll(long long *arr) { //417; return (vector long long) { arr[0], arr[1] }; //418;} //419;// P8: lxvd2x //420;// P9: lxvx, xxswapd (maybe just use lxvd2x) //421;vector long long fromDiffMemConsDll(long long *arr) { //422; return (vector long long) { arr[3], arr[2] }; //423;} //424;// P8: sldi 3, lxvd2x, xxswapd //425;// P9: sldi 3, lxvx //426;vector long long fromDiffMemVarAll(long long *arr, int elem) { //427; return (vector long long) { arr[elem], arr[elem+1] }; //428;} //429;// P8: sldi 3, lxvd2x //430;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) //431;vector long long fromDiffMemVarDll(long long *arr, int elem) { //432; return (vector long long) { arr[elem], arr[elem-1] }; //433;} //434;// P8: 2 x ld, 2 x mtvsrd, xxmrghd //435;// P9: 2 x ld, mtvsrdd //436;vector long long fromRandMemConsll(long long *arr) { //437; return (vector long long) { arr[4], arr[18] }; //438;} //439;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd //440;// P9: sldi 3, add, 2 x ld, mtvsrdd //441;vector long long fromRandMemVarll(long long *arr, int elem) { //442; return (vector long long) { arr[elem+4], arr[elem+1] }; //443;} //444;// P8: mtvsrd, xxspltd //445;// P9: mtvsrdd //446;vector long long spltRegValll(long long val) { //447; return (vector long long) val; //448;} //449;// P8: lxvdsx //450;// P9: lxvdsx //451;vector long long spltMemValll(long long *ptr) { //452; return (vector long long)*ptr; //453;} //454;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //455;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //456;vector long long spltCnstConvftoll() { //457; return (vector long long) 4.74f; //458;} //459;// P8: xxmrghd, xvcvdpsxds //460;// P9: xxmrghd, xvcvdpsxds //461;vector long long fromRegsConvftoll(float a, float b) { //462; return (vector long long) { a, b }; //463;} //464;// P8: lxvd2x, xxswapd //465;// P9: lxvx (even lxv) //466;vector long long fromDiffConstsConvftoll() { //467; return (vector long long) { 24.46f, 234.f }; //468;} //469;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds //470;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds //471;vector long long fromDiffMemConsAConvftoll(ptr ptr) { //472; return (vector long long) { ptr[0], ptr[1] }; //473;} //474;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds //475;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds //476;vector long long fromDiffMemConsDConvftoll(ptr ptr) { //477; return (vector long long) { ptr[3], ptr[2] }; //478;} //479;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds //480;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds //481;vector long long fromDiffMemVarAConvftoll(ptr arr, int elem) { //482; return (vector long long) { arr[elem], arr[elem+1] }; //483;} //484;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds //485;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds //486;vector long long fromDiffMemVarDConvftoll(ptr arr, int elem) { //487; return (vector long long) { arr[elem], arr[elem-1] }; //488;} //489;// P8: xscvdpsxds, xxspltd //490;// P9: xscvdpsxds, xxspltd //491;vector long long spltRegValConvftoll(float val) { //492; return (vector long long) val; //493;} //494;// P8: lxsspx, xscvdpsxds, xxspltd //495;// P9: lfs, xscvdpsxds, xxspltd //496;vector long long spltMemValConvftoll(ptr ptr) { //497; return (vector long long)*ptr; //498;} //499;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //500;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //501;vector long long spltCnstConvdtoll() { //502; return (vector long long) 4.74; //503;} //504;// P8: xxmrghd, xvcvdpsxds //505;// P9: xxmrghd, xvcvdpsxds //506;vector long long fromRegsConvdtoll(double a, double b) { //507; return (vector long long) { a, b }; //508;} //509;// P8: lxvd2x, xxswapd //510;// P9: lxvx (even lxv) //511;vector long long fromDiffConstsConvdtoll() { //512; return (vector long long) { 24.46, 234. }; //513;} //514;// P8: lxvd2x, xxswapd, xvcvdpsxds //515;// P9: lxvx, xvcvdpsxds //516;vector long long fromDiffMemConsAConvdtoll(ptr ptr) { //517; return (vector long long) { ptr[0], ptr[1] }; //518;} //519;// P8: lxvd2x, xvcvdpsxds //520;// P9: lxvx, xxswapd, xvcvdpsxds //521;vector long long fromDiffMemConsDConvdtoll(ptr ptr) { //522; return (vector long long) { ptr[3], ptr[2] }; //523;} //524;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpsxds //525;// P9: sldi 3, lxvx, xvcvdpsxds //526;vector long long fromDiffMemVarAConvdtoll(ptr arr, int elem) { //527; return (vector long long) { arr[elem], arr[elem+1] }; //528;} //529;// P8: sldi 3, lxvd2x, xvcvdpsxds //530;// P9: sldi 3, lxvx, xxswapd, xvcvdpsxds //531;vector long long fromDiffMemVarDConvdtoll(ptr arr, int elem) { //532; return (vector long long) { arr[elem], arr[elem-1] }; //533;} //534;// P8: xscvdpsxds, xxspltd //535;// P9: xscvdpsxds, xxspltd //536;vector long long spltRegValConvdtoll(double val) { //537; return (vector long long) val; //538;} //539;// P8: lxvdsx, xvcvdpsxds //540;// P9: lxvdsx, xvcvdpsxds //541;vector long long spltMemValConvdtoll(ptr ptr) { //542; return (vector long long)*ptr; //543;} //544;/*=============================== long long =================================*/545;/*========================== unsigned long long =============================*/546;// P8: xxlxor //547;// P9: xxlxor //548;vector unsigned long long allZeroull() { //549; return (vector unsigned long long)0; //550;} //551;// P8: vspltisb -1 //552;// P9: xxspltisb 255 //553;vector unsigned long long spltConst1ull() { //554; return (vector unsigned long long)1; //555;} //556;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //557;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //558;vector unsigned long long spltConst16kull() { //559; return (vector unsigned long long)((1<<15) - 1); //560;} //561;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //562;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //563;vector unsigned long long spltConst32kull() { //564; return (vector unsigned long long)((1<<16) - 1); //565;} //566;// P8: 2 x mtvsrd, xxmrghd //567;// P9: mtvsrdd //568;vector unsigned long long fromRegsull(unsigned long long a, //569; unsigned long long b) { //570; return (vector unsigned long long){ a, b }; //571;} //572;// P8: lxvd2x, xxswapd //573;// P9: lxvx (or even lxv) //574;vector unsigned long long fromDiffConstsull() { //575; return (vector unsigned long long) { 242, -113 }; //576;} //577;// P8: lxvd2x, xxswapd //578;// P9: lxvx //579;vector unsigned long long fromDiffMemConsAull(unsigned long long *arr) { //580; return (vector unsigned long long) { arr[0], arr[1] }; //581;} //582;// P8: lxvd2x //583;// P9: lxvx, xxswapd (maybe just use lxvd2x) //584;vector unsigned long long fromDiffMemConsDull(unsigned long long *arr) { //585; return (vector unsigned long long) { arr[3], arr[2] }; //586;} //587;// P8: sldi 3, lxvd2x, xxswapd //588;// P9: sldi 3, lxvx //589;vector unsigned long long fromDiffMemVarAull(unsigned long long *arr, //590; int elem) { //591; return (vector unsigned long long) { arr[elem], arr[elem+1] }; //592;} //593;// P8: sldi 3, lxvd2x //594;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) //595;vector unsigned long long fromDiffMemVarDull(unsigned long long *arr, //596; int elem) { //597; return (vector unsigned long long) { arr[elem], arr[elem-1] }; //598;} //599;// P8: 2 x ld, 2 x mtvsrd, xxmrghd //600;// P9: 2 x ld, mtvsrdd //601;vector unsigned long long fromRandMemConsull(unsigned long long *arr) { //602; return (vector unsigned long long) { arr[4], arr[18] }; //603;} //604;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd //605;// P9: sldi 3, add, 2 x ld, mtvsrdd //606;vector unsigned long long fromRandMemVarull(unsigned long long *arr, //607; int elem) { //608; return (vector unsigned long long) { arr[elem+4], arr[elem+1] }; //609;} //610;// P8: mtvsrd, xxspltd //611;// P9: mtvsrdd //612;vector unsigned long long spltRegValull(unsigned long long val) { //613; return (vector unsigned long long) val; //614;} //615;// P8: lxvdsx //616;// P9: lxvdsx //617;vector unsigned long long spltMemValull(unsigned long long *ptr) { //618; return (vector unsigned long long)*ptr; //619;} //620;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //621;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //622;vector unsigned long long spltCnstConvftoull() { //623; return (vector unsigned long long) 4.74f; //624;} //625;// P8: xxmrghd, xvcvdpuxds //626;// P9: xxmrghd, xvcvdpuxds //627;vector unsigned long long fromRegsConvftoull(float a, float b) { //628; return (vector unsigned long long) { a, b }; //629;} //630;// P8: lxvd2x, xxswapd //631;// P9: lxvx (even lxv) //632;vector unsigned long long fromDiffConstsConvftoull() { //633; return (vector unsigned long long) { 24.46f, 234.f }; //634;} //635;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds //636;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds //637;vector unsigned long long fromDiffMemConsAConvftoull(ptr ptr) { //638; return (vector unsigned long long) { ptr[0], ptr[1] }; //639;} //640;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds //641;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds //642;vector unsigned long long fromDiffMemConsDConvftoull(ptr ptr) { //643; return (vector unsigned long long) { ptr[3], ptr[2] }; //644;} //645;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds //646;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds //647;vector unsigned long long fromDiffMemVarAConvftoull(ptr arr, int elem) { //648; return (vector unsigned long long) { arr[elem], arr[elem+1] }; //649;} //650;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds //651;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds //652;vector unsigned long long fromDiffMemVarDConvftoull(ptr arr, int elem) { //653; return (vector unsigned long long) { arr[elem], arr[elem-1] }; //654;} //655;// P8: xscvdpuxds, xxspltd //656;// P9: xscvdpuxds, xxspltd //657;vector unsigned long long spltRegValConvftoull(float val) { //658; return (vector unsigned long long) val; //659;} //660;// P8: lxsspx, xscvdpuxds, xxspltd //661;// P9: lfs, xscvdpuxds, xxspltd //662;vector unsigned long long spltMemValConvftoull(ptr ptr) { //663; return (vector unsigned long long)*ptr; //664;} //665;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //666;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //667;vector unsigned long long spltCnstConvdtoull() { //668; return (vector unsigned long long) 4.74; //669;} //670;// P8: xxmrghd, xvcvdpuxds //671;// P9: xxmrghd, xvcvdpuxds //672;vector unsigned long long fromRegsConvdtoull(double a, double b) { //673; return (vector unsigned long long) { a, b }; //674;} //675;// P8: lxvd2x, xxswapd //676;// P9: lxvx (even lxv) //677;vector unsigned long long fromDiffConstsConvdtoull() { //678; return (vector unsigned long long) { 24.46, 234. }; //679;} //680;// P8: lxvd2x, xxswapd, xvcvdpuxds //681;// P9: lxvx, xvcvdpuxds //682;vector unsigned long long fromDiffMemConsAConvdtoull(ptr ptr) { //683; return (vector unsigned long long) { ptr[0], ptr[1] }; //684;} //685;// P8: lxvd2x, xvcvdpuxds //686;// P9: lxvx, xxswapd, xvcvdpuxds //687;vector unsigned long long fromDiffMemConsDConvdtoull(ptr ptr) { //688; return (vector unsigned long long) { ptr[3], ptr[2] }; //689;} //690;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpuxds //691;// P9: sldi 3, lxvx, xvcvdpuxds //692;vector unsigned long long fromDiffMemVarAConvdtoull(ptr arr, int elem) { //693; return (vector unsigned long long) { arr[elem], arr[elem+1] }; //694;} //695;// P8: sldi 3, lxvd2x, xvcvdpuxds //696;// P9: sldi 3, lxvx, xxswapd, xvcvdpuxds //697;vector unsigned long long fromDiffMemVarDConvdtoull(ptr arr, int elem) { //698; return (vector unsigned long long) { arr[elem], arr[elem-1] }; //699;} //700;// P8: xscvdpuxds, xxspltd //701;// P9: xscvdpuxds, xxspltd //702;vector unsigned long long spltRegValConvdtoull(double val) { //703; return (vector unsigned long long) val; //704;} //705;// P8: lxvdsx, xvcvdpuxds //706;// P9: lxvdsx, xvcvdpuxds //707;vector unsigned long long spltMemValConvdtoull(ptr ptr) { //708; return (vector unsigned long long)*ptr; //709;} //710;/*========================== unsigned long long ==============================*/711 712define <4 x i32> @allZeroi() {713; P9BE-LABEL: allZeroi:714; P9BE: # %bb.0: # %entry715; P9BE-NEXT: xxlxor v2, v2, v2716; P9BE-NEXT: blr717;718; P9LE-LABEL: allZeroi:719; P9LE: # %bb.0: # %entry720; P9LE-NEXT: xxlxor v2, v2, v2721; P9LE-NEXT: blr722;723; P8BE-LABEL: allZeroi:724; P8BE: # %bb.0: # %entry725; P8BE-NEXT: xxlxor v2, v2, v2726; P8BE-NEXT: blr727;728; P8LE-LABEL: allZeroi:729; P8LE: # %bb.0: # %entry730; P8LE-NEXT: xxlxor v2, v2, v2731; P8LE-NEXT: blr732entry:733 ret <4 x i32> zeroinitializer734}735 736define <4 x i32> @spltConst1i() {737; P9BE-LABEL: spltConst1i:738; P9BE: # %bb.0: # %entry739; P9BE-NEXT: vspltisw v2, 1740; P9BE-NEXT: blr741;742; P9LE-LABEL: spltConst1i:743; P9LE: # %bb.0: # %entry744; P9LE-NEXT: vspltisw v2, 1745; P9LE-NEXT: blr746;747; P8BE-LABEL: spltConst1i:748; P8BE: # %bb.0: # %entry749; P8BE-NEXT: vspltisw v2, 1750; P8BE-NEXT: blr751;752; P8LE-LABEL: spltConst1i:753; P8LE: # %bb.0: # %entry754; P8LE-NEXT: vspltisw v2, 1755; P8LE-NEXT: blr756entry:757 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1>758}759 760define <4 x i32> @spltConst16ki() {761; P9BE-LABEL: spltConst16ki:762; P9BE: # %bb.0: # %entry763; P9BE-NEXT: vspltisw v2, -15764; P9BE-NEXT: vsrw v2, v2, v2765; P9BE-NEXT: blr766;767; P9LE-LABEL: spltConst16ki:768; P9LE: # %bb.0: # %entry769; P9LE-NEXT: vspltisw v2, -15770; P9LE-NEXT: vsrw v2, v2, v2771; P9LE-NEXT: blr772;773; P8BE-LABEL: spltConst16ki:774; P8BE: # %bb.0: # %entry775; P8BE-NEXT: vspltisw v2, -15776; P8BE-NEXT: vsrw v2, v2, v2777; P8BE-NEXT: blr778;779; P8LE-LABEL: spltConst16ki:780; P8LE: # %bb.0: # %entry781; P8LE-NEXT: vspltisw v2, -15782; P8LE-NEXT: vsrw v2, v2, v2783; P8LE-NEXT: blr784entry:785 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>786}787 788define <4 x i32> @spltConst32ki() {789; P9BE-LABEL: spltConst32ki:790; P9BE: # %bb.0: # %entry791; P9BE-NEXT: vspltisw v2, -16792; P9BE-NEXT: vsrw v2, v2, v2793; P9BE-NEXT: blr794;795; P9LE-LABEL: spltConst32ki:796; P9LE: # %bb.0: # %entry797; P9LE-NEXT: vspltisw v2, -16798; P9LE-NEXT: vsrw v2, v2, v2799; P9LE-NEXT: blr800;801; P8BE-LABEL: spltConst32ki:802; P8BE: # %bb.0: # %entry803; P8BE-NEXT: vspltisw v2, -16804; P8BE-NEXT: vsrw v2, v2, v2805; P8BE-NEXT: blr806;807; P8LE-LABEL: spltConst32ki:808; P8LE: # %bb.0: # %entry809; P8LE-NEXT: vspltisw v2, -16810; P8LE-NEXT: vsrw v2, v2, v2811; P8LE-NEXT: blr812entry:813 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>814}815 816define <4 x i32> @fromRegsi(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) {817; P9BE-LABEL: fromRegsi:818; P9BE: # %bb.0: # %entry819; P9BE-NEXT: rldimi r6, r5, 32, 0820; P9BE-NEXT: rldimi r4, r3, 32, 0821; P9BE-NEXT: mtvsrdd v2, r4, r6822; P9BE-NEXT: blr823;824; P9LE-LABEL: fromRegsi:825; P9LE: # %bb.0: # %entry826; P9LE-NEXT: rldimi r3, r4, 32, 0827; P9LE-NEXT: rldimi r5, r6, 32, 0828; P9LE-NEXT: mtvsrdd v2, r5, r3829; P9LE-NEXT: blr830;831; P8BE-LABEL: fromRegsi:832; P8BE: # %bb.0: # %entry833; P8BE-NEXT: rldimi r6, r5, 32, 0834; P8BE-NEXT: rldimi r4, r3, 32, 0835; P8BE-NEXT: mtfprd f0, r6836; P8BE-NEXT: mtfprd f1, r4837; P8BE-NEXT: xxmrghd v2, vs1, vs0838; P8BE-NEXT: blr839;840; P8LE-LABEL: fromRegsi:841; P8LE: # %bb.0: # %entry842; P8LE-NEXT: rldimi r3, r4, 32, 0843; P8LE-NEXT: rldimi r5, r6, 32, 0844; P8LE-NEXT: mtfprd f0, r3845; P8LE-NEXT: mtfprd f1, r5846; P8LE-NEXT: xxmrghd v2, vs1, vs0847; P8LE-NEXT: blr848entry:849 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0850 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1851 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2852 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3853 ret <4 x i32> %vecinit3854}855 856define <4 x i32> @fromDiffConstsi() {857; P9BE-LABEL: fromDiffConstsi:858; P9BE: # %bb.0: # %entry859; P9BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha860; P9BE-NEXT: addi r3, r3, .LCPI5_0@toc@l861; P9BE-NEXT: lxv v2, 0(r3)862; P9BE-NEXT: blr863;864; P9LE-LABEL: fromDiffConstsi:865; P9LE: # %bb.0: # %entry866; P9LE-NEXT: addis r3, r2, .LCPI5_0@toc@ha867; P9LE-NEXT: addi r3, r3, .LCPI5_0@toc@l868; P9LE-NEXT: lxv v2, 0(r3)869; P9LE-NEXT: blr870;871; P8BE-LABEL: fromDiffConstsi:872; P8BE: # %bb.0: # %entry873; P8BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha874; P8BE-NEXT: addi r3, r3, .LCPI5_0@toc@l875; P8BE-NEXT: lxvw4x v2, 0, r3876; P8BE-NEXT: blr877;878; P8LE-LABEL: fromDiffConstsi:879; P8LE: # %bb.0: # %entry880; P8LE-NEXT: addis r3, r2, .LCPI5_0@toc@ha881; P8LE-NEXT: addi r3, r3, .LCPI5_0@toc@l882; P8LE-NEXT: lxvd2x vs0, 0, r3883; P8LE-NEXT: xxswapd v2, vs0884; P8LE-NEXT: blr885entry:886 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19>887}888 889define <4 x i32> @fromDiffMemConsAi(ptr nocapture readonly %arr) {890; P9BE-LABEL: fromDiffMemConsAi:891; P9BE: # %bb.0: # %entry892; P9BE-NEXT: lxv v2, 0(r3)893; P9BE-NEXT: blr894;895; P9LE-LABEL: fromDiffMemConsAi:896; P9LE: # %bb.0: # %entry897; P9LE-NEXT: lxv v2, 0(r3)898; P9LE-NEXT: blr899;900; P8BE-LABEL: fromDiffMemConsAi:901; P8BE: # %bb.0: # %entry902; P8BE-NEXT: lxvw4x v2, 0, r3903; P8BE-NEXT: blr904;905; P8LE-LABEL: fromDiffMemConsAi:906; P8LE: # %bb.0: # %entry907; P8LE-NEXT: lxvd2x vs0, 0, r3908; P8LE-NEXT: xxswapd v2, vs0909; P8LE-NEXT: blr910entry:911 %0 = load i32, ptr %arr, align 4912 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0913 %arrayidx1 = getelementptr inbounds i32, ptr %arr, i64 1914 %1 = load i32, ptr %arrayidx1, align 4915 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1916 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 2917 %2 = load i32, ptr %arrayidx3, align 4918 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2919 %arrayidx5 = getelementptr inbounds i32, ptr %arr, i64 3920 %3 = load i32, ptr %arrayidx5, align 4921 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3922 ret <4 x i32> %vecinit6923}924 925define <4 x i32> @fromDiffMemConsDi(ptr nocapture readonly %arr) {926; P9BE-LABEL: fromDiffMemConsDi:927; P9BE: # %bb.0: # %entry928; P9BE-NEXT: lxv v2, 0(r3)929; P9BE-NEXT: addis r3, r2, .LCPI7_0@toc@ha930; P9BE-NEXT: addi r3, r3, .LCPI7_0@toc@l931; P9BE-NEXT: lxv vs0, 0(r3)932; P9BE-NEXT: xxperm v2, v2, vs0933; P9BE-NEXT: blr934;935; P9LE-LABEL: fromDiffMemConsDi:936; P9LE: # %bb.0: # %entry937; P9LE-NEXT: lxvw4x v2, 0, r3938; P9LE-NEXT: blr939;940; P8BE-LABEL: fromDiffMemConsDi:941; P8BE: # %bb.0: # %entry942; P8BE-NEXT: lxvw4x v2, 0, r3943; P8BE-NEXT: addis r3, r2, .LCPI7_0@toc@ha944; P8BE-NEXT: addi r3, r3, .LCPI7_0@toc@l945; P8BE-NEXT: lxvw4x v3, 0, r3946; P8BE-NEXT: vperm v2, v2, v2, v3947; P8BE-NEXT: blr948;949; P8LE-LABEL: fromDiffMemConsDi:950; P8LE: # %bb.0: # %entry951; P8LE-NEXT: lxvd2x vs0, 0, r3952; P8LE-NEXT: addis r3, r2, .LCPI7_0@toc@ha953; P8LE-NEXT: addi r3, r3, .LCPI7_0@toc@l954; P8LE-NEXT: xxswapd v2, vs0955; P8LE-NEXT: lxvd2x vs0, 0, r3956; P8LE-NEXT: xxswapd v3, vs0957; P8LE-NEXT: vperm v2, v2, v2, v3958; P8LE-NEXT: blr959entry:960 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 3961 %0 = load i32, ptr %arrayidx, align 4962 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0963 %arrayidx1 = getelementptr inbounds i32, ptr %arr, i64 2964 %1 = load i32, ptr %arrayidx1, align 4965 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1966 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 1967 %2 = load i32, ptr %arrayidx3, align 4968 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2969 %3 = load i32, ptr %arr, align 4970 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3971 ret <4 x i32> %vecinit6972}973 974define <4 x i32> @fromDiffMemVarAi(ptr nocapture readonly %arr, i32 signext %elem) {975; P9BE-LABEL: fromDiffMemVarAi:976; P9BE: # %bb.0: # %entry977; P9BE-NEXT: sldi r4, r4, 2978; P9BE-NEXT: lxvx v2, r3, r4979; P9BE-NEXT: blr980;981; P9LE-LABEL: fromDiffMemVarAi:982; P9LE: # %bb.0: # %entry983; P9LE-NEXT: sldi r4, r4, 2984; P9LE-NEXT: lxvx v2, r3, r4985; P9LE-NEXT: blr986;987; P8BE-LABEL: fromDiffMemVarAi:988; P8BE: # %bb.0: # %entry989; P8BE-NEXT: sldi r4, r4, 2990; P8BE-NEXT: lxvw4x v2, r3, r4991; P8BE-NEXT: blr992;993; P8LE-LABEL: fromDiffMemVarAi:994; P8LE: # %bb.0: # %entry995; P8LE-NEXT: sldi r4, r4, 2996; P8LE-NEXT: lxvd2x vs0, r3, r4997; P8LE-NEXT: xxswapd v2, vs0998; P8LE-NEXT: blr999entry:1000 %idxprom = sext i32 %elem to i641001 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 %idxprom1002 %0 = load i32, ptr %arrayidx, align 41003 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 01004 %add = add nsw i32 %elem, 11005 %idxprom1 = sext i32 %add to i641006 %arrayidx2 = getelementptr inbounds i32, ptr %arr, i64 %idxprom11007 %1 = load i32, ptr %arrayidx2, align 41008 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 11009 %add4 = add nsw i32 %elem, 21010 %idxprom5 = sext i32 %add4 to i641011 %arrayidx6 = getelementptr inbounds i32, ptr %arr, i64 %idxprom51012 %2 = load i32, ptr %arrayidx6, align 41013 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 21014 %add8 = add nsw i32 %elem, 31015 %idxprom9 = sext i32 %add8 to i641016 %arrayidx10 = getelementptr inbounds i32, ptr %arr, i64 %idxprom91017 %3 = load i32, ptr %arrayidx10, align 41018 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 31019 ret <4 x i32> %vecinit111020}1021 1022define <4 x i32> @fromDiffMemVarDi(ptr nocapture readonly %arr, i32 signext %elem) {1023; P9BE-LABEL: fromDiffMemVarDi:1024; P9BE: # %bb.0: # %entry1025; P9BE-NEXT: sldi r4, r4, 21026; P9BE-NEXT: add r3, r3, r41027; P9BE-NEXT: li r4, -121028; P9BE-NEXT: lxvx v2, r3, r41029; P9BE-NEXT: addis r3, r2, .LCPI9_0@toc@ha1030; P9BE-NEXT: addi r3, r3, .LCPI9_0@toc@l1031; P9BE-NEXT: lxv vs0, 0(r3)1032; P9BE-NEXT: xxperm v2, v2, vs01033; P9BE-NEXT: blr1034;1035; P9LE-LABEL: fromDiffMemVarDi:1036; P9LE: # %bb.0: # %entry1037; P9LE-NEXT: sldi r4, r4, 21038; P9LE-NEXT: add r3, r3, r41039; P9LE-NEXT: addi r3, r3, -121040; P9LE-NEXT: lxvw4x v2, 0, r31041; P9LE-NEXT: blr1042;1043; P8BE-LABEL: fromDiffMemVarDi:1044; P8BE: # %bb.0: # %entry1045; P8BE-NEXT: sldi r4, r4, 21046; P8BE-NEXT: add r3, r3, r41047; P8BE-NEXT: addi r3, r3, -121048; P8BE-NEXT: lxvw4x v2, 0, r31049; P8BE-NEXT: addis r3, r2, .LCPI9_0@toc@ha1050; P8BE-NEXT: addi r3, r3, .LCPI9_0@toc@l1051; P8BE-NEXT: lxvw4x v3, 0, r31052; P8BE-NEXT: vperm v2, v2, v2, v31053; P8BE-NEXT: blr1054;1055; P8LE-LABEL: fromDiffMemVarDi:1056; P8LE: # %bb.0: # %entry1057; P8LE-NEXT: sldi r4, r4, 21058; P8LE-NEXT: add r3, r3, r41059; P8LE-NEXT: addi r3, r3, -121060; P8LE-NEXT: lxvd2x vs0, 0, r31061; P8LE-NEXT: addis r3, r2, .LCPI9_0@toc@ha1062; P8LE-NEXT: addi r3, r3, .LCPI9_0@toc@l1063; P8LE-NEXT: xxswapd v2, vs01064; P8LE-NEXT: lxvd2x vs0, 0, r31065; P8LE-NEXT: xxswapd v3, vs01066; P8LE-NEXT: vperm v2, v2, v2, v31067; P8LE-NEXT: blr1068entry:1069 %idxprom = sext i32 %elem to i641070 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 %idxprom1071 %0 = load i32, ptr %arrayidx, align 41072 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 01073 %sub = add nsw i32 %elem, -11074 %idxprom1 = sext i32 %sub to i641075 %arrayidx2 = getelementptr inbounds i32, ptr %arr, i64 %idxprom11076 %1 = load i32, ptr %arrayidx2, align 41077 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 11078 %sub4 = add nsw i32 %elem, -21079 %idxprom5 = sext i32 %sub4 to i641080 %arrayidx6 = getelementptr inbounds i32, ptr %arr, i64 %idxprom51081 %2 = load i32, ptr %arrayidx6, align 41082 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 21083 %sub8 = add nsw i32 %elem, -31084 %idxprom9 = sext i32 %sub8 to i641085 %arrayidx10 = getelementptr inbounds i32, ptr %arr, i64 %idxprom91086 %3 = load i32, ptr %arrayidx10, align 41087 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 31088 ret <4 x i32> %vecinit111089}1090 1091define <4 x i32> @fromRandMemConsi(ptr nocapture readonly %arr) {1092; P9BE-LABEL: fromRandMemConsi:1093; P9BE: # %bb.0: # %entry1094; P9BE-NEXT: lwz r4, 16(r3)1095; P9BE-NEXT: lwz r5, 72(r3)1096; P9BE-NEXT: lwz r6, 8(r3)1097; P9BE-NEXT: lwz r3, 352(r3)1098; P9BE-NEXT: rldimi r3, r6, 32, 01099; P9BE-NEXT: rldimi r5, r4, 32, 01100; P9BE-NEXT: mtvsrdd v2, r5, r31101; P9BE-NEXT: blr1102;1103; P9LE-LABEL: fromRandMemConsi:1104; P9LE: # %bb.0: # %entry1105; P9LE-NEXT: lwz r4, 16(r3)1106; P9LE-NEXT: lwz r5, 72(r3)1107; P9LE-NEXT: lwz r6, 8(r3)1108; P9LE-NEXT: lwz r3, 352(r3)1109; P9LE-NEXT: rldimi r4, r5, 32, 01110; P9LE-NEXT: rldimi r6, r3, 32, 01111; P9LE-NEXT: mtvsrdd v2, r6, r41112; P9LE-NEXT: blr1113;1114; P8BE-LABEL: fromRandMemConsi:1115; P8BE: # %bb.0: # %entry1116; P8BE-NEXT: lwz r4, 16(r3)1117; P8BE-NEXT: lwz r5, 72(r3)1118; P8BE-NEXT: lwz r6, 8(r3)1119; P8BE-NEXT: lwz r3, 352(r3)1120; P8BE-NEXT: rldimi r3, r6, 32, 01121; P8BE-NEXT: rldimi r5, r4, 32, 01122; P8BE-NEXT: mtfprd f0, r31123; P8BE-NEXT: mtfprd f1, r51124; P8BE-NEXT: xxmrghd v2, vs1, vs01125; P8BE-NEXT: blr1126;1127; P8LE-LABEL: fromRandMemConsi:1128; P8LE: # %bb.0: # %entry1129; P8LE-NEXT: lwz r4, 16(r3)1130; P8LE-NEXT: lwz r5, 72(r3)1131; P8LE-NEXT: lwz r6, 8(r3)1132; P8LE-NEXT: lwz r3, 352(r3)1133; P8LE-NEXT: rldimi r4, r5, 32, 01134; P8LE-NEXT: rldimi r6, r3, 32, 01135; P8LE-NEXT: mtfprd f0, r41136; P8LE-NEXT: mtfprd f1, r61137; P8LE-NEXT: xxmrghd v2, vs1, vs01138; P8LE-NEXT: blr1139entry:1140 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 41141 %0 = load i32, ptr %arrayidx, align 41142 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 01143 %arrayidx1 = getelementptr inbounds i32, ptr %arr, i64 181144 %1 = load i32, ptr %arrayidx1, align 41145 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 11146 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 21147 %2 = load i32, ptr %arrayidx3, align 41148 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 21149 %arrayidx5 = getelementptr inbounds i32, ptr %arr, i64 881150 %3 = load i32, ptr %arrayidx5, align 41151 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 31152 ret <4 x i32> %vecinit61153}1154 1155define <4 x i32> @fromRandMemVari(ptr nocapture readonly %arr, i32 signext %elem) {1156; P9BE-LABEL: fromRandMemVari:1157; P9BE: # %bb.0: # %entry1158; P9BE-NEXT: sldi r4, r4, 21159; P9BE-NEXT: add r3, r3, r41160; P9BE-NEXT: lwz r4, 16(r3)1161; P9BE-NEXT: lwz r5, 4(r3)1162; P9BE-NEXT: lwz r6, 8(r3)1163; P9BE-NEXT: lwz r3, 32(r3)1164; P9BE-NEXT: rldimi r3, r6, 32, 01165; P9BE-NEXT: rldimi r5, r4, 32, 01166; P9BE-NEXT: mtvsrdd v2, r5, r31167; P9BE-NEXT: blr1168;1169; P9LE-LABEL: fromRandMemVari:1170; P9LE: # %bb.0: # %entry1171; P9LE-NEXT: sldi r4, r4, 21172; P9LE-NEXT: add r3, r3, r41173; P9LE-NEXT: lwz r4, 16(r3)1174; P9LE-NEXT: lwz r5, 4(r3)1175; P9LE-NEXT: lwz r6, 8(r3)1176; P9LE-NEXT: lwz r3, 32(r3)1177; P9LE-NEXT: rldimi r4, r5, 32, 01178; P9LE-NEXT: rldimi r6, r3, 32, 01179; P9LE-NEXT: mtvsrdd v2, r6, r41180; P9LE-NEXT: blr1181;1182; P8BE-LABEL: fromRandMemVari:1183; P8BE: # %bb.0: # %entry1184; P8BE-NEXT: sldi r4, r4, 21185; P8BE-NEXT: add r3, r3, r41186; P8BE-NEXT: lwz r4, 16(r3)1187; P8BE-NEXT: lwz r5, 4(r3)1188; P8BE-NEXT: lwz r6, 8(r3)1189; P8BE-NEXT: lwz r3, 32(r3)1190; P8BE-NEXT: rldimi r3, r6, 32, 01191; P8BE-NEXT: rldimi r5, r4, 32, 01192; P8BE-NEXT: mtfprd f0, r31193; P8BE-NEXT: mtfprd f1, r51194; P8BE-NEXT: xxmrghd v2, vs1, vs01195; P8BE-NEXT: blr1196;1197; P8LE-LABEL: fromRandMemVari:1198; P8LE: # %bb.0: # %entry1199; P8LE-NEXT: sldi r4, r4, 21200; P8LE-NEXT: add r3, r3, r41201; P8LE-NEXT: lwz r4, 16(r3)1202; P8LE-NEXT: lwz r5, 4(r3)1203; P8LE-NEXT: lwz r6, 8(r3)1204; P8LE-NEXT: lwz r3, 32(r3)1205; P8LE-NEXT: rldimi r4, r5, 32, 01206; P8LE-NEXT: rldimi r6, r3, 32, 01207; P8LE-NEXT: mtfprd f0, r41208; P8LE-NEXT: mtfprd f1, r61209; P8LE-NEXT: xxmrghd v2, vs1, vs01210; P8LE-NEXT: blr1211entry:1212 %add = add nsw i32 %elem, 41213 %idxprom = sext i32 %add to i641214 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 %idxprom1215 %0 = load i32, ptr %arrayidx, align 41216 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 01217 %add1 = add nsw i32 %elem, 11218 %idxprom2 = sext i32 %add1 to i641219 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 %idxprom21220 %1 = load i32, ptr %arrayidx3, align 41221 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 11222 %add5 = add nsw i32 %elem, 21223 %idxprom6 = sext i32 %add5 to i641224 %arrayidx7 = getelementptr inbounds i32, ptr %arr, i64 %idxprom61225 %2 = load i32, ptr %arrayidx7, align 41226 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 21227 %add9 = add nsw i32 %elem, 81228 %idxprom10 = sext i32 %add9 to i641229 %arrayidx11 = getelementptr inbounds i32, ptr %arr, i64 %idxprom101230 %3 = load i32, ptr %arrayidx11, align 41231 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 31232 ret <4 x i32> %vecinit121233}1234 1235define <4 x i32> @spltRegVali(i32 signext %val) {1236; P9BE-LABEL: spltRegVali:1237; P9BE: # %bb.0: # %entry1238; P9BE-NEXT: mtvsrws v2, r31239; P9BE-NEXT: blr1240;1241; P9LE-LABEL: spltRegVali:1242; P9LE: # %bb.0: # %entry1243; P9LE-NEXT: mtvsrws v2, r31244; P9LE-NEXT: blr1245;1246; P8BE-LABEL: spltRegVali:1247; P8BE: # %bb.0: # %entry1248; P8BE-NEXT: mtfprwz f0, r31249; P8BE-NEXT: xxspltw v2, vs0, 11250; P8BE-NEXT: blr1251;1252; P8LE-LABEL: spltRegVali:1253; P8LE: # %bb.0: # %entry1254; P8LE-NEXT: mtfprwz f0, r31255; P8LE-NEXT: xxspltw v2, vs0, 11256; P8LE-NEXT: blr1257entry:1258 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 01259 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer1260 ret <4 x i32> %splat.splat1261}1262 1263define <4 x i32> @spltMemVali(ptr nocapture readonly %ptr) {1264; P9BE-LABEL: spltMemVali:1265; P9BE: # %bb.0: # %entry1266; P9BE-NEXT: lxvwsx v2, 0, r31267; P9BE-NEXT: blr1268;1269; P9LE-LABEL: spltMemVali:1270; P9LE: # %bb.0: # %entry1271; P9LE-NEXT: lxvwsx v2, 0, r31272; P9LE-NEXT: blr1273;1274; P8BE-LABEL: spltMemVali:1275; P8BE: # %bb.0: # %entry1276; P8BE-NEXT: lfiwzx f0, 0, r31277; P8BE-NEXT: xxspltw v2, vs0, 11278; P8BE-NEXT: blr1279;1280; P8LE-LABEL: spltMemVali:1281; P8LE: # %bb.0: # %entry1282; P8LE-NEXT: lfiwzx f0, 0, r31283; P8LE-NEXT: xxspltw v2, vs0, 11284; P8LE-NEXT: blr1285entry:1286 %0 = load i32, ptr %ptr, align 41287 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 01288 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer1289 ret <4 x i32> %splat.splat1290}1291 1292define <4 x i32> @spltCnstConvftoi() {1293; P9BE-LABEL: spltCnstConvftoi:1294; P9BE: # %bb.0: # %entry1295; P9BE-NEXT: vspltisw v2, 41296; P9BE-NEXT: blr1297;1298; P9LE-LABEL: spltCnstConvftoi:1299; P9LE: # %bb.0: # %entry1300; P9LE-NEXT: vspltisw v2, 41301; P9LE-NEXT: blr1302;1303; P8BE-LABEL: spltCnstConvftoi:1304; P8BE: # %bb.0: # %entry1305; P8BE-NEXT: vspltisw v2, 41306; P8BE-NEXT: blr1307;1308; P8LE-LABEL: spltCnstConvftoi:1309; P8LE: # %bb.0: # %entry1310; P8LE-NEXT: vspltisw v2, 41311; P8LE-NEXT: blr1312entry:1313 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4>1314}1315 1316define <4 x i32> @fromRegsConvftoi(float %a, float %b, float %c, float %d) {1317; P9BE-LABEL: fromRegsConvftoi:1318; P9BE: # %bb.0: # %entry1319; P9BE-NEXT: xxmrghd vs0, vs2, vs41320; P9BE-NEXT: xvcvdpsxws v2, vs01321; P9BE-NEXT: xxmrghd vs0, vs1, vs31322; P9BE-NEXT: xvcvdpsxws v3, vs01323; P9BE-NEXT: vmrgew v2, v3, v21324; P9BE-NEXT: blr1325;1326; P9LE-LABEL: fromRegsConvftoi:1327; P9LE: # %bb.0: # %entry1328; P9LE-NEXT: xxmrghd vs0, vs3, vs11329; P9LE-NEXT: xvcvdpsxws v2, vs01330; P9LE-NEXT: xxmrghd vs0, vs4, vs21331; P9LE-NEXT: xvcvdpsxws v3, vs01332; P9LE-NEXT: vmrgew v2, v3, v21333; P9LE-NEXT: blr1334;1335; P8BE-LABEL: fromRegsConvftoi:1336; P8BE: # %bb.0: # %entry1337; P8BE-NEXT: xxmrghd vs0, vs2, vs41338; P8BE-NEXT: xxmrghd vs1, vs1, vs31339; P8BE-NEXT: xvcvdpsxws v2, vs01340; P8BE-NEXT: xvcvdpsxws v3, vs11341; P8BE-NEXT: vmrgew v2, v3, v21342; P8BE-NEXT: blr1343;1344; P8LE-LABEL: fromRegsConvftoi:1345; P8LE: # %bb.0: # %entry1346; P8LE-NEXT: xxmrghd vs0, vs3, vs11347; P8LE-NEXT: xxmrghd vs1, vs4, vs21348; P8LE-NEXT: xvcvdpsxws v2, vs01349; P8LE-NEXT: xvcvdpsxws v3, vs11350; P8LE-NEXT: vmrgew v2, v3, v21351; P8LE-NEXT: blr1352entry:1353 %conv = fptosi float %a to i321354 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 01355 %conv1 = fptosi float %b to i321356 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 11357 %conv3 = fptosi float %c to i321358 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 21359 %conv5 = fptosi float %d to i321360 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 31361 ret <4 x i32> %vecinit61362}1363 1364define <4 x i32> @fromDiffConstsConvftoi() {1365; P9BE-LABEL: fromDiffConstsConvftoi:1366; P9BE: # %bb.0: # %entry1367; P9BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha1368; P9BE-NEXT: addi r3, r3, .LCPI16_0@toc@l1369; P9BE-NEXT: lxv v2, 0(r3)1370; P9BE-NEXT: blr1371;1372; P9LE-LABEL: fromDiffConstsConvftoi:1373; P9LE: # %bb.0: # %entry1374; P9LE-NEXT: addis r3, r2, .LCPI16_0@toc@ha1375; P9LE-NEXT: addi r3, r3, .LCPI16_0@toc@l1376; P9LE-NEXT: lxv v2, 0(r3)1377; P9LE-NEXT: blr1378;1379; P8BE-LABEL: fromDiffConstsConvftoi:1380; P8BE: # %bb.0: # %entry1381; P8BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha1382; P8BE-NEXT: addi r3, r3, .LCPI16_0@toc@l1383; P8BE-NEXT: lxvw4x v2, 0, r31384; P8BE-NEXT: blr1385;1386; P8LE-LABEL: fromDiffConstsConvftoi:1387; P8LE: # %bb.0: # %entry1388; P8LE-NEXT: addis r3, r2, .LCPI16_0@toc@ha1389; P8LE-NEXT: addi r3, r3, .LCPI16_0@toc@l1390; P8LE-NEXT: lxvd2x vs0, 0, r31391; P8LE-NEXT: xxswapd v2, vs01392; P8LE-NEXT: blr1393entry:1394 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>1395}1396 1397define <4 x i32> @fromDiffMemConsAConvftoi(ptr nocapture readonly %ptr) {1398; P9BE-LABEL: fromDiffMemConsAConvftoi:1399; P9BE: # %bb.0: # %entry1400; P9BE-NEXT: lxv vs0, 0(r3)1401; P9BE-NEXT: xvcvspsxws v2, vs01402; P9BE-NEXT: blr1403;1404; P9LE-LABEL: fromDiffMemConsAConvftoi:1405; P9LE: # %bb.0: # %entry1406; P9LE-NEXT: lxv vs0, 0(r3)1407; P9LE-NEXT: xvcvspsxws v2, vs01408; P9LE-NEXT: blr1409;1410; P8BE-LABEL: fromDiffMemConsAConvftoi:1411; P8BE: # %bb.0: # %entry1412; P8BE-NEXT: lxvw4x vs0, 0, r31413; P8BE-NEXT: xvcvspsxws v2, vs01414; P8BE-NEXT: blr1415;1416; P8LE-LABEL: fromDiffMemConsAConvftoi:1417; P8LE: # %bb.0: # %entry1418; P8LE-NEXT: lxvd2x vs0, 0, r31419; P8LE-NEXT: xxswapd v2, vs01420; P8LE-NEXT: xvcvspsxws v2, v21421; P8LE-NEXT: blr1422entry:1423 %0 = load <4 x float>, ptr %ptr, align 41424 %1 = fptosi <4 x float> %0 to <4 x i32>1425 ret <4 x i32> %11426}1427 1428define <4 x i32> @fromDiffMemConsDConvftoi(ptr nocapture readonly %ptr) {1429; P9BE-LABEL: fromDiffMemConsDConvftoi:1430; P9BE: # %bb.0: # %entry1431; P9BE-NEXT: lxv vs0, 0(r3)1432; P9BE-NEXT: addis r3, r2, .LCPI18_0@toc@ha1433; P9BE-NEXT: addi r3, r3, .LCPI18_0@toc@l1434; P9BE-NEXT: lxv vs1, 0(r3)1435; P9BE-NEXT: xxperm vs0, vs0, vs11436; P9BE-NEXT: xvcvspsxws v2, vs01437; P9BE-NEXT: blr1438;1439; P9LE-LABEL: fromDiffMemConsDConvftoi:1440; P9LE: # %bb.0: # %entry1441; P9LE-NEXT: lxv vs0, 0(r3)1442; P9LE-NEXT: addis r3, r2, .LCPI18_0@toc@ha1443; P9LE-NEXT: addi r3, r3, .LCPI18_0@toc@l1444; P9LE-NEXT: lxv vs1, 0(r3)1445; P9LE-NEXT: xxperm vs0, vs0, vs11446; P9LE-NEXT: xvcvspsxws v2, vs01447; P9LE-NEXT: blr1448;1449; P8BE-LABEL: fromDiffMemConsDConvftoi:1450; P8BE: # %bb.0: # %entry1451; P8BE-NEXT: lxvw4x v2, 0, r31452; P8BE-NEXT: addis r3, r2, .LCPI18_0@toc@ha1453; P8BE-NEXT: addi r3, r3, .LCPI18_0@toc@l1454; P8BE-NEXT: lxvw4x v3, 0, r31455; P8BE-NEXT: vperm v2, v2, v2, v31456; P8BE-NEXT: xvcvspsxws v2, v21457; P8BE-NEXT: blr1458;1459; P8LE-LABEL: fromDiffMemConsDConvftoi:1460; P8LE: # %bb.0: # %entry1461; P8LE-NEXT: addis r4, r2, .LCPI18_0@toc@ha1462; P8LE-NEXT: lxvd2x v3, 0, r31463; P8LE-NEXT: addi r4, r4, .LCPI18_0@toc@l1464; P8LE-NEXT: lxvd2x vs0, 0, r41465; P8LE-NEXT: xxswapd v2, vs01466; P8LE-NEXT: vperm v2, v3, v3, v21467; P8LE-NEXT: xvcvspsxws v2, v21468; P8LE-NEXT: blr1469entry:1470 %arrayidx = getelementptr inbounds float, ptr %ptr, i64 31471 %0 = load float, ptr %arrayidx, align 41472 %conv = fptosi float %0 to i321473 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 01474 %arrayidx1 = getelementptr inbounds float, ptr %ptr, i64 21475 %1 = load float, ptr %arrayidx1, align 41476 %conv2 = fptosi float %1 to i321477 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 11478 %arrayidx4 = getelementptr inbounds float, ptr %ptr, i64 11479 %2 = load float, ptr %arrayidx4, align 41480 %conv5 = fptosi float %2 to i321481 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 21482 %3 = load float, ptr %ptr, align 41483 %conv8 = fptosi float %3 to i321484 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 31485 ret <4 x i32> %vecinit91486}1487 1488define <4 x i32> @fromDiffMemVarAConvftoi(ptr nocapture readonly %arr, i32 signext %elem) {1489; P9BE-LABEL: fromDiffMemVarAConvftoi:1490; P9BE: # %bb.0: # %entry1491; P9BE-NEXT: sldi r4, r4, 21492; P9BE-NEXT: lfsux f0, r3, r41493; P9BE-NEXT: lfs f1, 12(r3)1494; P9BE-NEXT: lfs f2, 4(r3)1495; P9BE-NEXT: xxmrghd vs1, vs2, vs11496; P9BE-NEXT: xvcvdpsp v2, vs11497; P9BE-NEXT: lfs f1, 8(r3)1498; P9BE-NEXT: xxmrghd vs0, vs0, vs11499; P9BE-NEXT: xvcvdpsp v3, vs01500; P9BE-NEXT: vmrgew v2, v3, v21501; P9BE-NEXT: xvcvspsxws v2, v21502; P9BE-NEXT: blr1503;1504; P9LE-LABEL: fromDiffMemVarAConvftoi:1505; P9LE: # %bb.0: # %entry1506; P9LE-NEXT: sldi r4, r4, 21507; P9LE-NEXT: lfsux f0, r3, r41508; P9LE-NEXT: lfs f1, 8(r3)1509; P9LE-NEXT: xxmrghd vs0, vs1, vs01510; P9LE-NEXT: lfs f1, 12(r3)1511; P9LE-NEXT: xvcvdpsp v2, vs01512; P9LE-NEXT: lfs f0, 4(r3)1513; P9LE-NEXT: xxmrghd vs0, vs1, vs01514; P9LE-NEXT: xvcvdpsp v3, vs01515; P9LE-NEXT: vmrgew v2, v3, v21516; P9LE-NEXT: xvcvspsxws v2, v21517; P9LE-NEXT: blr1518;1519; P8BE-LABEL: fromDiffMemVarAConvftoi:1520; P8BE: # %bb.0: # %entry1521; P8BE-NEXT: sldi r4, r4, 21522; P8BE-NEXT: lfsux f0, r3, r41523; P8BE-NEXT: lfs f1, 12(r3)1524; P8BE-NEXT: lfs f2, 4(r3)1525; P8BE-NEXT: xxmrghd vs1, vs2, vs11526; P8BE-NEXT: lfs f2, 8(r3)1527; P8BE-NEXT: xvcvdpsp v2, vs11528; P8BE-NEXT: xxmrghd vs0, vs0, vs21529; P8BE-NEXT: xvcvdpsp v3, vs01530; P8BE-NEXT: vmrgew v2, v3, v21531; P8BE-NEXT: xvcvspsxws v2, v21532; P8BE-NEXT: blr1533;1534; P8LE-LABEL: fromDiffMemVarAConvftoi:1535; P8LE: # %bb.0: # %entry1536; P8LE-NEXT: sldi r4, r4, 21537; P8LE-NEXT: lfsux f0, r3, r41538; P8LE-NEXT: lfs f1, 8(r3)1539; P8LE-NEXT: xxmrghd vs0, vs1, vs01540; P8LE-NEXT: lfs f1, 4(r3)1541; P8LE-NEXT: lfs f2, 12(r3)1542; P8LE-NEXT: xvcvdpsp v2, vs01543; P8LE-NEXT: xxmrghd vs1, vs2, vs11544; P8LE-NEXT: xvcvdpsp v3, vs11545; P8LE-NEXT: vmrgew v2, v3, v21546; P8LE-NEXT: xvcvspsxws v2, v21547; P8LE-NEXT: blr1548entry:1549 %idxprom = sext i32 %elem to i641550 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom1551 %0 = load float, ptr %arrayidx, align 41552 %conv = fptosi float %0 to i321553 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 01554 %add = add nsw i32 %elem, 11555 %idxprom1 = sext i32 %add to i641556 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom11557 %1 = load float, ptr %arrayidx2, align 41558 %conv3 = fptosi float %1 to i321559 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 11560 %add5 = add nsw i32 %elem, 21561 %idxprom6 = sext i32 %add5 to i641562 %arrayidx7 = getelementptr inbounds float, ptr %arr, i64 %idxprom61563 %2 = load float, ptr %arrayidx7, align 41564 %conv8 = fptosi float %2 to i321565 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 21566 %add10 = add nsw i32 %elem, 31567 %idxprom11 = sext i32 %add10 to i641568 %arrayidx12 = getelementptr inbounds float, ptr %arr, i64 %idxprom111569 %3 = load float, ptr %arrayidx12, align 41570 %conv13 = fptosi float %3 to i321571 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 31572 ret <4 x i32> %vecinit141573}1574 1575define <4 x i32> @fromDiffMemVarDConvftoi(ptr nocapture readonly %arr, i32 signext %elem) {1576; P9BE-LABEL: fromDiffMemVarDConvftoi:1577; P9BE: # %bb.0: # %entry1578; P9BE-NEXT: sldi r4, r4, 21579; P9BE-NEXT: lfsux f0, r3, r41580; P9BE-NEXT: lfs f1, -12(r3)1581; P9BE-NEXT: lfs f2, -4(r3)1582; P9BE-NEXT: xxmrghd vs1, vs2, vs11583; P9BE-NEXT: xvcvdpsp v2, vs11584; P9BE-NEXT: lfs f1, -8(r3)1585; P9BE-NEXT: xxmrghd vs0, vs0, vs11586; P9BE-NEXT: xvcvdpsp v3, vs01587; P9BE-NEXT: vmrgew v2, v3, v21588; P9BE-NEXT: xvcvspsxws v2, v21589; P9BE-NEXT: blr1590;1591; P9LE-LABEL: fromDiffMemVarDConvftoi:1592; P9LE: # %bb.0: # %entry1593; P9LE-NEXT: sldi r4, r4, 21594; P9LE-NEXT: lfsux f0, r3, r41595; P9LE-NEXT: lfs f1, -8(r3)1596; P9LE-NEXT: xxmrghd vs0, vs1, vs01597; P9LE-NEXT: lfs f1, -12(r3)1598; P9LE-NEXT: xvcvdpsp v2, vs01599; P9LE-NEXT: lfs f0, -4(r3)1600; P9LE-NEXT: xxmrghd vs0, vs1, vs01601; P9LE-NEXT: xvcvdpsp v3, vs01602; P9LE-NEXT: vmrgew v2, v3, v21603; P9LE-NEXT: xvcvspsxws v2, v21604; P9LE-NEXT: blr1605;1606; P8BE-LABEL: fromDiffMemVarDConvftoi:1607; P8BE: # %bb.0: # %entry1608; P8BE-NEXT: sldi r4, r4, 21609; P8BE-NEXT: lfsux f0, r3, r41610; P8BE-NEXT: lfs f1, -12(r3)1611; P8BE-NEXT: lfs f2, -4(r3)1612; P8BE-NEXT: xxmrghd vs1, vs2, vs11613; P8BE-NEXT: lfs f2, -8(r3)1614; P8BE-NEXT: xvcvdpsp v2, vs11615; P8BE-NEXT: xxmrghd vs0, vs0, vs21616; P8BE-NEXT: xvcvdpsp v3, vs01617; P8BE-NEXT: vmrgew v2, v3, v21618; P8BE-NEXT: xvcvspsxws v2, v21619; P8BE-NEXT: blr1620;1621; P8LE-LABEL: fromDiffMemVarDConvftoi:1622; P8LE: # %bb.0: # %entry1623; P8LE-NEXT: sldi r4, r4, 21624; P8LE-NEXT: lfsux f0, r3, r41625; P8LE-NEXT: lfs f1, -8(r3)1626; P8LE-NEXT: xxmrghd vs0, vs1, vs01627; P8LE-NEXT: lfs f1, -4(r3)1628; P8LE-NEXT: lfs f2, -12(r3)1629; P8LE-NEXT: xvcvdpsp v2, vs01630; P8LE-NEXT: xxmrghd vs1, vs2, vs11631; P8LE-NEXT: xvcvdpsp v3, vs11632; P8LE-NEXT: vmrgew v2, v3, v21633; P8LE-NEXT: xvcvspsxws v2, v21634; P8LE-NEXT: blr1635entry:1636 %idxprom = sext i32 %elem to i641637 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom1638 %0 = load float, ptr %arrayidx, align 41639 %conv = fptosi float %0 to i321640 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 01641 %sub = add nsw i32 %elem, -11642 %idxprom1 = sext i32 %sub to i641643 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom11644 %1 = load float, ptr %arrayidx2, align 41645 %conv3 = fptosi float %1 to i321646 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 11647 %sub5 = add nsw i32 %elem, -21648 %idxprom6 = sext i32 %sub5 to i641649 %arrayidx7 = getelementptr inbounds float, ptr %arr, i64 %idxprom61650 %2 = load float, ptr %arrayidx7, align 41651 %conv8 = fptosi float %2 to i321652 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 21653 %sub10 = add nsw i32 %elem, -31654 %idxprom11 = sext i32 %sub10 to i641655 %arrayidx12 = getelementptr inbounds float, ptr %arr, i64 %idxprom111656 %3 = load float, ptr %arrayidx12, align 41657 %conv13 = fptosi float %3 to i321658 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 31659 ret <4 x i32> %vecinit141660; FIXME: implement finding consecutive loads with pre-inc1661}1662 1663define <4 x i32> @spltRegValConvftoi(float %val) {1664; P9BE-LABEL: spltRegValConvftoi:1665; P9BE: # %bb.0: # %entry1666; P9BE-NEXT: xscvdpsxws f0, f11667; P9BE-NEXT: xxspltw v2, vs0, 11668; P9BE-NEXT: blr1669;1670; P9LE-LABEL: spltRegValConvftoi:1671; P9LE: # %bb.0: # %entry1672; P9LE-NEXT: xscvdpsxws f0, f11673; P9LE-NEXT: xxspltw v2, vs0, 11674; P9LE-NEXT: blr1675;1676; P8BE-LABEL: spltRegValConvftoi:1677; P8BE: # %bb.0: # %entry1678; P8BE-NEXT: xscvdpsxws f0, f11679; P8BE-NEXT: xxspltw v2, vs0, 11680; P8BE-NEXT: blr1681;1682; P8LE-LABEL: spltRegValConvftoi:1683; P8LE: # %bb.0: # %entry1684; P8LE-NEXT: xscvdpsxws f0, f11685; P8LE-NEXT: xxspltw v2, vs0, 11686; P8LE-NEXT: blr1687entry:1688 %conv = fptosi float %val to i321689 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 01690 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer1691 ret <4 x i32> %splat.splat1692}1693 1694define <4 x i32> @spltMemValConvftoi(ptr nocapture readonly %ptr) {1695; P9BE-LABEL: spltMemValConvftoi:1696; P9BE: # %bb.0: # %entry1697; P9BE-NEXT: lfiwzx f0, 0, r31698; P9BE-NEXT: xvcvspsxws vs0, vs01699; P9BE-NEXT: xxspltw v2, vs0, 11700; P9BE-NEXT: blr1701;1702; P9LE-LABEL: spltMemValConvftoi:1703; P9LE: # %bb.0: # %entry1704; P9LE-NEXT: lfiwzx f0, 0, r31705; P9LE-NEXT: xvcvspsxws vs0, vs01706; P9LE-NEXT: xxspltw v2, vs0, 11707; P9LE-NEXT: blr1708;1709; P8BE-LABEL: spltMemValConvftoi:1710; P8BE: # %bb.0: # %entry1711; P8BE-NEXT: lfsx f0, 0, r31712; P8BE-NEXT: xscvdpsxws f0, f01713; P8BE-NEXT: xxspltw v2, vs0, 11714; P8BE-NEXT: blr1715;1716; P8LE-LABEL: spltMemValConvftoi:1717; P8LE: # %bb.0: # %entry1718; P8LE-NEXT: lfsx f0, 0, r31719; P8LE-NEXT: xscvdpsxws f0, f01720; P8LE-NEXT: xxspltw v2, vs0, 11721; P8LE-NEXT: blr1722entry:1723 %0 = load float, ptr %ptr, align 41724 %conv = fptosi float %0 to i321725 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 01726 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer1727 ret <4 x i32> %splat.splat1728}1729 1730define <4 x i32> @spltCnstConvdtoi() {1731; P9BE-LABEL: spltCnstConvdtoi:1732; P9BE: # %bb.0: # %entry1733; P9BE-NEXT: vspltisw v2, 41734; P9BE-NEXT: blr1735;1736; P9LE-LABEL: spltCnstConvdtoi:1737; P9LE: # %bb.0: # %entry1738; P9LE-NEXT: vspltisw v2, 41739; P9LE-NEXT: blr1740;1741; P8BE-LABEL: spltCnstConvdtoi:1742; P8BE: # %bb.0: # %entry1743; P8BE-NEXT: vspltisw v2, 41744; P8BE-NEXT: blr1745;1746; P8LE-LABEL: spltCnstConvdtoi:1747; P8LE: # %bb.0: # %entry1748; P8LE-NEXT: vspltisw v2, 41749; P8LE-NEXT: blr1750entry:1751 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4>1752}1753 1754define <4 x i32> @fromRegsConvdtoi(double %a, double %b, double %c, double %d) {1755; P9BE-LABEL: fromRegsConvdtoi:1756; P9BE: # %bb.0: # %entry1757; P9BE-NEXT: xxmrghd vs0, vs2, vs41758; P9BE-NEXT: xvcvdpsxws v2, vs01759; P9BE-NEXT: xxmrghd vs0, vs1, vs31760; P9BE-NEXT: xvcvdpsxws v3, vs01761; P9BE-NEXT: vmrgew v2, v3, v21762; P9BE-NEXT: blr1763;1764; P9LE-LABEL: fromRegsConvdtoi:1765; P9LE: # %bb.0: # %entry1766; P9LE-NEXT: xxmrghd vs0, vs3, vs11767; P9LE-NEXT: xvcvdpsxws v2, vs01768; P9LE-NEXT: xxmrghd vs0, vs4, vs21769; P9LE-NEXT: xvcvdpsxws v3, vs01770; P9LE-NEXT: vmrgew v2, v3, v21771; P9LE-NEXT: blr1772;1773; P8BE-LABEL: fromRegsConvdtoi:1774; P8BE: # %bb.0: # %entry1775; P8BE-NEXT: xxmrghd vs0, vs2, vs41776; P8BE-NEXT: xxmrghd vs1, vs1, vs31777; P8BE-NEXT: xvcvdpsxws v2, vs01778; P8BE-NEXT: xvcvdpsxws v3, vs11779; P8BE-NEXT: vmrgew v2, v3, v21780; P8BE-NEXT: blr1781;1782; P8LE-LABEL: fromRegsConvdtoi:1783; P8LE: # %bb.0: # %entry1784; P8LE-NEXT: xxmrghd vs0, vs3, vs11785; P8LE-NEXT: xxmrghd vs1, vs4, vs21786; P8LE-NEXT: xvcvdpsxws v2, vs01787; P8LE-NEXT: xvcvdpsxws v3, vs11788; P8LE-NEXT: vmrgew v2, v3, v21789; P8LE-NEXT: blr1790entry:1791 %conv = fptosi double %a to i321792 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 01793 %conv1 = fptosi double %b to i321794 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 11795 %conv3 = fptosi double %c to i321796 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 21797 %conv5 = fptosi double %d to i321798 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 31799 ret <4 x i32> %vecinit61800}1801 1802define <4 x i32> @fromDiffConstsConvdtoi() {1803; P9BE-LABEL: fromDiffConstsConvdtoi:1804; P9BE: # %bb.0: # %entry1805; P9BE-NEXT: addis r3, r2, .LCPI25_0@toc@ha1806; P9BE-NEXT: addi r3, r3, .LCPI25_0@toc@l1807; P9BE-NEXT: lxv v2, 0(r3)1808; P9BE-NEXT: blr1809;1810; P9LE-LABEL: fromDiffConstsConvdtoi:1811; P9LE: # %bb.0: # %entry1812; P9LE-NEXT: addis r3, r2, .LCPI25_0@toc@ha1813; P9LE-NEXT: addi r3, r3, .LCPI25_0@toc@l1814; P9LE-NEXT: lxv v2, 0(r3)1815; P9LE-NEXT: blr1816;1817; P8BE-LABEL: fromDiffConstsConvdtoi:1818; P8BE: # %bb.0: # %entry1819; P8BE-NEXT: addis r3, r2, .LCPI25_0@toc@ha1820; P8BE-NEXT: addi r3, r3, .LCPI25_0@toc@l1821; P8BE-NEXT: lxvw4x v2, 0, r31822; P8BE-NEXT: blr1823;1824; P8LE-LABEL: fromDiffConstsConvdtoi:1825; P8LE: # %bb.0: # %entry1826; P8LE-NEXT: addis r3, r2, .LCPI25_0@toc@ha1827; P8LE-NEXT: addi r3, r3, .LCPI25_0@toc@l1828; P8LE-NEXT: lxvd2x vs0, 0, r31829; P8LE-NEXT: xxswapd v2, vs01830; P8LE-NEXT: blr1831entry:1832 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>1833}1834 1835define <4 x i32> @fromDiffMemConsAConvdtoi(ptr nocapture readonly %ptr) {1836; P9BE-LABEL: fromDiffMemConsAConvdtoi:1837; P9BE: # %bb.0: # %entry1838; P9BE-NEXT: lxv vs0, 0(r3)1839; P9BE-NEXT: lxv vs1, 16(r3)1840; P9BE-NEXT: xxmrgld vs2, vs0, vs11841; P9BE-NEXT: xxmrghd vs0, vs0, vs11842; P9BE-NEXT: xvcvdpsxws v2, vs21843; P9BE-NEXT: xvcvdpsxws v3, vs01844; P9BE-NEXT: vmrgew v2, v3, v21845; P9BE-NEXT: blr1846;1847; P9LE-LABEL: fromDiffMemConsAConvdtoi:1848; P9LE: # %bb.0: # %entry1849; P9LE-NEXT: lxv vs0, 0(r3)1850; P9LE-NEXT: lxv vs1, 16(r3)1851; P9LE-NEXT: xxmrgld vs2, vs1, vs01852; P9LE-NEXT: xxmrghd vs0, vs1, vs01853; P9LE-NEXT: xvcvdpsxws v2, vs21854; P9LE-NEXT: xvcvdpsxws v3, vs01855; P9LE-NEXT: vmrgew v2, v3, v21856; P9LE-NEXT: blr1857;1858; P8BE-LABEL: fromDiffMemConsAConvdtoi:1859; P8BE: # %bb.0: # %entry1860; P8BE-NEXT: li r4, 161861; P8BE-NEXT: lxvd2x vs0, 0, r31862; P8BE-NEXT: lxvd2x vs1, r3, r41863; P8BE-NEXT: xxmrgld vs2, vs0, vs11864; P8BE-NEXT: xxmrghd vs0, vs0, vs11865; P8BE-NEXT: xvcvdpsxws v2, vs21866; P8BE-NEXT: xvcvdpsxws v3, vs01867; P8BE-NEXT: vmrgew v2, v3, v21868; P8BE-NEXT: blr1869;1870; P8LE-LABEL: fromDiffMemConsAConvdtoi:1871; P8LE: # %bb.0: # %entry1872; P8LE-NEXT: li r4, 161873; P8LE-NEXT: lxvd2x vs0, 0, r31874; P8LE-NEXT: lxvd2x vs1, r3, r41875; P8LE-NEXT: xxswapd vs0, vs01876; P8LE-NEXT: xxswapd vs1, vs11877; P8LE-NEXT: xxmrgld vs2, vs1, vs01878; P8LE-NEXT: xxmrghd vs0, vs1, vs01879; P8LE-NEXT: xvcvdpsxws v2, vs21880; P8LE-NEXT: xvcvdpsxws v3, vs01881; P8LE-NEXT: vmrgew v2, v3, v21882; P8LE-NEXT: blr1883entry:1884 %0 = load <2 x double>, ptr %ptr, align 81885 %1 = fptosi <2 x double> %0 to <2 x i32>1886 %arrayidx4 = getelementptr inbounds double, ptr %ptr, i64 21887 %2 = load <2 x double>, ptr %arrayidx4, align 81888 %3 = fptosi <2 x double> %2 to <2 x i32>1889 %vecinit9 = shufflevector <2 x i32> %1, <2 x i32> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1890 ret <4 x i32> %vecinit91891}1892 1893define <4 x i32> @fromDiffMemConsDConvdtoi(ptr nocapture readonly %ptr) {1894; P9BE-LABEL: fromDiffMemConsDConvdtoi:1895; P9BE: # %bb.0: # %entry1896; P9BE-NEXT: lfd f0, 24(r3)1897; P9BE-NEXT: lfd f1, 16(r3)1898; P9BE-NEXT: lfd f2, 8(r3)1899; P9BE-NEXT: xxmrghd vs0, vs0, vs21900; P9BE-NEXT: lfd f3, 0(r3)1901; P9BE-NEXT: xxmrghd vs1, vs1, vs31902; P9BE-NEXT: xvcvdpsxws v2, vs11903; P9BE-NEXT: xvcvdpsxws v3, vs01904; P9BE-NEXT: vmrgew v2, v3, v21905; P9BE-NEXT: blr1906;1907; P9LE-LABEL: fromDiffMemConsDConvdtoi:1908; P9LE: # %bb.0: # %entry1909; P9LE-NEXT: lfd f0, 24(r3)1910; P9LE-NEXT: lfd f2, 8(r3)1911; P9LE-NEXT: xxmrghd vs0, vs2, vs01912; P9LE-NEXT: lfd f1, 16(r3)1913; P9LE-NEXT: lfd f3, 0(r3)1914; P9LE-NEXT: xvcvdpsxws v2, vs01915; P9LE-NEXT: xxmrghd vs0, vs3, vs11916; P9LE-NEXT: xvcvdpsxws v3, vs01917; P9LE-NEXT: vmrgew v2, v3, v21918; P9LE-NEXT: blr1919;1920; P8BE-LABEL: fromDiffMemConsDConvdtoi:1921; P8BE: # %bb.0: # %entry1922; P8BE-NEXT: lfd f0, 24(r3)1923; P8BE-NEXT: lfd f1, 16(r3)1924; P8BE-NEXT: lfd f2, 8(r3)1925; P8BE-NEXT: lfd f3, 0(r3)1926; P8BE-NEXT: xxmrghd vs1, vs1, vs31927; P8BE-NEXT: xxmrghd vs0, vs0, vs21928; P8BE-NEXT: xvcvdpsxws v2, vs11929; P8BE-NEXT: xvcvdpsxws v3, vs01930; P8BE-NEXT: vmrgew v2, v3, v21931; P8BE-NEXT: blr1932;1933; P8LE-LABEL: fromDiffMemConsDConvdtoi:1934; P8LE: # %bb.0: # %entry1935; P8LE-NEXT: lfd f0, 24(r3)1936; P8LE-NEXT: lfd f1, 16(r3)1937; P8LE-NEXT: lfd f2, 8(r3)1938; P8LE-NEXT: lfd f3, 0(r3)1939; P8LE-NEXT: xxmrghd vs0, vs2, vs01940; P8LE-NEXT: xxmrghd vs1, vs3, vs11941; P8LE-NEXT: xvcvdpsxws v2, vs01942; P8LE-NEXT: xvcvdpsxws v3, vs11943; P8LE-NEXT: vmrgew v2, v3, v21944; P8LE-NEXT: blr1945entry:1946 %arrayidx = getelementptr inbounds double, ptr %ptr, i64 31947 %0 = load double, ptr %arrayidx, align 81948 %conv = fptosi double %0 to i321949 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 01950 %arrayidx1 = getelementptr inbounds double, ptr %ptr, i64 21951 %1 = load double, ptr %arrayidx1, align 81952 %conv2 = fptosi double %1 to i321953 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 11954 %arrayidx4 = getelementptr inbounds double, ptr %ptr, i64 11955 %2 = load double, ptr %arrayidx4, align 81956 %conv5 = fptosi double %2 to i321957 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 21958 %3 = load double, ptr %ptr, align 81959 %conv8 = fptosi double %3 to i321960 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 31961 ret <4 x i32> %vecinit91962}1963 1964define <4 x i32> @fromDiffMemVarAConvdtoi(ptr nocapture readonly %arr, i32 signext %elem) {1965; P9BE-LABEL: fromDiffMemVarAConvdtoi:1966; P9BE: # %bb.0: # %entry1967; P9BE-NEXT: sldi r4, r4, 31968; P9BE-NEXT: lfdux f0, r3, r41969; P9BE-NEXT: lfd f1, 8(r3)1970; P9BE-NEXT: lfd f2, 16(r3)1971; P9BE-NEXT: lfd f3, 24(r3)1972; P9BE-NEXT: xxmrghd vs1, vs1, vs31973; P9BE-NEXT: xxmrghd vs0, vs0, vs21974; P9BE-NEXT: xvcvdpsxws v2, vs11975; P9BE-NEXT: xvcvdpsxws v3, vs01976; P9BE-NEXT: vmrgew v2, v3, v21977; P9BE-NEXT: blr1978;1979; P9LE-LABEL: fromDiffMemVarAConvdtoi:1980; P9LE: # %bb.0: # %entry1981; P9LE-NEXT: sldi r4, r4, 31982; P9LE-NEXT: lfdux f0, r3, r41983; P9LE-NEXT: lfd f2, 16(r3)1984; P9LE-NEXT: lfd f1, 8(r3)1985; P9LE-NEXT: lfd f3, 24(r3)1986; P9LE-NEXT: xxmrghd vs0, vs2, vs01987; P9LE-NEXT: xvcvdpsxws v2, vs01988; P9LE-NEXT: xxmrghd vs0, vs3, vs11989; P9LE-NEXT: xvcvdpsxws v3, vs01990; P9LE-NEXT: vmrgew v2, v3, v21991; P9LE-NEXT: blr1992;1993; P8BE-LABEL: fromDiffMemVarAConvdtoi:1994; P8BE: # %bb.0: # %entry1995; P8BE-NEXT: sldi r4, r4, 31996; P8BE-NEXT: lfdux f0, r3, r41997; P8BE-NEXT: lfd f1, 8(r3)1998; P8BE-NEXT: lfd f2, 16(r3)1999; P8BE-NEXT: lfd f3, 24(r3)2000; P8BE-NEXT: xxmrghd vs1, vs1, vs32001; P8BE-NEXT: xxmrghd vs0, vs0, vs22002; P8BE-NEXT: xvcvdpsxws v2, vs12003; P8BE-NEXT: xvcvdpsxws v3, vs02004; P8BE-NEXT: vmrgew v2, v3, v22005; P8BE-NEXT: blr2006;2007; P8LE-LABEL: fromDiffMemVarAConvdtoi:2008; P8LE: # %bb.0: # %entry2009; P8LE-NEXT: sldi r4, r4, 32010; P8LE-NEXT: lfdux f0, r3, r42011; P8LE-NEXT: lfd f1, 8(r3)2012; P8LE-NEXT: lfd f2, 16(r3)2013; P8LE-NEXT: lfd f3, 24(r3)2014; P8LE-NEXT: xxmrghd vs0, vs2, vs02015; P8LE-NEXT: xxmrghd vs1, vs3, vs12016; P8LE-NEXT: xvcvdpsxws v2, vs02017; P8LE-NEXT: xvcvdpsxws v3, vs12018; P8LE-NEXT: vmrgew v2, v3, v22019; P8LE-NEXT: blr2020entry:2021 %idxprom = sext i32 %elem to i642022 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom2023 %0 = load double, ptr %arrayidx, align 82024 %conv = fptosi double %0 to i322025 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 02026 %add = add nsw i32 %elem, 12027 %idxprom1 = sext i32 %add to i642028 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom12029 %1 = load double, ptr %arrayidx2, align 82030 %conv3 = fptosi double %1 to i322031 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 12032 %add5 = add nsw i32 %elem, 22033 %idxprom6 = sext i32 %add5 to i642034 %arrayidx7 = getelementptr inbounds double, ptr %arr, i64 %idxprom62035 %2 = load double, ptr %arrayidx7, align 82036 %conv8 = fptosi double %2 to i322037 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 22038 %add10 = add nsw i32 %elem, 32039 %idxprom11 = sext i32 %add10 to i642040 %arrayidx12 = getelementptr inbounds double, ptr %arr, i64 %idxprom112041 %3 = load double, ptr %arrayidx12, align 82042 %conv13 = fptosi double %3 to i322043 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 32044 ret <4 x i32> %vecinit142045}2046 2047define <4 x i32> @fromDiffMemVarDConvdtoi(ptr nocapture readonly %arr, i32 signext %elem) {2048; P9BE-LABEL: fromDiffMemVarDConvdtoi:2049; P9BE: # %bb.0: # %entry2050; P9BE-NEXT: sldi r4, r4, 32051; P9BE-NEXT: lfdux f0, r3, r42052; P9BE-NEXT: lfd f1, -8(r3)2053; P9BE-NEXT: lfd f2, -16(r3)2054; P9BE-NEXT: lfd f3, -24(r3)2055; P9BE-NEXT: xxmrghd vs1, vs1, vs32056; P9BE-NEXT: xxmrghd vs0, vs0, vs22057; P9BE-NEXT: xvcvdpsxws v2, vs12058; P9BE-NEXT: xvcvdpsxws v3, vs02059; P9BE-NEXT: vmrgew v2, v3, v22060; P9BE-NEXT: blr2061;2062; P9LE-LABEL: fromDiffMemVarDConvdtoi:2063; P9LE: # %bb.0: # %entry2064; P9LE-NEXT: sldi r4, r4, 32065; P9LE-NEXT: lfdux f0, r3, r42066; P9LE-NEXT: lfd f2, -16(r3)2067; P9LE-NEXT: lfd f1, -8(r3)2068; P9LE-NEXT: lfd f3, -24(r3)2069; P9LE-NEXT: xxmrghd vs0, vs2, vs02070; P9LE-NEXT: xvcvdpsxws v2, vs02071; P9LE-NEXT: xxmrghd vs0, vs3, vs12072; P9LE-NEXT: xvcvdpsxws v3, vs02073; P9LE-NEXT: vmrgew v2, v3, v22074; P9LE-NEXT: blr2075;2076; P8BE-LABEL: fromDiffMemVarDConvdtoi:2077; P8BE: # %bb.0: # %entry2078; P8BE-NEXT: sldi r4, r4, 32079; P8BE-NEXT: lfdux f0, r3, r42080; P8BE-NEXT: lfd f1, -8(r3)2081; P8BE-NEXT: lfd f2, -16(r3)2082; P8BE-NEXT: lfd f3, -24(r3)2083; P8BE-NEXT: xxmrghd vs1, vs1, vs32084; P8BE-NEXT: xxmrghd vs0, vs0, vs22085; P8BE-NEXT: xvcvdpsxws v2, vs12086; P8BE-NEXT: xvcvdpsxws v3, vs02087; P8BE-NEXT: vmrgew v2, v3, v22088; P8BE-NEXT: blr2089;2090; P8LE-LABEL: fromDiffMemVarDConvdtoi:2091; P8LE: # %bb.0: # %entry2092; P8LE-NEXT: sldi r4, r4, 32093; P8LE-NEXT: lfdux f0, r3, r42094; P8LE-NEXT: lfd f1, -8(r3)2095; P8LE-NEXT: lfd f2, -16(r3)2096; P8LE-NEXT: lfd f3, -24(r3)2097; P8LE-NEXT: xxmrghd vs0, vs2, vs02098; P8LE-NEXT: xxmrghd vs1, vs3, vs12099; P8LE-NEXT: xvcvdpsxws v2, vs02100; P8LE-NEXT: xvcvdpsxws v3, vs12101; P8LE-NEXT: vmrgew v2, v3, v22102; P8LE-NEXT: blr2103entry:2104 %idxprom = sext i32 %elem to i642105 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom2106 %0 = load double, ptr %arrayidx, align 82107 %conv = fptosi double %0 to i322108 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 02109 %sub = add nsw i32 %elem, -12110 %idxprom1 = sext i32 %sub to i642111 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom12112 %1 = load double, ptr %arrayidx2, align 82113 %conv3 = fptosi double %1 to i322114 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 12115 %sub5 = add nsw i32 %elem, -22116 %idxprom6 = sext i32 %sub5 to i642117 %arrayidx7 = getelementptr inbounds double, ptr %arr, i64 %idxprom62118 %2 = load double, ptr %arrayidx7, align 82119 %conv8 = fptosi double %2 to i322120 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 22121 %sub10 = add nsw i32 %elem, -32122 %idxprom11 = sext i32 %sub10 to i642123 %arrayidx12 = getelementptr inbounds double, ptr %arr, i64 %idxprom112124 %3 = load double, ptr %arrayidx12, align 82125 %conv13 = fptosi double %3 to i322126 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 32127 ret <4 x i32> %vecinit142128}2129 2130define <4 x i32> @spltRegValConvdtoi(double %val) {2131; P9BE-LABEL: spltRegValConvdtoi:2132; P9BE: # %bb.0: # %entry2133; P9BE-NEXT: xscvdpsxws f0, f12134; P9BE-NEXT: xxspltw v2, vs0, 12135; P9BE-NEXT: blr2136;2137; P9LE-LABEL: spltRegValConvdtoi:2138; P9LE: # %bb.0: # %entry2139; P9LE-NEXT: xscvdpsxws f0, f12140; P9LE-NEXT: xxspltw v2, vs0, 12141; P9LE-NEXT: blr2142;2143; P8BE-LABEL: spltRegValConvdtoi:2144; P8BE: # %bb.0: # %entry2145; P8BE-NEXT: xscvdpsxws f0, f12146; P8BE-NEXT: xxspltw v2, vs0, 12147; P8BE-NEXT: blr2148;2149; P8LE-LABEL: spltRegValConvdtoi:2150; P8LE: # %bb.0: # %entry2151; P8LE-NEXT: xscvdpsxws f0, f12152; P8LE-NEXT: xxspltw v2, vs0, 12153; P8LE-NEXT: blr2154entry:2155 %conv = fptosi double %val to i322156 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 02157 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer2158 ret <4 x i32> %splat.splat2159}2160 2161define <4 x i32> @spltMemValConvdtoi(ptr nocapture readonly %ptr) {2162; P9BE-LABEL: spltMemValConvdtoi:2163; P9BE: # %bb.0: # %entry2164; P9BE-NEXT: lfd f0, 0(r3)2165; P9BE-NEXT: xscvdpsxws f0, f02166; P9BE-NEXT: xxspltw v2, vs0, 12167; P9BE-NEXT: blr2168;2169; P9LE-LABEL: spltMemValConvdtoi:2170; P9LE: # %bb.0: # %entry2171; P9LE-NEXT: lfd f0, 0(r3)2172; P9LE-NEXT: xscvdpsxws f0, f02173; P9LE-NEXT: xxspltw v2, vs0, 12174; P9LE-NEXT: blr2175;2176; P8BE-LABEL: spltMemValConvdtoi:2177; P8BE: # %bb.0: # %entry2178; P8BE-NEXT: lfdx f0, 0, r32179; P8BE-NEXT: xscvdpsxws f0, f02180; P8BE-NEXT: xxspltw v2, vs0, 12181; P8BE-NEXT: blr2182;2183; P8LE-LABEL: spltMemValConvdtoi:2184; P8LE: # %bb.0: # %entry2185; P8LE-NEXT: lfdx f0, 0, r32186; P8LE-NEXT: xscvdpsxws f0, f02187; P8LE-NEXT: xxspltw v2, vs0, 12188; P8LE-NEXT: blr2189entry:2190 %0 = load double, ptr %ptr, align 82191 %conv = fptosi double %0 to i322192 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 02193 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer2194 ret <4 x i32> %splat.splat2195}2196 2197define <4 x i32> @allZeroui() {2198; P9BE-LABEL: allZeroui:2199; P9BE: # %bb.0: # %entry2200; P9BE-NEXT: xxlxor v2, v2, v22201; P9BE-NEXT: blr2202;2203; P9LE-LABEL: allZeroui:2204; P9LE: # %bb.0: # %entry2205; P9LE-NEXT: xxlxor v2, v2, v22206; P9LE-NEXT: blr2207;2208; P8BE-LABEL: allZeroui:2209; P8BE: # %bb.0: # %entry2210; P8BE-NEXT: xxlxor v2, v2, v22211; P8BE-NEXT: blr2212;2213; P8LE-LABEL: allZeroui:2214; P8LE: # %bb.0: # %entry2215; P8LE-NEXT: xxlxor v2, v2, v22216; P8LE-NEXT: blr2217entry:2218 ret <4 x i32> zeroinitializer2219}2220 2221define <4 x i32> @spltConst1ui() {2222; P9BE-LABEL: spltConst1ui:2223; P9BE: # %bb.0: # %entry2224; P9BE-NEXT: vspltisw v2, 12225; P9BE-NEXT: blr2226;2227; P9LE-LABEL: spltConst1ui:2228; P9LE: # %bb.0: # %entry2229; P9LE-NEXT: vspltisw v2, 12230; P9LE-NEXT: blr2231;2232; P8BE-LABEL: spltConst1ui:2233; P8BE: # %bb.0: # %entry2234; P8BE-NEXT: vspltisw v2, 12235; P8BE-NEXT: blr2236;2237; P8LE-LABEL: spltConst1ui:2238; P8LE: # %bb.0: # %entry2239; P8LE-NEXT: vspltisw v2, 12240; P8LE-NEXT: blr2241entry:2242 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1>2243}2244 2245define <4 x i32> @spltConst16kui() {2246; P9BE-LABEL: spltConst16kui:2247; P9BE: # %bb.0: # %entry2248; P9BE-NEXT: vspltisw v2, -152249; P9BE-NEXT: vsrw v2, v2, v22250; P9BE-NEXT: blr2251;2252; P9LE-LABEL: spltConst16kui:2253; P9LE: # %bb.0: # %entry2254; P9LE-NEXT: vspltisw v2, -152255; P9LE-NEXT: vsrw v2, v2, v22256; P9LE-NEXT: blr2257;2258; P8BE-LABEL: spltConst16kui:2259; P8BE: # %bb.0: # %entry2260; P8BE-NEXT: vspltisw v2, -152261; P8BE-NEXT: vsrw v2, v2, v22262; P8BE-NEXT: blr2263;2264; P8LE-LABEL: spltConst16kui:2265; P8LE: # %bb.0: # %entry2266; P8LE-NEXT: vspltisw v2, -152267; P8LE-NEXT: vsrw v2, v2, v22268; P8LE-NEXT: blr2269entry:2270 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>2271}2272 2273define <4 x i32> @spltConst32kui() {2274; P9BE-LABEL: spltConst32kui:2275; P9BE: # %bb.0: # %entry2276; P9BE-NEXT: vspltisw v2, -162277; P9BE-NEXT: vsrw v2, v2, v22278; P9BE-NEXT: blr2279;2280; P9LE-LABEL: spltConst32kui:2281; P9LE: # %bb.0: # %entry2282; P9LE-NEXT: vspltisw v2, -162283; P9LE-NEXT: vsrw v2, v2, v22284; P9LE-NEXT: blr2285;2286; P8BE-LABEL: spltConst32kui:2287; P8BE: # %bb.0: # %entry2288; P8BE-NEXT: vspltisw v2, -162289; P8BE-NEXT: vsrw v2, v2, v22290; P8BE-NEXT: blr2291;2292; P8LE-LABEL: spltConst32kui:2293; P8LE: # %bb.0: # %entry2294; P8LE-NEXT: vspltisw v2, -162295; P8LE-NEXT: vsrw v2, v2, v22296; P8LE-NEXT: blr2297entry:2298 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>2299}2300 2301define <4 x i32> @fromRegsui(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c, i32 zeroext %d) {2302; P9BE-LABEL: fromRegsui:2303; P9BE: # %bb.0: # %entry2304; P9BE-NEXT: rldimi r6, r5, 32, 02305; P9BE-NEXT: rldimi r4, r3, 32, 02306; P9BE-NEXT: mtvsrdd v2, r4, r62307; P9BE-NEXT: blr2308;2309; P9LE-LABEL: fromRegsui:2310; P9LE: # %bb.0: # %entry2311; P9LE-NEXT: rldimi r3, r4, 32, 02312; P9LE-NEXT: rldimi r5, r6, 32, 02313; P9LE-NEXT: mtvsrdd v2, r5, r32314; P9LE-NEXT: blr2315;2316; P8BE-LABEL: fromRegsui:2317; P8BE: # %bb.0: # %entry2318; P8BE-NEXT: rldimi r6, r5, 32, 02319; P8BE-NEXT: rldimi r4, r3, 32, 02320; P8BE-NEXT: mtfprd f0, r62321; P8BE-NEXT: mtfprd f1, r42322; P8BE-NEXT: xxmrghd v2, vs1, vs02323; P8BE-NEXT: blr2324;2325; P8LE-LABEL: fromRegsui:2326; P8LE: # %bb.0: # %entry2327; P8LE-NEXT: rldimi r3, r4, 32, 02328; P8LE-NEXT: rldimi r5, r6, 32, 02329; P8LE-NEXT: mtfprd f0, r32330; P8LE-NEXT: mtfprd f1, r52331; P8LE-NEXT: xxmrghd v2, vs1, vs02332; P8LE-NEXT: blr2333entry:2334 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 02335 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 12336 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 22337 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 32338 ret <4 x i32> %vecinit32339}2340 2341define <4 x i32> @fromDiffConstsui() {2342; P9BE-LABEL: fromDiffConstsui:2343; P9BE: # %bb.0: # %entry2344; P9BE-NEXT: addis r3, r2, .LCPI37_0@toc@ha2345; P9BE-NEXT: addi r3, r3, .LCPI37_0@toc@l2346; P9BE-NEXT: lxv v2, 0(r3)2347; P9BE-NEXT: blr2348;2349; P9LE-LABEL: fromDiffConstsui:2350; P9LE: # %bb.0: # %entry2351; P9LE-NEXT: addis r3, r2, .LCPI37_0@toc@ha2352; P9LE-NEXT: addi r3, r3, .LCPI37_0@toc@l2353; P9LE-NEXT: lxv v2, 0(r3)2354; P9LE-NEXT: blr2355;2356; P8BE-LABEL: fromDiffConstsui:2357; P8BE: # %bb.0: # %entry2358; P8BE-NEXT: addis r3, r2, .LCPI37_0@toc@ha2359; P8BE-NEXT: addi r3, r3, .LCPI37_0@toc@l2360; P8BE-NEXT: lxvw4x v2, 0, r32361; P8BE-NEXT: blr2362;2363; P8LE-LABEL: fromDiffConstsui:2364; P8LE: # %bb.0: # %entry2365; P8LE-NEXT: addis r3, r2, .LCPI37_0@toc@ha2366; P8LE-NEXT: addi r3, r3, .LCPI37_0@toc@l2367; P8LE-NEXT: lxvd2x vs0, 0, r32368; P8LE-NEXT: xxswapd v2, vs02369; P8LE-NEXT: blr2370entry:2371 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19>2372}2373 2374define <4 x i32> @fromDiffMemConsAui(ptr nocapture readonly %arr) {2375; P9BE-LABEL: fromDiffMemConsAui:2376; P9BE: # %bb.0: # %entry2377; P9BE-NEXT: lxv v2, 0(r3)2378; P9BE-NEXT: blr2379;2380; P9LE-LABEL: fromDiffMemConsAui:2381; P9LE: # %bb.0: # %entry2382; P9LE-NEXT: lxv v2, 0(r3)2383; P9LE-NEXT: blr2384;2385; P8BE-LABEL: fromDiffMemConsAui:2386; P8BE: # %bb.0: # %entry2387; P8BE-NEXT: lxvw4x v2, 0, r32388; P8BE-NEXT: blr2389;2390; P8LE-LABEL: fromDiffMemConsAui:2391; P8LE: # %bb.0: # %entry2392; P8LE-NEXT: lxvd2x vs0, 0, r32393; P8LE-NEXT: xxswapd v2, vs02394; P8LE-NEXT: blr2395entry:2396 %0 = load i32, ptr %arr, align 42397 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 02398 %arrayidx1 = getelementptr inbounds i32, ptr %arr, i64 12399 %1 = load i32, ptr %arrayidx1, align 42400 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 12401 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 22402 %2 = load i32, ptr %arrayidx3, align 42403 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 22404 %arrayidx5 = getelementptr inbounds i32, ptr %arr, i64 32405 %3 = load i32, ptr %arrayidx5, align 42406 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 32407 ret <4 x i32> %vecinit62408}2409 2410define <4 x i32> @fromDiffMemConsDui(ptr nocapture readonly %arr) {2411; P9BE-LABEL: fromDiffMemConsDui:2412; P9BE: # %bb.0: # %entry2413; P9BE-NEXT: lxv v2, 0(r3)2414; P9BE-NEXT: addis r3, r2, .LCPI39_0@toc@ha2415; P9BE-NEXT: addi r3, r3, .LCPI39_0@toc@l2416; P9BE-NEXT: lxv vs0, 0(r3)2417; P9BE-NEXT: xxperm v2, v2, vs02418; P9BE-NEXT: blr2419;2420; P9LE-LABEL: fromDiffMemConsDui:2421; P9LE: # %bb.0: # %entry2422; P9LE-NEXT: lxvw4x v2, 0, r32423; P9LE-NEXT: blr2424;2425; P8BE-LABEL: fromDiffMemConsDui:2426; P8BE: # %bb.0: # %entry2427; P8BE-NEXT: lxvw4x v2, 0, r32428; P8BE-NEXT: addis r3, r2, .LCPI39_0@toc@ha2429; P8BE-NEXT: addi r3, r3, .LCPI39_0@toc@l2430; P8BE-NEXT: lxvw4x v3, 0, r32431; P8BE-NEXT: vperm v2, v2, v2, v32432; P8BE-NEXT: blr2433;2434; P8LE-LABEL: fromDiffMemConsDui:2435; P8LE: # %bb.0: # %entry2436; P8LE-NEXT: lxvd2x vs0, 0, r32437; P8LE-NEXT: addis r3, r2, .LCPI39_0@toc@ha2438; P8LE-NEXT: addi r3, r3, .LCPI39_0@toc@l2439; P8LE-NEXT: xxswapd v2, vs02440; P8LE-NEXT: lxvd2x vs0, 0, r32441; P8LE-NEXT: xxswapd v3, vs02442; P8LE-NEXT: vperm v2, v2, v2, v32443; P8LE-NEXT: blr2444entry:2445 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 32446 %0 = load i32, ptr %arrayidx, align 42447 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 02448 %arrayidx1 = getelementptr inbounds i32, ptr %arr, i64 22449 %1 = load i32, ptr %arrayidx1, align 42450 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 12451 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 12452 %2 = load i32, ptr %arrayidx3, align 42453 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 22454 %3 = load i32, ptr %arr, align 42455 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 32456 ret <4 x i32> %vecinit62457}2458 2459define <4 x i32> @fromDiffMemVarAui(ptr nocapture readonly %arr, i32 signext %elem) {2460; P9BE-LABEL: fromDiffMemVarAui:2461; P9BE: # %bb.0: # %entry2462; P9BE-NEXT: sldi r4, r4, 22463; P9BE-NEXT: lxvx v2, r3, r42464; P9BE-NEXT: blr2465;2466; P9LE-LABEL: fromDiffMemVarAui:2467; P9LE: # %bb.0: # %entry2468; P9LE-NEXT: sldi r4, r4, 22469; P9LE-NEXT: lxvx v2, r3, r42470; P9LE-NEXT: blr2471;2472; P8BE-LABEL: fromDiffMemVarAui:2473; P8BE: # %bb.0: # %entry2474; P8BE-NEXT: sldi r4, r4, 22475; P8BE-NEXT: lxvw4x v2, r3, r42476; P8BE-NEXT: blr2477;2478; P8LE-LABEL: fromDiffMemVarAui:2479; P8LE: # %bb.0: # %entry2480; P8LE-NEXT: sldi r4, r4, 22481; P8LE-NEXT: lxvd2x vs0, r3, r42482; P8LE-NEXT: xxswapd v2, vs02483; P8LE-NEXT: blr2484entry:2485 %idxprom = sext i32 %elem to i642486 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 %idxprom2487 %0 = load i32, ptr %arrayidx, align 42488 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 02489 %add = add nsw i32 %elem, 12490 %idxprom1 = sext i32 %add to i642491 %arrayidx2 = getelementptr inbounds i32, ptr %arr, i64 %idxprom12492 %1 = load i32, ptr %arrayidx2, align 42493 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 12494 %add4 = add nsw i32 %elem, 22495 %idxprom5 = sext i32 %add4 to i642496 %arrayidx6 = getelementptr inbounds i32, ptr %arr, i64 %idxprom52497 %2 = load i32, ptr %arrayidx6, align 42498 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 22499 %add8 = add nsw i32 %elem, 32500 %idxprom9 = sext i32 %add8 to i642501 %arrayidx10 = getelementptr inbounds i32, ptr %arr, i64 %idxprom92502 %3 = load i32, ptr %arrayidx10, align 42503 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 32504 ret <4 x i32> %vecinit112505}2506 2507define <4 x i32> @fromDiffMemVarDui(ptr nocapture readonly %arr, i32 signext %elem) {2508; P9BE-LABEL: fromDiffMemVarDui:2509; P9BE: # %bb.0: # %entry2510; P9BE-NEXT: sldi r4, r4, 22511; P9BE-NEXT: add r3, r3, r42512; P9BE-NEXT: li r4, -122513; P9BE-NEXT: lxvx v2, r3, r42514; P9BE-NEXT: addis r3, r2, .LCPI41_0@toc@ha2515; P9BE-NEXT: addi r3, r3, .LCPI41_0@toc@l2516; P9BE-NEXT: lxv vs0, 0(r3)2517; P9BE-NEXT: xxperm v2, v2, vs02518; P9BE-NEXT: blr2519;2520; P9LE-LABEL: fromDiffMemVarDui:2521; P9LE: # %bb.0: # %entry2522; P9LE-NEXT: sldi r4, r4, 22523; P9LE-NEXT: add r3, r3, r42524; P9LE-NEXT: addi r3, r3, -122525; P9LE-NEXT: lxvw4x v2, 0, r32526; P9LE-NEXT: blr2527;2528; P8BE-LABEL: fromDiffMemVarDui:2529; P8BE: # %bb.0: # %entry2530; P8BE-NEXT: sldi r4, r4, 22531; P8BE-NEXT: add r3, r3, r42532; P8BE-NEXT: addi r3, r3, -122533; P8BE-NEXT: lxvw4x v2, 0, r32534; P8BE-NEXT: addis r3, r2, .LCPI41_0@toc@ha2535; P8BE-NEXT: addi r3, r3, .LCPI41_0@toc@l2536; P8BE-NEXT: lxvw4x v3, 0, r32537; P8BE-NEXT: vperm v2, v2, v2, v32538; P8BE-NEXT: blr2539;2540; P8LE-LABEL: fromDiffMemVarDui:2541; P8LE: # %bb.0: # %entry2542; P8LE-NEXT: sldi r4, r4, 22543; P8LE-NEXT: add r3, r3, r42544; P8LE-NEXT: addi r3, r3, -122545; P8LE-NEXT: lxvd2x vs0, 0, r32546; P8LE-NEXT: addis r3, r2, .LCPI41_0@toc@ha2547; P8LE-NEXT: addi r3, r3, .LCPI41_0@toc@l2548; P8LE-NEXT: xxswapd v2, vs02549; P8LE-NEXT: lxvd2x vs0, 0, r32550; P8LE-NEXT: xxswapd v3, vs02551; P8LE-NEXT: vperm v2, v2, v2, v32552; P8LE-NEXT: blr2553entry:2554 %idxprom = sext i32 %elem to i642555 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 %idxprom2556 %0 = load i32, ptr %arrayidx, align 42557 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 02558 %sub = add nsw i32 %elem, -12559 %idxprom1 = sext i32 %sub to i642560 %arrayidx2 = getelementptr inbounds i32, ptr %arr, i64 %idxprom12561 %1 = load i32, ptr %arrayidx2, align 42562 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 12563 %sub4 = add nsw i32 %elem, -22564 %idxprom5 = sext i32 %sub4 to i642565 %arrayidx6 = getelementptr inbounds i32, ptr %arr, i64 %idxprom52566 %2 = load i32, ptr %arrayidx6, align 42567 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 22568 %sub8 = add nsw i32 %elem, -32569 %idxprom9 = sext i32 %sub8 to i642570 %arrayidx10 = getelementptr inbounds i32, ptr %arr, i64 %idxprom92571 %3 = load i32, ptr %arrayidx10, align 42572 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 32573 ret <4 x i32> %vecinit112574}2575 2576define <4 x i32> @fromRandMemConsui(ptr nocapture readonly %arr) {2577; P9BE-LABEL: fromRandMemConsui:2578; P9BE: # %bb.0: # %entry2579; P9BE-NEXT: lwz r4, 16(r3)2580; P9BE-NEXT: lwz r5, 72(r3)2581; P9BE-NEXT: lwz r6, 8(r3)2582; P9BE-NEXT: lwz r3, 352(r3)2583; P9BE-NEXT: rldimi r3, r6, 32, 02584; P9BE-NEXT: rldimi r5, r4, 32, 02585; P9BE-NEXT: mtvsrdd v2, r5, r32586; P9BE-NEXT: blr2587;2588; P9LE-LABEL: fromRandMemConsui:2589; P9LE: # %bb.0: # %entry2590; P9LE-NEXT: lwz r4, 16(r3)2591; P9LE-NEXT: lwz r5, 72(r3)2592; P9LE-NEXT: lwz r6, 8(r3)2593; P9LE-NEXT: lwz r3, 352(r3)2594; P9LE-NEXT: rldimi r4, r5, 32, 02595; P9LE-NEXT: rldimi r6, r3, 32, 02596; P9LE-NEXT: mtvsrdd v2, r6, r42597; P9LE-NEXT: blr2598;2599; P8BE-LABEL: fromRandMemConsui:2600; P8BE: # %bb.0: # %entry2601; P8BE-NEXT: lwz r4, 16(r3)2602; P8BE-NEXT: lwz r5, 72(r3)2603; P8BE-NEXT: lwz r6, 8(r3)2604; P8BE-NEXT: lwz r3, 352(r3)2605; P8BE-NEXT: rldimi r3, r6, 32, 02606; P8BE-NEXT: rldimi r5, r4, 32, 02607; P8BE-NEXT: mtfprd f0, r32608; P8BE-NEXT: mtfprd f1, r52609; P8BE-NEXT: xxmrghd v2, vs1, vs02610; P8BE-NEXT: blr2611;2612; P8LE-LABEL: fromRandMemConsui:2613; P8LE: # %bb.0: # %entry2614; P8LE-NEXT: lwz r4, 16(r3)2615; P8LE-NEXT: lwz r5, 72(r3)2616; P8LE-NEXT: lwz r6, 8(r3)2617; P8LE-NEXT: lwz r3, 352(r3)2618; P8LE-NEXT: rldimi r4, r5, 32, 02619; P8LE-NEXT: rldimi r6, r3, 32, 02620; P8LE-NEXT: mtfprd f0, r42621; P8LE-NEXT: mtfprd f1, r62622; P8LE-NEXT: xxmrghd v2, vs1, vs02623; P8LE-NEXT: blr2624entry:2625 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 42626 %0 = load i32, ptr %arrayidx, align 42627 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 02628 %arrayidx1 = getelementptr inbounds i32, ptr %arr, i64 182629 %1 = load i32, ptr %arrayidx1, align 42630 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 12631 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 22632 %2 = load i32, ptr %arrayidx3, align 42633 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 22634 %arrayidx5 = getelementptr inbounds i32, ptr %arr, i64 882635 %3 = load i32, ptr %arrayidx5, align 42636 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 32637 ret <4 x i32> %vecinit62638}2639 2640define <4 x i32> @fromRandMemVarui(ptr nocapture readonly %arr, i32 signext %elem) {2641; P9BE-LABEL: fromRandMemVarui:2642; P9BE: # %bb.0: # %entry2643; P9BE-NEXT: sldi r4, r4, 22644; P9BE-NEXT: add r3, r3, r42645; P9BE-NEXT: lwz r4, 16(r3)2646; P9BE-NEXT: lwz r5, 4(r3)2647; P9BE-NEXT: lwz r6, 8(r3)2648; P9BE-NEXT: lwz r3, 32(r3)2649; P9BE-NEXT: rldimi r3, r6, 32, 02650; P9BE-NEXT: rldimi r5, r4, 32, 02651; P9BE-NEXT: mtvsrdd v2, r5, r32652; P9BE-NEXT: blr2653;2654; P9LE-LABEL: fromRandMemVarui:2655; P9LE: # %bb.0: # %entry2656; P9LE-NEXT: sldi r4, r4, 22657; P9LE-NEXT: add r3, r3, r42658; P9LE-NEXT: lwz r4, 16(r3)2659; P9LE-NEXT: lwz r5, 4(r3)2660; P9LE-NEXT: lwz r6, 8(r3)2661; P9LE-NEXT: lwz r3, 32(r3)2662; P9LE-NEXT: rldimi r4, r5, 32, 02663; P9LE-NEXT: rldimi r6, r3, 32, 02664; P9LE-NEXT: mtvsrdd v2, r6, r42665; P9LE-NEXT: blr2666;2667; P8BE-LABEL: fromRandMemVarui:2668; P8BE: # %bb.0: # %entry2669; P8BE-NEXT: sldi r4, r4, 22670; P8BE-NEXT: add r3, r3, r42671; P8BE-NEXT: lwz r4, 16(r3)2672; P8BE-NEXT: lwz r5, 4(r3)2673; P8BE-NEXT: lwz r6, 8(r3)2674; P8BE-NEXT: lwz r3, 32(r3)2675; P8BE-NEXT: rldimi r3, r6, 32, 02676; P8BE-NEXT: rldimi r5, r4, 32, 02677; P8BE-NEXT: mtfprd f0, r32678; P8BE-NEXT: mtfprd f1, r52679; P8BE-NEXT: xxmrghd v2, vs1, vs02680; P8BE-NEXT: blr2681;2682; P8LE-LABEL: fromRandMemVarui:2683; P8LE: # %bb.0: # %entry2684; P8LE-NEXT: sldi r4, r4, 22685; P8LE-NEXT: add r3, r3, r42686; P8LE-NEXT: lwz r4, 16(r3)2687; P8LE-NEXT: lwz r5, 4(r3)2688; P8LE-NEXT: lwz r6, 8(r3)2689; P8LE-NEXT: lwz r3, 32(r3)2690; P8LE-NEXT: rldimi r4, r5, 32, 02691; P8LE-NEXT: rldimi r6, r3, 32, 02692; P8LE-NEXT: mtfprd f0, r42693; P8LE-NEXT: mtfprd f1, r62694; P8LE-NEXT: xxmrghd v2, vs1, vs02695; P8LE-NEXT: blr2696entry:2697 %add = add nsw i32 %elem, 42698 %idxprom = sext i32 %add to i642699 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 %idxprom2700 %0 = load i32, ptr %arrayidx, align 42701 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 02702 %add1 = add nsw i32 %elem, 12703 %idxprom2 = sext i32 %add1 to i642704 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 %idxprom22705 %1 = load i32, ptr %arrayidx3, align 42706 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 12707 %add5 = add nsw i32 %elem, 22708 %idxprom6 = sext i32 %add5 to i642709 %arrayidx7 = getelementptr inbounds i32, ptr %arr, i64 %idxprom62710 %2 = load i32, ptr %arrayidx7, align 42711 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 22712 %add9 = add nsw i32 %elem, 82713 %idxprom10 = sext i32 %add9 to i642714 %arrayidx11 = getelementptr inbounds i32, ptr %arr, i64 %idxprom102715 %3 = load i32, ptr %arrayidx11, align 42716 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 32717 ret <4 x i32> %vecinit122718}2719 2720define <4 x i32> @spltRegValui(i32 zeroext %val) {2721; P9BE-LABEL: spltRegValui:2722; P9BE: # %bb.0: # %entry2723; P9BE-NEXT: mtvsrws v2, r32724; P9BE-NEXT: blr2725;2726; P9LE-LABEL: spltRegValui:2727; P9LE: # %bb.0: # %entry2728; P9LE-NEXT: mtvsrws v2, r32729; P9LE-NEXT: blr2730;2731; P8BE-LABEL: spltRegValui:2732; P8BE: # %bb.0: # %entry2733; P8BE-NEXT: mtfprwz f0, r32734; P8BE-NEXT: xxspltw v2, vs0, 12735; P8BE-NEXT: blr2736;2737; P8LE-LABEL: spltRegValui:2738; P8LE: # %bb.0: # %entry2739; P8LE-NEXT: mtfprwz f0, r32740; P8LE-NEXT: xxspltw v2, vs0, 12741; P8LE-NEXT: blr2742entry:2743 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 02744 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer2745 ret <4 x i32> %splat.splat2746}2747 2748define <4 x i32> @spltMemValui(ptr nocapture readonly %ptr) {2749; P9BE-LABEL: spltMemValui:2750; P9BE: # %bb.0: # %entry2751; P9BE-NEXT: lxvwsx v2, 0, r32752; P9BE-NEXT: blr2753;2754; P9LE-LABEL: spltMemValui:2755; P9LE: # %bb.0: # %entry2756; P9LE-NEXT: lxvwsx v2, 0, r32757; P9LE-NEXT: blr2758;2759; P8BE-LABEL: spltMemValui:2760; P8BE: # %bb.0: # %entry2761; P8BE-NEXT: lfiwzx f0, 0, r32762; P8BE-NEXT: xxspltw v2, vs0, 12763; P8BE-NEXT: blr2764;2765; P8LE-LABEL: spltMemValui:2766; P8LE: # %bb.0: # %entry2767; P8LE-NEXT: lfiwzx f0, 0, r32768; P8LE-NEXT: xxspltw v2, vs0, 12769; P8LE-NEXT: blr2770entry:2771 %0 = load i32, ptr %ptr, align 42772 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 02773 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer2774 ret <4 x i32> %splat.splat2775}2776 2777define <4 x i32> @spltCnstConvftoui() {2778; P9BE-LABEL: spltCnstConvftoui:2779; P9BE: # %bb.0: # %entry2780; P9BE-NEXT: vspltisw v2, 42781; P9BE-NEXT: blr2782;2783; P9LE-LABEL: spltCnstConvftoui:2784; P9LE: # %bb.0: # %entry2785; P9LE-NEXT: vspltisw v2, 42786; P9LE-NEXT: blr2787;2788; P8BE-LABEL: spltCnstConvftoui:2789; P8BE: # %bb.0: # %entry2790; P8BE-NEXT: vspltisw v2, 42791; P8BE-NEXT: blr2792;2793; P8LE-LABEL: spltCnstConvftoui:2794; P8LE: # %bb.0: # %entry2795; P8LE-NEXT: vspltisw v2, 42796; P8LE-NEXT: blr2797entry:2798 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4>2799}2800 2801define <4 x i32> @fromRegsConvftoui(float %a, float %b, float %c, float %d) {2802; P9BE-LABEL: fromRegsConvftoui:2803; P9BE: # %bb.0: # %entry2804; P9BE-NEXT: xxmrghd vs0, vs2, vs42805; P9BE-NEXT: xvcvdpuxws v2, vs02806; P9BE-NEXT: xxmrghd vs0, vs1, vs32807; P9BE-NEXT: xvcvdpuxws v3, vs02808; P9BE-NEXT: vmrgew v2, v3, v22809; P9BE-NEXT: blr2810;2811; P9LE-LABEL: fromRegsConvftoui:2812; P9LE: # %bb.0: # %entry2813; P9LE-NEXT: xxmrghd vs0, vs3, vs12814; P9LE-NEXT: xvcvdpuxws v2, vs02815; P9LE-NEXT: xxmrghd vs0, vs4, vs22816; P9LE-NEXT: xvcvdpuxws v3, vs02817; P9LE-NEXT: vmrgew v2, v3, v22818; P9LE-NEXT: blr2819;2820; P8BE-LABEL: fromRegsConvftoui:2821; P8BE: # %bb.0: # %entry2822; P8BE-NEXT: xxmrghd vs0, vs2, vs42823; P8BE-NEXT: xxmrghd vs1, vs1, vs32824; P8BE-NEXT: xvcvdpuxws v2, vs02825; P8BE-NEXT: xvcvdpuxws v3, vs12826; P8BE-NEXT: vmrgew v2, v3, v22827; P8BE-NEXT: blr2828;2829; P8LE-LABEL: fromRegsConvftoui:2830; P8LE: # %bb.0: # %entry2831; P8LE-NEXT: xxmrghd vs0, vs3, vs12832; P8LE-NEXT: xxmrghd vs1, vs4, vs22833; P8LE-NEXT: xvcvdpuxws v2, vs02834; P8LE-NEXT: xvcvdpuxws v3, vs12835; P8LE-NEXT: vmrgew v2, v3, v22836; P8LE-NEXT: blr2837entry:2838 %conv = fptoui float %a to i322839 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 02840 %conv1 = fptoui float %b to i322841 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 12842 %conv3 = fptoui float %c to i322843 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 22844 %conv5 = fptoui float %d to i322845 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 32846 ret <4 x i32> %vecinit62847}2848 2849define <4 x i32> @fromDiffConstsConvftoui() {2850; P9BE-LABEL: fromDiffConstsConvftoui:2851; P9BE: # %bb.0: # %entry2852; P9BE-NEXT: addis r3, r2, .LCPI48_0@toc@ha2853; P9BE-NEXT: addi r3, r3, .LCPI48_0@toc@l2854; P9BE-NEXT: lxv v2, 0(r3)2855; P9BE-NEXT: blr2856;2857; P9LE-LABEL: fromDiffConstsConvftoui:2858; P9LE: # %bb.0: # %entry2859; P9LE-NEXT: addis r3, r2, .LCPI48_0@toc@ha2860; P9LE-NEXT: addi r3, r3, .LCPI48_0@toc@l2861; P9LE-NEXT: lxv v2, 0(r3)2862; P9LE-NEXT: blr2863;2864; P8BE-LABEL: fromDiffConstsConvftoui:2865; P8BE: # %bb.0: # %entry2866; P8BE-NEXT: addis r3, r2, .LCPI48_0@toc@ha2867; P8BE-NEXT: addi r3, r3, .LCPI48_0@toc@l2868; P8BE-NEXT: lxvw4x v2, 0, r32869; P8BE-NEXT: blr2870;2871; P8LE-LABEL: fromDiffConstsConvftoui:2872; P8LE: # %bb.0: # %entry2873; P8LE-NEXT: addis r3, r2, .LCPI48_0@toc@ha2874; P8LE-NEXT: addi r3, r3, .LCPI48_0@toc@l2875; P8LE-NEXT: lxvd2x vs0, 0, r32876; P8LE-NEXT: xxswapd v2, vs02877; P8LE-NEXT: blr2878entry:2879 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>2880}2881 2882define <4 x i32> @fromDiffMemConsAConvftoui(ptr nocapture readonly %ptr) {2883; P9BE-LABEL: fromDiffMemConsAConvftoui:2884; P9BE: # %bb.0: # %entry2885; P9BE-NEXT: lxv vs0, 0(r3)2886; P9BE-NEXT: xvcvspuxws v2, vs02887; P9BE-NEXT: blr2888;2889; P9LE-LABEL: fromDiffMemConsAConvftoui:2890; P9LE: # %bb.0: # %entry2891; P9LE-NEXT: lxv vs0, 0(r3)2892; P9LE-NEXT: xvcvspuxws v2, vs02893; P9LE-NEXT: blr2894;2895; P8BE-LABEL: fromDiffMemConsAConvftoui:2896; P8BE: # %bb.0: # %entry2897; P8BE-NEXT: lxvw4x vs0, 0, r32898; P8BE-NEXT: xvcvspuxws v2, vs02899; P8BE-NEXT: blr2900;2901; P8LE-LABEL: fromDiffMemConsAConvftoui:2902; P8LE: # %bb.0: # %entry2903; P8LE-NEXT: lxvd2x vs0, 0, r32904; P8LE-NEXT: xxswapd v2, vs02905; P8LE-NEXT: xvcvspuxws v2, v22906; P8LE-NEXT: blr2907entry:2908 %0 = load <4 x float>, ptr %ptr, align 42909 %1 = fptoui <4 x float> %0 to <4 x i32>2910 ret <4 x i32> %12911}2912 2913define <4 x i32> @fromDiffMemConsDConvftoui(ptr nocapture readonly %ptr) {2914; P9BE-LABEL: fromDiffMemConsDConvftoui:2915; P9BE: # %bb.0: # %entry2916; P9BE-NEXT: lxv vs0, 0(r3)2917; P9BE-NEXT: addis r3, r2, .LCPI50_0@toc@ha2918; P9BE-NEXT: addi r3, r3, .LCPI50_0@toc@l2919; P9BE-NEXT: lxv vs1, 0(r3)2920; P9BE-NEXT: xxperm vs0, vs0, vs12921; P9BE-NEXT: xvcvspuxws v2, vs02922; P9BE-NEXT: blr2923;2924; P9LE-LABEL: fromDiffMemConsDConvftoui:2925; P9LE: # %bb.0: # %entry2926; P9LE-NEXT: lxv vs0, 0(r3)2927; P9LE-NEXT: addis r3, r2, .LCPI50_0@toc@ha2928; P9LE-NEXT: addi r3, r3, .LCPI50_0@toc@l2929; P9LE-NEXT: lxv vs1, 0(r3)2930; P9LE-NEXT: xxperm vs0, vs0, vs12931; P9LE-NEXT: xvcvspuxws v2, vs02932; P9LE-NEXT: blr2933;2934; P8BE-LABEL: fromDiffMemConsDConvftoui:2935; P8BE: # %bb.0: # %entry2936; P8BE-NEXT: lxvw4x v2, 0, r32937; P8BE-NEXT: addis r3, r2, .LCPI50_0@toc@ha2938; P8BE-NEXT: addi r3, r3, .LCPI50_0@toc@l2939; P8BE-NEXT: lxvw4x v3, 0, r32940; P8BE-NEXT: vperm v2, v2, v2, v32941; P8BE-NEXT: xvcvspuxws v2, v22942; P8BE-NEXT: blr2943;2944; P8LE-LABEL: fromDiffMemConsDConvftoui:2945; P8LE: # %bb.0: # %entry2946; P8LE-NEXT: addis r4, r2, .LCPI50_0@toc@ha2947; P8LE-NEXT: lxvd2x v3, 0, r32948; P8LE-NEXT: addi r4, r4, .LCPI50_0@toc@l2949; P8LE-NEXT: lxvd2x vs0, 0, r42950; P8LE-NEXT: xxswapd v2, vs02951; P8LE-NEXT: vperm v2, v3, v3, v22952; P8LE-NEXT: xvcvspuxws v2, v22953; P8LE-NEXT: blr2954entry:2955 %arrayidx = getelementptr inbounds float, ptr %ptr, i64 32956 %0 = load float, ptr %arrayidx, align 42957 %conv = fptoui float %0 to i322958 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 02959 %arrayidx1 = getelementptr inbounds float, ptr %ptr, i64 22960 %1 = load float, ptr %arrayidx1, align 42961 %conv2 = fptoui float %1 to i322962 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 12963 %arrayidx4 = getelementptr inbounds float, ptr %ptr, i64 12964 %2 = load float, ptr %arrayidx4, align 42965 %conv5 = fptoui float %2 to i322966 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 22967 %3 = load float, ptr %ptr, align 42968 %conv8 = fptoui float %3 to i322969 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 32970 ret <4 x i32> %vecinit92971}2972 2973define <4 x i32> @fromDiffMemVarAConvftoui(ptr nocapture readonly %arr, i32 signext %elem) {2974; P9BE-LABEL: fromDiffMemVarAConvftoui:2975; P9BE: # %bb.0: # %entry2976; P9BE-NEXT: sldi r4, r4, 22977; P9BE-NEXT: lfsux f0, r3, r42978; P9BE-NEXT: lfs f1, 12(r3)2979; P9BE-NEXT: lfs f2, 4(r3)2980; P9BE-NEXT: xxmrghd vs1, vs2, vs12981; P9BE-NEXT: xvcvdpsp v2, vs12982; P9BE-NEXT: lfs f1, 8(r3)2983; P9BE-NEXT: xxmrghd vs0, vs0, vs12984; P9BE-NEXT: xvcvdpsp v3, vs02985; P9BE-NEXT: vmrgew v2, v3, v22986; P9BE-NEXT: xvcvspuxws v2, v22987; P9BE-NEXT: blr2988;2989; P9LE-LABEL: fromDiffMemVarAConvftoui:2990; P9LE: # %bb.0: # %entry2991; P9LE-NEXT: sldi r4, r4, 22992; P9LE-NEXT: lfsux f0, r3, r42993; P9LE-NEXT: lfs f1, 8(r3)2994; P9LE-NEXT: xxmrghd vs0, vs1, vs02995; P9LE-NEXT: lfs f1, 12(r3)2996; P9LE-NEXT: xvcvdpsp v2, vs02997; P9LE-NEXT: lfs f0, 4(r3)2998; P9LE-NEXT: xxmrghd vs0, vs1, vs02999; P9LE-NEXT: xvcvdpsp v3, vs03000; P9LE-NEXT: vmrgew v2, v3, v23001; P9LE-NEXT: xvcvspuxws v2, v23002; P9LE-NEXT: blr3003;3004; P8BE-LABEL: fromDiffMemVarAConvftoui:3005; P8BE: # %bb.0: # %entry3006; P8BE-NEXT: sldi r4, r4, 23007; P8BE-NEXT: lfsux f0, r3, r43008; P8BE-NEXT: lfs f1, 12(r3)3009; P8BE-NEXT: lfs f2, 4(r3)3010; P8BE-NEXT: xxmrghd vs1, vs2, vs13011; P8BE-NEXT: lfs f2, 8(r3)3012; P8BE-NEXT: xvcvdpsp v2, vs13013; P8BE-NEXT: xxmrghd vs0, vs0, vs23014; P8BE-NEXT: xvcvdpsp v3, vs03015; P8BE-NEXT: vmrgew v2, v3, v23016; P8BE-NEXT: xvcvspuxws v2, v23017; P8BE-NEXT: blr3018;3019; P8LE-LABEL: fromDiffMemVarAConvftoui:3020; P8LE: # %bb.0: # %entry3021; P8LE-NEXT: sldi r4, r4, 23022; P8LE-NEXT: lfsux f0, r3, r43023; P8LE-NEXT: lfs f1, 8(r3)3024; P8LE-NEXT: xxmrghd vs0, vs1, vs03025; P8LE-NEXT: lfs f1, 4(r3)3026; P8LE-NEXT: lfs f2, 12(r3)3027; P8LE-NEXT: xvcvdpsp v2, vs03028; P8LE-NEXT: xxmrghd vs1, vs2, vs13029; P8LE-NEXT: xvcvdpsp v3, vs13030; P8LE-NEXT: vmrgew v2, v3, v23031; P8LE-NEXT: xvcvspuxws v2, v23032; P8LE-NEXT: blr3033entry:3034 %idxprom = sext i32 %elem to i643035 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom3036 %0 = load float, ptr %arrayidx, align 43037 %conv = fptoui float %0 to i323038 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 03039 %add = add nsw i32 %elem, 13040 %idxprom1 = sext i32 %add to i643041 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom13042 %1 = load float, ptr %arrayidx2, align 43043 %conv3 = fptoui float %1 to i323044 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 13045 %add5 = add nsw i32 %elem, 23046 %idxprom6 = sext i32 %add5 to i643047 %arrayidx7 = getelementptr inbounds float, ptr %arr, i64 %idxprom63048 %2 = load float, ptr %arrayidx7, align 43049 %conv8 = fptoui float %2 to i323050 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 23051 %add10 = add nsw i32 %elem, 33052 %idxprom11 = sext i32 %add10 to i643053 %arrayidx12 = getelementptr inbounds float, ptr %arr, i64 %idxprom113054 %3 = load float, ptr %arrayidx12, align 43055 %conv13 = fptoui float %3 to i323056 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 33057 ret <4 x i32> %vecinit143058; FIXME: implement finding consecutive loads with pre-inc3059}3060 3061define <4 x i32> @fromDiffMemVarDConvftoui(ptr nocapture readonly %arr, i32 signext %elem) {3062; P9BE-LABEL: fromDiffMemVarDConvftoui:3063; P9BE: # %bb.0: # %entry3064; P9BE-NEXT: sldi r4, r4, 23065; P9BE-NEXT: lfsux f0, r3, r43066; P9BE-NEXT: lfs f1, -12(r3)3067; P9BE-NEXT: lfs f2, -4(r3)3068; P9BE-NEXT: xxmrghd vs1, vs2, vs13069; P9BE-NEXT: xvcvdpsp v2, vs13070; P9BE-NEXT: lfs f1, -8(r3)3071; P9BE-NEXT: xxmrghd vs0, vs0, vs13072; P9BE-NEXT: xvcvdpsp v3, vs03073; P9BE-NEXT: vmrgew v2, v3, v23074; P9BE-NEXT: xvcvspuxws v2, v23075; P9BE-NEXT: blr3076;3077; P9LE-LABEL: fromDiffMemVarDConvftoui:3078; P9LE: # %bb.0: # %entry3079; P9LE-NEXT: sldi r4, r4, 23080; P9LE-NEXT: lfsux f0, r3, r43081; P9LE-NEXT: lfs f1, -8(r3)3082; P9LE-NEXT: xxmrghd vs0, vs1, vs03083; P9LE-NEXT: lfs f1, -12(r3)3084; P9LE-NEXT: xvcvdpsp v2, vs03085; P9LE-NEXT: lfs f0, -4(r3)3086; P9LE-NEXT: xxmrghd vs0, vs1, vs03087; P9LE-NEXT: xvcvdpsp v3, vs03088; P9LE-NEXT: vmrgew v2, v3, v23089; P9LE-NEXT: xvcvspuxws v2, v23090; P9LE-NEXT: blr3091;3092; P8BE-LABEL: fromDiffMemVarDConvftoui:3093; P8BE: # %bb.0: # %entry3094; P8BE-NEXT: sldi r4, r4, 23095; P8BE-NEXT: lfsux f0, r3, r43096; P8BE-NEXT: lfs f1, -12(r3)3097; P8BE-NEXT: lfs f2, -4(r3)3098; P8BE-NEXT: xxmrghd vs1, vs2, vs13099; P8BE-NEXT: lfs f2, -8(r3)3100; P8BE-NEXT: xvcvdpsp v2, vs13101; P8BE-NEXT: xxmrghd vs0, vs0, vs23102; P8BE-NEXT: xvcvdpsp v3, vs03103; P8BE-NEXT: vmrgew v2, v3, v23104; P8BE-NEXT: xvcvspuxws v2, v23105; P8BE-NEXT: blr3106;3107; P8LE-LABEL: fromDiffMemVarDConvftoui:3108; P8LE: # %bb.0: # %entry3109; P8LE-NEXT: sldi r4, r4, 23110; P8LE-NEXT: lfsux f0, r3, r43111; P8LE-NEXT: lfs f1, -8(r3)3112; P8LE-NEXT: xxmrghd vs0, vs1, vs03113; P8LE-NEXT: lfs f1, -4(r3)3114; P8LE-NEXT: lfs f2, -12(r3)3115; P8LE-NEXT: xvcvdpsp v2, vs03116; P8LE-NEXT: xxmrghd vs1, vs2, vs13117; P8LE-NEXT: xvcvdpsp v3, vs13118; P8LE-NEXT: vmrgew v2, v3, v23119; P8LE-NEXT: xvcvspuxws v2, v23120; P8LE-NEXT: blr3121entry:3122 %idxprom = sext i32 %elem to i643123 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom3124 %0 = load float, ptr %arrayidx, align 43125 %conv = fptoui float %0 to i323126 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 03127 %sub = add nsw i32 %elem, -13128 %idxprom1 = sext i32 %sub to i643129 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom13130 %1 = load float, ptr %arrayidx2, align 43131 %conv3 = fptoui float %1 to i323132 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 13133 %sub5 = add nsw i32 %elem, -23134 %idxprom6 = sext i32 %sub5 to i643135 %arrayidx7 = getelementptr inbounds float, ptr %arr, i64 %idxprom63136 %2 = load float, ptr %arrayidx7, align 43137 %conv8 = fptoui float %2 to i323138 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 23139 %sub10 = add nsw i32 %elem, -33140 %idxprom11 = sext i32 %sub10 to i643141 %arrayidx12 = getelementptr inbounds float, ptr %arr, i64 %idxprom113142 %3 = load float, ptr %arrayidx12, align 43143 %conv13 = fptoui float %3 to i323144 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 33145 ret <4 x i32> %vecinit143146; FIXME: implement finding consecutive loads with pre-inc3147}3148 3149define <4 x i32> @spltRegValConvftoui(float %val) {3150; P9BE-LABEL: spltRegValConvftoui:3151; P9BE: # %bb.0: # %entry3152; P9BE-NEXT: xscvdpuxws f0, f13153; P9BE-NEXT: xxspltw v2, vs0, 13154; P9BE-NEXT: blr3155;3156; P9LE-LABEL: spltRegValConvftoui:3157; P9LE: # %bb.0: # %entry3158; P9LE-NEXT: xscvdpuxws f0, f13159; P9LE-NEXT: xxspltw v2, vs0, 13160; P9LE-NEXT: blr3161;3162; P8BE-LABEL: spltRegValConvftoui:3163; P8BE: # %bb.0: # %entry3164; P8BE-NEXT: xscvdpuxws f0, f13165; P8BE-NEXT: xxspltw v2, vs0, 13166; P8BE-NEXT: blr3167;3168; P8LE-LABEL: spltRegValConvftoui:3169; P8LE: # %bb.0: # %entry3170; P8LE-NEXT: xscvdpuxws f0, f13171; P8LE-NEXT: xxspltw v2, vs0, 13172; P8LE-NEXT: blr3173entry:3174 %conv = fptoui float %val to i323175 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 03176 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer3177 ret <4 x i32> %splat.splat3178}3179 3180define <4 x i32> @spltMemValConvftoui(ptr nocapture readonly %ptr) {3181; P9BE-LABEL: spltMemValConvftoui:3182; P9BE: # %bb.0: # %entry3183; P9BE-NEXT: lfiwzx f0, 0, r33184; P9BE-NEXT: xvcvspuxws vs0, vs03185; P9BE-NEXT: xxspltw v2, vs0, 13186; P9BE-NEXT: blr3187;3188; P9LE-LABEL: spltMemValConvftoui:3189; P9LE: # %bb.0: # %entry3190; P9LE-NEXT: lfiwzx f0, 0, r33191; P9LE-NEXT: xvcvspuxws vs0, vs03192; P9LE-NEXT: xxspltw v2, vs0, 13193; P9LE-NEXT: blr3194;3195; P8BE-LABEL: spltMemValConvftoui:3196; P8BE: # %bb.0: # %entry3197; P8BE-NEXT: lfsx f0, 0, r33198; P8BE-NEXT: xscvdpuxws f0, f03199; P8BE-NEXT: xxspltw v2, vs0, 13200; P8BE-NEXT: blr3201;3202; P8LE-LABEL: spltMemValConvftoui:3203; P8LE: # %bb.0: # %entry3204; P8LE-NEXT: lfsx f0, 0, r33205; P8LE-NEXT: xscvdpuxws f0, f03206; P8LE-NEXT: xxspltw v2, vs0, 13207; P8LE-NEXT: blr3208entry:3209 %0 = load float, ptr %ptr, align 43210 %conv = fptoui float %0 to i323211 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 03212 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer3213 ret <4 x i32> %splat.splat3214}3215 3216define <4 x i32> @spltCnstConvdtoui() {3217; P9BE-LABEL: spltCnstConvdtoui:3218; P9BE: # %bb.0: # %entry3219; P9BE-NEXT: vspltisw v2, 43220; P9BE-NEXT: blr3221;3222; P9LE-LABEL: spltCnstConvdtoui:3223; P9LE: # %bb.0: # %entry3224; P9LE-NEXT: vspltisw v2, 43225; P9LE-NEXT: blr3226;3227; P8BE-LABEL: spltCnstConvdtoui:3228; P8BE: # %bb.0: # %entry3229; P8BE-NEXT: vspltisw v2, 43230; P8BE-NEXT: blr3231;3232; P8LE-LABEL: spltCnstConvdtoui:3233; P8LE: # %bb.0: # %entry3234; P8LE-NEXT: vspltisw v2, 43235; P8LE-NEXT: blr3236entry:3237 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4>3238}3239 3240define <4 x i32> @fromRegsConvdtoui(double %a, double %b, double %c, double %d) {3241; P9BE-LABEL: fromRegsConvdtoui:3242; P9BE: # %bb.0: # %entry3243; P9BE-NEXT: xxmrghd vs0, vs2, vs43244; P9BE-NEXT: xvcvdpuxws v2, vs03245; P9BE-NEXT: xxmrghd vs0, vs1, vs33246; P9BE-NEXT: xvcvdpuxws v3, vs03247; P9BE-NEXT: vmrgew v2, v3, v23248; P9BE-NEXT: blr3249;3250; P9LE-LABEL: fromRegsConvdtoui:3251; P9LE: # %bb.0: # %entry3252; P9LE-NEXT: xxmrghd vs0, vs3, vs13253; P9LE-NEXT: xvcvdpuxws v2, vs03254; P9LE-NEXT: xxmrghd vs0, vs4, vs23255; P9LE-NEXT: xvcvdpuxws v3, vs03256; P9LE-NEXT: vmrgew v2, v3, v23257; P9LE-NEXT: blr3258;3259; P8BE-LABEL: fromRegsConvdtoui:3260; P8BE: # %bb.0: # %entry3261; P8BE-NEXT: xxmrghd vs0, vs2, vs43262; P8BE-NEXT: xxmrghd vs1, vs1, vs33263; P8BE-NEXT: xvcvdpuxws v2, vs03264; P8BE-NEXT: xvcvdpuxws v3, vs13265; P8BE-NEXT: vmrgew v2, v3, v23266; P8BE-NEXT: blr3267;3268; P8LE-LABEL: fromRegsConvdtoui:3269; P8LE: # %bb.0: # %entry3270; P8LE-NEXT: xxmrghd vs0, vs3, vs13271; P8LE-NEXT: xxmrghd vs1, vs4, vs23272; P8LE-NEXT: xvcvdpuxws v2, vs03273; P8LE-NEXT: xvcvdpuxws v3, vs13274; P8LE-NEXT: vmrgew v2, v3, v23275; P8LE-NEXT: blr3276entry:3277 %conv = fptoui double %a to i323278 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 03279 %conv1 = fptoui double %b to i323280 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 13281 %conv3 = fptoui double %c to i323282 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 23283 %conv5 = fptoui double %d to i323284 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 33285 ret <4 x i32> %vecinit63286}3287 3288define <4 x i32> @fromDiffConstsConvdtoui() {3289; P9BE-LABEL: fromDiffConstsConvdtoui:3290; P9BE: # %bb.0: # %entry3291; P9BE-NEXT: addis r3, r2, .LCPI57_0@toc@ha3292; P9BE-NEXT: addi r3, r3, .LCPI57_0@toc@l3293; P9BE-NEXT: lxv v2, 0(r3)3294; P9BE-NEXT: blr3295;3296; P9LE-LABEL: fromDiffConstsConvdtoui:3297; P9LE: # %bb.0: # %entry3298; P9LE-NEXT: addis r3, r2, .LCPI57_0@toc@ha3299; P9LE-NEXT: addi r3, r3, .LCPI57_0@toc@l3300; P9LE-NEXT: lxv v2, 0(r3)3301; P9LE-NEXT: blr3302;3303; P8BE-LABEL: fromDiffConstsConvdtoui:3304; P8BE: # %bb.0: # %entry3305; P8BE-NEXT: addis r3, r2, .LCPI57_0@toc@ha3306; P8BE-NEXT: addi r3, r3, .LCPI57_0@toc@l3307; P8BE-NEXT: lxvw4x v2, 0, r33308; P8BE-NEXT: blr3309;3310; P8LE-LABEL: fromDiffConstsConvdtoui:3311; P8LE: # %bb.0: # %entry3312; P8LE-NEXT: addis r3, r2, .LCPI57_0@toc@ha3313; P8LE-NEXT: addi r3, r3, .LCPI57_0@toc@l3314; P8LE-NEXT: lxvd2x vs0, 0, r33315; P8LE-NEXT: xxswapd v2, vs03316; P8LE-NEXT: blr3317entry:3318 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>3319}3320 3321define <4 x i32> @fromDiffMemConsAConvdtoui(ptr nocapture readonly %ptr) {3322; P9BE-LABEL: fromDiffMemConsAConvdtoui:3323; P9BE: # %bb.0: # %entry3324; P9BE-NEXT: lxv vs0, 0(r3)3325; P9BE-NEXT: lxv vs1, 16(r3)3326; P9BE-NEXT: xxmrgld vs2, vs0, vs13327; P9BE-NEXT: xxmrghd vs0, vs0, vs13328; P9BE-NEXT: xvcvdpuxws v2, vs23329; P9BE-NEXT: xvcvdpuxws v3, vs03330; P9BE-NEXT: vmrgew v2, v3, v23331; P9BE-NEXT: blr3332;3333; P9LE-LABEL: fromDiffMemConsAConvdtoui:3334; P9LE: # %bb.0: # %entry3335; P9LE-NEXT: lxv vs0, 0(r3)3336; P9LE-NEXT: lxv vs1, 16(r3)3337; P9LE-NEXT: xxmrgld vs2, vs1, vs03338; P9LE-NEXT: xxmrghd vs0, vs1, vs03339; P9LE-NEXT: xvcvdpuxws v2, vs23340; P9LE-NEXT: xvcvdpuxws v3, vs03341; P9LE-NEXT: vmrgew v2, v3, v23342; P9LE-NEXT: blr3343;3344; P8BE-LABEL: fromDiffMemConsAConvdtoui:3345; P8BE: # %bb.0: # %entry3346; P8BE-NEXT: li r4, 163347; P8BE-NEXT: lxvd2x vs0, 0, r33348; P8BE-NEXT: lxvd2x vs1, r3, r43349; P8BE-NEXT: xxmrgld vs2, vs0, vs13350; P8BE-NEXT: xxmrghd vs0, vs0, vs13351; P8BE-NEXT: xvcvdpuxws v2, vs23352; P8BE-NEXT: xvcvdpuxws v3, vs03353; P8BE-NEXT: vmrgew v2, v3, v23354; P8BE-NEXT: blr3355;3356; P8LE-LABEL: fromDiffMemConsAConvdtoui:3357; P8LE: # %bb.0: # %entry3358; P8LE-NEXT: li r4, 163359; P8LE-NEXT: lxvd2x vs0, 0, r33360; P8LE-NEXT: lxvd2x vs1, r3, r43361; P8LE-NEXT: xxswapd vs0, vs03362; P8LE-NEXT: xxswapd vs1, vs13363; P8LE-NEXT: xxmrgld vs2, vs1, vs03364; P8LE-NEXT: xxmrghd vs0, vs1, vs03365; P8LE-NEXT: xvcvdpuxws v2, vs23366; P8LE-NEXT: xvcvdpuxws v3, vs03367; P8LE-NEXT: vmrgew v2, v3, v23368; P8LE-NEXT: blr3369entry:3370 %0 = load <2 x double>, ptr %ptr, align 83371 %1 = fptoui <2 x double> %0 to <2 x i32>3372 %arrayidx4 = getelementptr inbounds double, ptr %ptr, i64 23373 %2 = load <2 x double>, ptr %arrayidx4, align 83374 %3 = fptoui <2 x double> %2 to <2 x i32>3375 %vecinit9 = shufflevector <2 x i32> %1, <2 x i32> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>3376 ret <4 x i32> %vecinit93377}3378 3379define <4 x i32> @fromDiffMemConsDConvdtoui(ptr nocapture readonly %ptr) {3380; P9BE-LABEL: fromDiffMemConsDConvdtoui:3381; P9BE: # %bb.0: # %entry3382; P9BE-NEXT: lfd f0, 24(r3)3383; P9BE-NEXT: lfd f1, 16(r3)3384; P9BE-NEXT: lfd f2, 8(r3)3385; P9BE-NEXT: xxmrghd vs0, vs0, vs23386; P9BE-NEXT: lfd f3, 0(r3)3387; P9BE-NEXT: xxmrghd vs1, vs1, vs33388; P9BE-NEXT: xvcvdpuxws v2, vs13389; P9BE-NEXT: xvcvdpuxws v3, vs03390; P9BE-NEXT: vmrgew v2, v3, v23391; P9BE-NEXT: blr3392;3393; P9LE-LABEL: fromDiffMemConsDConvdtoui:3394; P9LE: # %bb.0: # %entry3395; P9LE-NEXT: lfd f0, 24(r3)3396; P9LE-NEXT: lfd f2, 8(r3)3397; P9LE-NEXT: xxmrghd vs0, vs2, vs03398; P9LE-NEXT: lfd f1, 16(r3)3399; P9LE-NEXT: lfd f3, 0(r3)3400; P9LE-NEXT: xvcvdpuxws v2, vs03401; P9LE-NEXT: xxmrghd vs0, vs3, vs13402; P9LE-NEXT: xvcvdpuxws v3, vs03403; P9LE-NEXT: vmrgew v2, v3, v23404; P9LE-NEXT: blr3405;3406; P8BE-LABEL: fromDiffMemConsDConvdtoui:3407; P8BE: # %bb.0: # %entry3408; P8BE-NEXT: lfd f0, 24(r3)3409; P8BE-NEXT: lfd f1, 16(r3)3410; P8BE-NEXT: lfd f2, 8(r3)3411; P8BE-NEXT: lfd f3, 0(r3)3412; P8BE-NEXT: xxmrghd vs1, vs1, vs33413; P8BE-NEXT: xxmrghd vs0, vs0, vs23414; P8BE-NEXT: xvcvdpuxws v2, vs13415; P8BE-NEXT: xvcvdpuxws v3, vs03416; P8BE-NEXT: vmrgew v2, v3, v23417; P8BE-NEXT: blr3418;3419; P8LE-LABEL: fromDiffMemConsDConvdtoui:3420; P8LE: # %bb.0: # %entry3421; P8LE-NEXT: lfd f0, 24(r3)3422; P8LE-NEXT: lfd f1, 16(r3)3423; P8LE-NEXT: lfd f2, 8(r3)3424; P8LE-NEXT: lfd f3, 0(r3)3425; P8LE-NEXT: xxmrghd vs0, vs2, vs03426; P8LE-NEXT: xxmrghd vs1, vs3, vs13427; P8LE-NEXT: xvcvdpuxws v2, vs03428; P8LE-NEXT: xvcvdpuxws v3, vs13429; P8LE-NEXT: vmrgew v2, v3, v23430; P8LE-NEXT: blr3431entry:3432 %arrayidx = getelementptr inbounds double, ptr %ptr, i64 33433 %0 = load double, ptr %arrayidx, align 83434 %conv = fptoui double %0 to i323435 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 03436 %arrayidx1 = getelementptr inbounds double, ptr %ptr, i64 23437 %1 = load double, ptr %arrayidx1, align 83438 %conv2 = fptoui double %1 to i323439 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 13440 %arrayidx4 = getelementptr inbounds double, ptr %ptr, i64 13441 %2 = load double, ptr %arrayidx4, align 83442 %conv5 = fptoui double %2 to i323443 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 23444 %3 = load double, ptr %ptr, align 83445 %conv8 = fptoui double %3 to i323446 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 33447 ret <4 x i32> %vecinit93448}3449 3450define <4 x i32> @fromDiffMemVarAConvdtoui(ptr nocapture readonly %arr, i32 signext %elem) {3451; P9BE-LABEL: fromDiffMemVarAConvdtoui:3452; P9BE: # %bb.0: # %entry3453; P9BE-NEXT: sldi r4, r4, 33454; P9BE-NEXT: lfdux f0, r3, r43455; P9BE-NEXT: lfd f1, 8(r3)3456; P9BE-NEXT: lfd f2, 16(r3)3457; P9BE-NEXT: lfd f3, 24(r3)3458; P9BE-NEXT: xxmrghd vs1, vs1, vs33459; P9BE-NEXT: xxmrghd vs0, vs0, vs23460; P9BE-NEXT: xvcvdpuxws v2, vs13461; P9BE-NEXT: xvcvdpuxws v3, vs03462; P9BE-NEXT: vmrgew v2, v3, v23463; P9BE-NEXT: blr3464;3465; P9LE-LABEL: fromDiffMemVarAConvdtoui:3466; P9LE: # %bb.0: # %entry3467; P9LE-NEXT: sldi r4, r4, 33468; P9LE-NEXT: lfdux f0, r3, r43469; P9LE-NEXT: lfd f2, 16(r3)3470; P9LE-NEXT: lfd f1, 8(r3)3471; P9LE-NEXT: lfd f3, 24(r3)3472; P9LE-NEXT: xxmrghd vs0, vs2, vs03473; P9LE-NEXT: xvcvdpuxws v2, vs03474; P9LE-NEXT: xxmrghd vs0, vs3, vs13475; P9LE-NEXT: xvcvdpuxws v3, vs03476; P9LE-NEXT: vmrgew v2, v3, v23477; P9LE-NEXT: blr3478;3479; P8BE-LABEL: fromDiffMemVarAConvdtoui:3480; P8BE: # %bb.0: # %entry3481; P8BE-NEXT: sldi r4, r4, 33482; P8BE-NEXT: lfdux f0, r3, r43483; P8BE-NEXT: lfd f1, 8(r3)3484; P8BE-NEXT: lfd f2, 16(r3)3485; P8BE-NEXT: lfd f3, 24(r3)3486; P8BE-NEXT: xxmrghd vs1, vs1, vs33487; P8BE-NEXT: xxmrghd vs0, vs0, vs23488; P8BE-NEXT: xvcvdpuxws v2, vs13489; P8BE-NEXT: xvcvdpuxws v3, vs03490; P8BE-NEXT: vmrgew v2, v3, v23491; P8BE-NEXT: blr3492;3493; P8LE-LABEL: fromDiffMemVarAConvdtoui:3494; P8LE: # %bb.0: # %entry3495; P8LE-NEXT: sldi r4, r4, 33496; P8LE-NEXT: lfdux f0, r3, r43497; P8LE-NEXT: lfd f1, 8(r3)3498; P8LE-NEXT: lfd f2, 16(r3)3499; P8LE-NEXT: lfd f3, 24(r3)3500; P8LE-NEXT: xxmrghd vs0, vs2, vs03501; P8LE-NEXT: xxmrghd vs1, vs3, vs13502; P8LE-NEXT: xvcvdpuxws v2, vs03503; P8LE-NEXT: xvcvdpuxws v3, vs13504; P8LE-NEXT: vmrgew v2, v3, v23505; P8LE-NEXT: blr3506entry:3507 %idxprom = sext i32 %elem to i643508 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom3509 %0 = load double, ptr %arrayidx, align 83510 %conv = fptoui double %0 to i323511 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 03512 %add = add nsw i32 %elem, 13513 %idxprom1 = sext i32 %add to i643514 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom13515 %1 = load double, ptr %arrayidx2, align 83516 %conv3 = fptoui double %1 to i323517 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 13518 %add5 = add nsw i32 %elem, 23519 %idxprom6 = sext i32 %add5 to i643520 %arrayidx7 = getelementptr inbounds double, ptr %arr, i64 %idxprom63521 %2 = load double, ptr %arrayidx7, align 83522 %conv8 = fptoui double %2 to i323523 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 23524 %add10 = add nsw i32 %elem, 33525 %idxprom11 = sext i32 %add10 to i643526 %arrayidx12 = getelementptr inbounds double, ptr %arr, i64 %idxprom113527 %3 = load double, ptr %arrayidx12, align 83528 %conv13 = fptoui double %3 to i323529 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 33530 ret <4 x i32> %vecinit143531}3532 3533define <4 x i32> @fromDiffMemVarDConvdtoui(ptr nocapture readonly %arr, i32 signext %elem) {3534; P9BE-LABEL: fromDiffMemVarDConvdtoui:3535; P9BE: # %bb.0: # %entry3536; P9BE-NEXT: sldi r4, r4, 33537; P9BE-NEXT: lfdux f0, r3, r43538; P9BE-NEXT: lfd f1, -8(r3)3539; P9BE-NEXT: lfd f2, -16(r3)3540; P9BE-NEXT: lfd f3, -24(r3)3541; P9BE-NEXT: xxmrghd vs1, vs1, vs33542; P9BE-NEXT: xxmrghd vs0, vs0, vs23543; P9BE-NEXT: xvcvdpuxws v2, vs13544; P9BE-NEXT: xvcvdpuxws v3, vs03545; P9BE-NEXT: vmrgew v2, v3, v23546; P9BE-NEXT: blr3547;3548; P9LE-LABEL: fromDiffMemVarDConvdtoui:3549; P9LE: # %bb.0: # %entry3550; P9LE-NEXT: sldi r4, r4, 33551; P9LE-NEXT: lfdux f0, r3, r43552; P9LE-NEXT: lfd f2, -16(r3)3553; P9LE-NEXT: lfd f1, -8(r3)3554; P9LE-NEXT: lfd f3, -24(r3)3555; P9LE-NEXT: xxmrghd vs0, vs2, vs03556; P9LE-NEXT: xvcvdpuxws v2, vs03557; P9LE-NEXT: xxmrghd vs0, vs3, vs13558; P9LE-NEXT: xvcvdpuxws v3, vs03559; P9LE-NEXT: vmrgew v2, v3, v23560; P9LE-NEXT: blr3561;3562; P8BE-LABEL: fromDiffMemVarDConvdtoui:3563; P8BE: # %bb.0: # %entry3564; P8BE-NEXT: sldi r4, r4, 33565; P8BE-NEXT: lfdux f0, r3, r43566; P8BE-NEXT: lfd f1, -8(r3)3567; P8BE-NEXT: lfd f2, -16(r3)3568; P8BE-NEXT: lfd f3, -24(r3)3569; P8BE-NEXT: xxmrghd vs1, vs1, vs33570; P8BE-NEXT: xxmrghd vs0, vs0, vs23571; P8BE-NEXT: xvcvdpuxws v2, vs13572; P8BE-NEXT: xvcvdpuxws v3, vs03573; P8BE-NEXT: vmrgew v2, v3, v23574; P8BE-NEXT: blr3575;3576; P8LE-LABEL: fromDiffMemVarDConvdtoui:3577; P8LE: # %bb.0: # %entry3578; P8LE-NEXT: sldi r4, r4, 33579; P8LE-NEXT: lfdux f0, r3, r43580; P8LE-NEXT: lfd f1, -8(r3)3581; P8LE-NEXT: lfd f2, -16(r3)3582; P8LE-NEXT: lfd f3, -24(r3)3583; P8LE-NEXT: xxmrghd vs0, vs2, vs03584; P8LE-NEXT: xxmrghd vs1, vs3, vs13585; P8LE-NEXT: xvcvdpuxws v2, vs03586; P8LE-NEXT: xvcvdpuxws v3, vs13587; P8LE-NEXT: vmrgew v2, v3, v23588; P8LE-NEXT: blr3589entry:3590 %idxprom = sext i32 %elem to i643591 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom3592 %0 = load double, ptr %arrayidx, align 83593 %conv = fptoui double %0 to i323594 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 03595 %sub = add nsw i32 %elem, -13596 %idxprom1 = sext i32 %sub to i643597 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom13598 %1 = load double, ptr %arrayidx2, align 83599 %conv3 = fptoui double %1 to i323600 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 13601 %sub5 = add nsw i32 %elem, -23602 %idxprom6 = sext i32 %sub5 to i643603 %arrayidx7 = getelementptr inbounds double, ptr %arr, i64 %idxprom63604 %2 = load double, ptr %arrayidx7, align 83605 %conv8 = fptoui double %2 to i323606 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 23607 %sub10 = add nsw i32 %elem, -33608 %idxprom11 = sext i32 %sub10 to i643609 %arrayidx12 = getelementptr inbounds double, ptr %arr, i64 %idxprom113610 %3 = load double, ptr %arrayidx12, align 83611 %conv13 = fptoui double %3 to i323612 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 33613 ret <4 x i32> %vecinit143614}3615 3616define <4 x i32> @spltRegValConvdtoui(double %val) {3617; P9BE-LABEL: spltRegValConvdtoui:3618; P9BE: # %bb.0: # %entry3619; P9BE-NEXT: xscvdpuxws f0, f13620; P9BE-NEXT: xxspltw v2, vs0, 13621; P9BE-NEXT: blr3622;3623; P9LE-LABEL: spltRegValConvdtoui:3624; P9LE: # %bb.0: # %entry3625; P9LE-NEXT: xscvdpuxws f0, f13626; P9LE-NEXT: xxspltw v2, vs0, 13627; P9LE-NEXT: blr3628;3629; P8BE-LABEL: spltRegValConvdtoui:3630; P8BE: # %bb.0: # %entry3631; P8BE-NEXT: xscvdpuxws f0, f13632; P8BE-NEXT: xxspltw v2, vs0, 13633; P8BE-NEXT: blr3634;3635; P8LE-LABEL: spltRegValConvdtoui:3636; P8LE: # %bb.0: # %entry3637; P8LE-NEXT: xscvdpuxws f0, f13638; P8LE-NEXT: xxspltw v2, vs0, 13639; P8LE-NEXT: blr3640entry:3641 %conv = fptoui double %val to i323642 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 03643 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer3644 ret <4 x i32> %splat.splat3645}3646 3647define <4 x i32> @spltMemValConvdtoui(ptr nocapture readonly %ptr) {3648; P9BE-LABEL: spltMemValConvdtoui:3649; P9BE: # %bb.0: # %entry3650; P9BE-NEXT: lfd f0, 0(r3)3651; P9BE-NEXT: xscvdpuxws f0, f03652; P9BE-NEXT: xxspltw v2, vs0, 13653; P9BE-NEXT: blr3654;3655; P9LE-LABEL: spltMemValConvdtoui:3656; P9LE: # %bb.0: # %entry3657; P9LE-NEXT: lfd f0, 0(r3)3658; P9LE-NEXT: xscvdpuxws f0, f03659; P9LE-NEXT: xxspltw v2, vs0, 13660; P9LE-NEXT: blr3661;3662; P8BE-LABEL: spltMemValConvdtoui:3663; P8BE: # %bb.0: # %entry3664; P8BE-NEXT: lfdx f0, 0, r33665; P8BE-NEXT: xscvdpuxws f0, f03666; P8BE-NEXT: xxspltw v2, vs0, 13667; P8BE-NEXT: blr3668;3669; P8LE-LABEL: spltMemValConvdtoui:3670; P8LE: # %bb.0: # %entry3671; P8LE-NEXT: lfdx f0, 0, r33672; P8LE-NEXT: xscvdpuxws f0, f03673; P8LE-NEXT: xxspltw v2, vs0, 13674; P8LE-NEXT: blr3675entry:3676 %0 = load double, ptr %ptr, align 83677 %conv = fptoui double %0 to i323678 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 03679 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer3680 ret <4 x i32> %splat.splat3681}3682 3683define <2 x i64> @allZeroll() {3684; P9BE-LABEL: allZeroll:3685; P9BE: # %bb.0: # %entry3686; P9BE-NEXT: xxlxor v2, v2, v23687; P9BE-NEXT: blr3688;3689; P9LE-LABEL: allZeroll:3690; P9LE: # %bb.0: # %entry3691; P9LE-NEXT: xxlxor v2, v2, v23692; P9LE-NEXT: blr3693;3694; P8BE-LABEL: allZeroll:3695; P8BE: # %bb.0: # %entry3696; P8BE-NEXT: xxlxor v2, v2, v23697; P8BE-NEXT: blr3698;3699; P8LE-LABEL: allZeroll:3700; P8LE: # %bb.0: # %entry3701; P8LE-NEXT: xxlxor v2, v2, v23702; P8LE-NEXT: blr3703entry:3704 ret <2 x i64> zeroinitializer3705}3706 3707define <2 x i64> @spltConst1ll() {3708; P9BE-LABEL: spltConst1ll:3709; P9BE: # %bb.0: # %entry3710; P9BE-NEXT: vspltisw v2, 13711; P9BE-NEXT: vupklsw v2, v23712; P9BE-NEXT: blr3713;3714; P9LE-LABEL: spltConst1ll:3715; P9LE: # %bb.0: # %entry3716; P9LE-NEXT: vspltisw v2, 13717; P9LE-NEXT: vupklsw v2, v23718; P9LE-NEXT: blr3719;3720; P8BE-LABEL: spltConst1ll:3721; P8BE: # %bb.0: # %entry3722; P8BE-NEXT: vspltisw v2, 13723; P8BE-NEXT: vupklsw v2, v23724; P8BE-NEXT: blr3725;3726; P8LE-LABEL: spltConst1ll:3727; P8LE: # %bb.0: # %entry3728; P8LE-NEXT: vspltisw v2, 13729; P8LE-NEXT: vupklsw v2, v23730; P8LE-NEXT: blr3731entry:3732 ret <2 x i64> <i64 1, i64 1>3733}3734 3735define <2 x i64> @spltConst16kll() {3736; P9BE-LABEL: spltConst16kll:3737; P9BE: # %bb.0: # %entry3738; P9BE-NEXT: addis r3, r2, .LCPI66_0@toc@ha3739; P9BE-NEXT: addi r3, r3, .LCPI66_0@toc@l3740; P9BE-NEXT: lxv v2, 0(r3)3741; P9BE-NEXT: blr3742;3743; P9LE-LABEL: spltConst16kll:3744; P9LE: # %bb.0: # %entry3745; P9LE-NEXT: addis r3, r2, .LCPI66_0@toc@ha3746; P9LE-NEXT: addi r3, r3, .LCPI66_0@toc@l3747; P9LE-NEXT: lxv v2, 0(r3)3748; P9LE-NEXT: blr3749;3750; P8BE-LABEL: spltConst16kll:3751; P8BE: # %bb.0: # %entry3752; P8BE-NEXT: addis r3, r2, .LCPI66_0@toc@ha3753; P8BE-NEXT: addi r3, r3, .LCPI66_0@toc@l3754; P8BE-NEXT: lxvd2x v2, 0, r33755; P8BE-NEXT: blr3756;3757; P8LE-LABEL: spltConst16kll:3758; P8LE: # %bb.0: # %entry3759; P8LE-NEXT: addis r3, r2, .LCPI66_0@toc@ha3760; P8LE-NEXT: addi r3, r3, .LCPI66_0@toc@l3761; P8LE-NEXT: lxvd2x v2, 0, r33762; P8LE-NEXT: blr3763entry:3764 ret <2 x i64> <i64 32767, i64 32767>3765}3766 3767define <2 x i64> @spltConst32kll() {3768; P9BE-LABEL: spltConst32kll:3769; P9BE: # %bb.0: # %entry3770; P9BE-NEXT: addis r3, r2, .LCPI67_0@toc@ha3771; P9BE-NEXT: addi r3, r3, .LCPI67_0@toc@l3772; P9BE-NEXT: lxv v2, 0(r3)3773; P9BE-NEXT: blr3774;3775; P9LE-LABEL: spltConst32kll:3776; P9LE: # %bb.0: # %entry3777; P9LE-NEXT: addis r3, r2, .LCPI67_0@toc@ha3778; P9LE-NEXT: addi r3, r3, .LCPI67_0@toc@l3779; P9LE-NEXT: lxv v2, 0(r3)3780; P9LE-NEXT: blr3781;3782; P8BE-LABEL: spltConst32kll:3783; P8BE: # %bb.0: # %entry3784; P8BE-NEXT: addis r3, r2, .LCPI67_0@toc@ha3785; P8BE-NEXT: addi r3, r3, .LCPI67_0@toc@l3786; P8BE-NEXT: lxvd2x v2, 0, r33787; P8BE-NEXT: blr3788;3789; P8LE-LABEL: spltConst32kll:3790; P8LE: # %bb.0: # %entry3791; P8LE-NEXT: addis r3, r2, .LCPI67_0@toc@ha3792; P8LE-NEXT: addi r3, r3, .LCPI67_0@toc@l3793; P8LE-NEXT: lxvd2x v2, 0, r33794; P8LE-NEXT: blr3795entry:3796 ret <2 x i64> <i64 65535, i64 65535>3797}3798 3799define <2 x i64> @fromRegsll(i64 %a, i64 %b) {3800; P9BE-LABEL: fromRegsll:3801; P9BE: # %bb.0: # %entry3802; P9BE-NEXT: mtvsrdd v2, r3, r43803; P9BE-NEXT: blr3804;3805; P9LE-LABEL: fromRegsll:3806; P9LE: # %bb.0: # %entry3807; P9LE-NEXT: mtvsrdd v2, r4, r33808; P9LE-NEXT: blr3809;3810; P8BE-LABEL: fromRegsll:3811; P8BE: # %bb.0: # %entry3812; P8BE-NEXT: mtfprd f0, r43813; P8BE-NEXT: mtfprd f1, r33814; P8BE-NEXT: xxmrghd v2, vs1, vs03815; P8BE-NEXT: blr3816;3817; P8LE-LABEL: fromRegsll:3818; P8LE: # %bb.0: # %entry3819; P8LE-NEXT: mtfprd f0, r33820; P8LE-NEXT: mtfprd f1, r43821; P8LE-NEXT: xxmrghd v2, vs1, vs03822; P8LE-NEXT: blr3823entry:3824 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 03825 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 13826 ret <2 x i64> %vecinit13827}3828 3829define <2 x i64> @fromDiffConstsll() {3830; P9BE-LABEL: fromDiffConstsll:3831; P9BE: # %bb.0: # %entry3832; P9BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha3833; P9BE-NEXT: addi r3, r3, .LCPI69_0@toc@l3834; P9BE-NEXT: lxv v2, 0(r3)3835; P9BE-NEXT: blr3836;3837; P9LE-LABEL: fromDiffConstsll:3838; P9LE: # %bb.0: # %entry3839; P9LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha3840; P9LE-NEXT: addi r3, r3, .LCPI69_0@toc@l3841; P9LE-NEXT: lxv v2, 0(r3)3842; P9LE-NEXT: blr3843;3844; P8BE-LABEL: fromDiffConstsll:3845; P8BE: # %bb.0: # %entry3846; P8BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha3847; P8BE-NEXT: addi r3, r3, .LCPI69_0@toc@l3848; P8BE-NEXT: lxvd2x v2, 0, r33849; P8BE-NEXT: blr3850;3851; P8LE-LABEL: fromDiffConstsll:3852; P8LE: # %bb.0: # %entry3853; P8LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha3854; P8LE-NEXT: addi r3, r3, .LCPI69_0@toc@l3855; P8LE-NEXT: lxvd2x vs0, 0, r33856; P8LE-NEXT: xxswapd v2, vs03857; P8LE-NEXT: blr3858entry:3859 ret <2 x i64> <i64 242, i64 -113>3860}3861 3862define <2 x i64> @fromDiffMemConsAll(ptr nocapture readonly %arr) {3863; P9BE-LABEL: fromDiffMemConsAll:3864; P9BE: # %bb.0: # %entry3865; P9BE-NEXT: lxv v2, 0(r3)3866; P9BE-NEXT: blr3867;3868; P9LE-LABEL: fromDiffMemConsAll:3869; P9LE: # %bb.0: # %entry3870; P9LE-NEXT: lxv v2, 0(r3)3871; P9LE-NEXT: blr3872;3873; P8BE-LABEL: fromDiffMemConsAll:3874; P8BE: # %bb.0: # %entry3875; P8BE-NEXT: lxvd2x v2, 0, r33876; P8BE-NEXT: blr3877;3878; P8LE-LABEL: fromDiffMemConsAll:3879; P8LE: # %bb.0: # %entry3880; P8LE-NEXT: lxvd2x vs0, 0, r33881; P8LE-NEXT: xxswapd v2, vs03882; P8LE-NEXT: blr3883entry:3884 %0 = load i64, ptr %arr, align 83885 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 03886 %arrayidx1 = getelementptr inbounds i64, ptr %arr, i64 13887 %1 = load i64, ptr %arrayidx1, align 83888 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 13889 ret <2 x i64> %vecinit23890}3891 3892define <2 x i64> @fromDiffMemConsDll(ptr nocapture readonly %arr) {3893; P9BE-LABEL: fromDiffMemConsDll:3894; P9BE: # %bb.0: # %entry3895; P9BE-NEXT: lxv v2, 16(r3)3896; P9BE-NEXT: xxswapd v2, v23897; P9BE-NEXT: blr3898;3899; P9LE-LABEL: fromDiffMemConsDll:3900; P9LE: # %bb.0: # %entry3901; P9LE-NEXT: addi r3, r3, 163902; P9LE-NEXT: lxvd2x v2, 0, r33903; P9LE-NEXT: blr3904;3905; P8BE-LABEL: fromDiffMemConsDll:3906; P8BE: # %bb.0: # %entry3907; P8BE-NEXT: addi r3, r3, 163908; P8BE-NEXT: lxvd2x v2, 0, r33909; P8BE-NEXT: xxswapd v2, v23910; P8BE-NEXT: blr3911;3912; P8LE-LABEL: fromDiffMemConsDll:3913; P8LE: # %bb.0: # %entry3914; P8LE-NEXT: addi r3, r3, 163915; P8LE-NEXT: lxvd2x v2, 0, r33916; P8LE-NEXT: blr3917entry:3918 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 33919 %0 = load i64, ptr %arrayidx, align 83920 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 03921 %arrayidx1 = getelementptr inbounds i64, ptr %arr, i64 23922 %1 = load i64, ptr %arrayidx1, align 83923 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 13924 ret <2 x i64> %vecinit23925}3926 3927define <2 x i64> @fromDiffMemVarAll(ptr nocapture readonly %arr, i32 signext %elem) {3928; P9BE-LABEL: fromDiffMemVarAll:3929; P9BE: # %bb.0: # %entry3930; P9BE-NEXT: sldi r4, r4, 33931; P9BE-NEXT: lxvx v2, r3, r43932; P9BE-NEXT: blr3933;3934; P9LE-LABEL: fromDiffMemVarAll:3935; P9LE: # %bb.0: # %entry3936; P9LE-NEXT: sldi r4, r4, 33937; P9LE-NEXT: lxvx v2, r3, r43938; P9LE-NEXT: blr3939;3940; P8BE-LABEL: fromDiffMemVarAll:3941; P8BE: # %bb.0: # %entry3942; P8BE-NEXT: sldi r4, r4, 33943; P8BE-NEXT: lxvd2x v2, r3, r43944; P8BE-NEXT: blr3945;3946; P8LE-LABEL: fromDiffMemVarAll:3947; P8LE: # %bb.0: # %entry3948; P8LE-NEXT: sldi r4, r4, 33949; P8LE-NEXT: lxvd2x vs0, r3, r43950; P8LE-NEXT: xxswapd v2, vs03951; P8LE-NEXT: blr3952entry:3953 %idxprom = sext i32 %elem to i643954 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 %idxprom3955 %0 = load i64, ptr %arrayidx, align 83956 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 03957 %add = add nsw i32 %elem, 13958 %idxprom1 = sext i32 %add to i643959 %arrayidx2 = getelementptr inbounds i64, ptr %arr, i64 %idxprom13960 %1 = load i64, ptr %arrayidx2, align 83961 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 13962 ret <2 x i64> %vecinit33963}3964 3965define <2 x i64> @fromDiffMemVarDll(ptr nocapture readonly %arr, i32 signext %elem) {3966; P9BE-LABEL: fromDiffMemVarDll:3967; P9BE: # %bb.0: # %entry3968; P9BE-NEXT: sldi r4, r4, 33969; P9BE-NEXT: add r3, r3, r43970; P9BE-NEXT: li r4, -83971; P9BE-NEXT: lxvx v2, r3, r43972; P9BE-NEXT: xxswapd v2, v23973; P9BE-NEXT: blr3974;3975; P9LE-LABEL: fromDiffMemVarDll:3976; P9LE: # %bb.0: # %entry3977; P9LE-NEXT: sldi r4, r4, 33978; P9LE-NEXT: add r3, r3, r43979; P9LE-NEXT: addi r3, r3, -83980; P9LE-NEXT: lxvd2x v2, 0, r33981; P9LE-NEXT: blr3982;3983; P8BE-LABEL: fromDiffMemVarDll:3984; P8BE: # %bb.0: # %entry3985; P8BE-NEXT: sldi r4, r4, 33986; P8BE-NEXT: add r3, r3, r43987; P8BE-NEXT: addi r3, r3, -83988; P8BE-NEXT: lxvd2x v2, 0, r33989; P8BE-NEXT: xxswapd v2, v23990; P8BE-NEXT: blr3991;3992; P8LE-LABEL: fromDiffMemVarDll:3993; P8LE: # %bb.0: # %entry3994; P8LE-NEXT: sldi r4, r4, 33995; P8LE-NEXT: add r3, r3, r43996; P8LE-NEXT: addi r3, r3, -83997; P8LE-NEXT: lxvd2x v2, 0, r33998; P8LE-NEXT: blr3999entry:4000 %idxprom = sext i32 %elem to i644001 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 %idxprom4002 %0 = load i64, ptr %arrayidx, align 84003 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 04004 %sub = add nsw i32 %elem, -14005 %idxprom1 = sext i32 %sub to i644006 %arrayidx2 = getelementptr inbounds i64, ptr %arr, i64 %idxprom14007 %1 = load i64, ptr %arrayidx2, align 84008 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 14009 ret <2 x i64> %vecinit34010}4011 4012define <2 x i64> @fromRandMemConsll(ptr nocapture readonly %arr) {4013; P9BE-LABEL: fromRandMemConsll:4014; P9BE: # %bb.0: # %entry4015; P9BE-NEXT: ld r4, 32(r3)4016; P9BE-NEXT: ld r3, 144(r3)4017; P9BE-NEXT: mtvsrdd v2, r4, r34018; P9BE-NEXT: blr4019;4020; P9LE-LABEL: fromRandMemConsll:4021; P9LE: # %bb.0: # %entry4022; P9LE-NEXT: ld r4, 32(r3)4023; P9LE-NEXT: ld r3, 144(r3)4024; P9LE-NEXT: mtvsrdd v2, r3, r44025; P9LE-NEXT: blr4026;4027; P8BE-LABEL: fromRandMemConsll:4028; P8BE: # %bb.0: # %entry4029; P8BE-NEXT: ld r4, 32(r3)4030; P8BE-NEXT: ld r3, 144(r3)4031; P8BE-NEXT: mtfprd f0, r34032; P8BE-NEXT: mtfprd f1, r44033; P8BE-NEXT: xxmrghd v2, vs1, vs04034; P8BE-NEXT: blr4035;4036; P8LE-LABEL: fromRandMemConsll:4037; P8LE: # %bb.0: # %entry4038; P8LE-NEXT: ld r4, 32(r3)4039; P8LE-NEXT: ld r3, 144(r3)4040; P8LE-NEXT: mtfprd f0, r44041; P8LE-NEXT: mtfprd f1, r34042; P8LE-NEXT: xxmrghd v2, vs1, vs04043; P8LE-NEXT: blr4044entry:4045 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 44046 %0 = load i64, ptr %arrayidx, align 84047 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 04048 %arrayidx1 = getelementptr inbounds i64, ptr %arr, i64 184049 %1 = load i64, ptr %arrayidx1, align 84050 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 14051 ret <2 x i64> %vecinit24052}4053 4054define <2 x i64> @fromRandMemVarll(ptr nocapture readonly %arr, i32 signext %elem) {4055; P9BE-LABEL: fromRandMemVarll:4056; P9BE: # %bb.0: # %entry4057; P9BE-NEXT: sldi r4, r4, 34058; P9BE-NEXT: add r3, r3, r44059; P9BE-NEXT: ld r4, 32(r3)4060; P9BE-NEXT: ld r3, 8(r3)4061; P9BE-NEXT: mtvsrdd v2, r4, r34062; P9BE-NEXT: blr4063;4064; P9LE-LABEL: fromRandMemVarll:4065; P9LE: # %bb.0: # %entry4066; P9LE-NEXT: sldi r4, r4, 34067; P9LE-NEXT: add r3, r3, r44068; P9LE-NEXT: ld r4, 32(r3)4069; P9LE-NEXT: ld r3, 8(r3)4070; P9LE-NEXT: mtvsrdd v2, r3, r44071; P9LE-NEXT: blr4072;4073; P8BE-LABEL: fromRandMemVarll:4074; P8BE: # %bb.0: # %entry4075; P8BE-NEXT: sldi r4, r4, 34076; P8BE-NEXT: add r3, r3, r44077; P8BE-NEXT: ld r4, 32(r3)4078; P8BE-NEXT: ld r3, 8(r3)4079; P8BE-NEXT: mtfprd f0, r34080; P8BE-NEXT: mtfprd f1, r44081; P8BE-NEXT: xxmrghd v2, vs1, vs04082; P8BE-NEXT: blr4083;4084; P8LE-LABEL: fromRandMemVarll:4085; P8LE: # %bb.0: # %entry4086; P8LE-NEXT: sldi r4, r4, 34087; P8LE-NEXT: add r3, r3, r44088; P8LE-NEXT: ld r4, 32(r3)4089; P8LE-NEXT: ld r3, 8(r3)4090; P8LE-NEXT: mtfprd f0, r44091; P8LE-NEXT: mtfprd f1, r34092; P8LE-NEXT: xxmrghd v2, vs1, vs04093; P8LE-NEXT: blr4094entry:4095 %add = add nsw i32 %elem, 44096 %idxprom = sext i32 %add to i644097 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 %idxprom4098 %0 = load i64, ptr %arrayidx, align 84099 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 04100 %add1 = add nsw i32 %elem, 14101 %idxprom2 = sext i32 %add1 to i644102 %arrayidx3 = getelementptr inbounds i64, ptr %arr, i64 %idxprom24103 %1 = load i64, ptr %arrayidx3, align 84104 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 14105 ret <2 x i64> %vecinit44106}4107 4108define <2 x i64> @spltRegValll(i64 %val) {4109; P9BE-LABEL: spltRegValll:4110; P9BE: # %bb.0: # %entry4111; P9BE-NEXT: mtvsrdd v2, r3, r34112; P9BE-NEXT: blr4113;4114; P9LE-LABEL: spltRegValll:4115; P9LE: # %bb.0: # %entry4116; P9LE-NEXT: mtvsrdd v2, r3, r34117; P9LE-NEXT: blr4118;4119; P8BE-LABEL: spltRegValll:4120; P8BE: # %bb.0: # %entry4121; P8BE-NEXT: mtfprd f0, r34122; P8BE-NEXT: xxspltd v2, vs0, 04123; P8BE-NEXT: blr4124;4125; P8LE-LABEL: spltRegValll:4126; P8LE: # %bb.0: # %entry4127; P8LE-NEXT: mtfprd f0, r34128; P8LE-NEXT: xxspltd v2, vs0, 04129; P8LE-NEXT: blr4130entry:4131 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 04132 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer4133 ret <2 x i64> %splat.splat4134}4135 4136define <2 x i64> @spltMemValll(ptr nocapture readonly %ptr) {4137; P9BE-LABEL: spltMemValll:4138; P9BE: # %bb.0: # %entry4139; P9BE-NEXT: lxvdsx v2, 0, r34140; P9BE-NEXT: blr4141;4142; P9LE-LABEL: spltMemValll:4143; P9LE: # %bb.0: # %entry4144; P9LE-NEXT: lxvdsx v2, 0, r34145; P9LE-NEXT: blr4146;4147; P8BE-LABEL: spltMemValll:4148; P8BE: # %bb.0: # %entry4149; P8BE-NEXT: lxvdsx v2, 0, r34150; P8BE-NEXT: blr4151;4152; P8LE-LABEL: spltMemValll:4153; P8LE: # %bb.0: # %entry4154; P8LE-NEXT: lxvdsx v2, 0, r34155; P8LE-NEXT: blr4156entry:4157 %0 = load i64, ptr %ptr, align 84158 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 04159 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer4160 ret <2 x i64> %splat.splat4161}4162 4163define <2 x i64> @spltCnstConvftoll() {4164; P9BE-LABEL: spltCnstConvftoll:4165; P9BE: # %bb.0: # %entry4166; P9BE-NEXT: vspltisw v2, 44167; P9BE-NEXT: vupklsw v2, v24168; P9BE-NEXT: blr4169;4170; P9LE-LABEL: spltCnstConvftoll:4171; P9LE: # %bb.0: # %entry4172; P9LE-NEXT: vspltisw v2, 44173; P9LE-NEXT: vupklsw v2, v24174; P9LE-NEXT: blr4175;4176; P8BE-LABEL: spltCnstConvftoll:4177; P8BE: # %bb.0: # %entry4178; P8BE-NEXT: vspltisw v2, 44179; P8BE-NEXT: vupklsw v2, v24180; P8BE-NEXT: blr4181;4182; P8LE-LABEL: spltCnstConvftoll:4183; P8LE: # %bb.0: # %entry4184; P8LE-NEXT: vspltisw v2, 44185; P8LE-NEXT: vupklsw v2, v24186; P8LE-NEXT: blr4187entry:4188 ret <2 x i64> <i64 4, i64 4>4189}4190 4191define <2 x i64> @fromRegsConvftoll(float %a, float %b) {4192; P9BE-LABEL: fromRegsConvftoll:4193; P9BE: # %bb.0: # %entry4194; P9BE-NEXT: xxmrghd vs0, vs1, vs24195; P9BE-NEXT: xvcvdpsxds v2, vs04196; P9BE-NEXT: blr4197;4198; P9LE-LABEL: fromRegsConvftoll:4199; P9LE: # %bb.0: # %entry4200; P9LE-NEXT: xxmrghd vs0, vs2, vs14201; P9LE-NEXT: xvcvdpsxds v2, vs04202; P9LE-NEXT: blr4203;4204; P8BE-LABEL: fromRegsConvftoll:4205; P8BE: # %bb.0: # %entry4206; P8BE-NEXT: xxmrghd vs0, vs1, vs24207; P8BE-NEXT: xvcvdpsxds v2, vs04208; P8BE-NEXT: blr4209;4210; P8LE-LABEL: fromRegsConvftoll:4211; P8LE: # %bb.0: # %entry4212; P8LE-NEXT: xxmrghd vs0, vs2, vs14213; P8LE-NEXT: xvcvdpsxds v2, vs04214; P8LE-NEXT: blr4215entry:4216 %conv = fptosi float %a to i644217 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 04218 %conv1 = fptosi float %b to i644219 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 14220 ret <2 x i64> %vecinit24221}4222 4223define <2 x i64> @fromDiffConstsConvftoll() {4224; P9BE-LABEL: fromDiffConstsConvftoll:4225; P9BE: # %bb.0: # %entry4226; P9BE-NEXT: addis r3, r2, .LCPI80_0@toc@ha4227; P9BE-NEXT: addi r3, r3, .LCPI80_0@toc@l4228; P9BE-NEXT: lxv v2, 0(r3)4229; P9BE-NEXT: blr4230;4231; P9LE-LABEL: fromDiffConstsConvftoll:4232; P9LE: # %bb.0: # %entry4233; P9LE-NEXT: addis r3, r2, .LCPI80_0@toc@ha4234; P9LE-NEXT: addi r3, r3, .LCPI80_0@toc@l4235; P9LE-NEXT: lxv v2, 0(r3)4236; P9LE-NEXT: blr4237;4238; P8BE-LABEL: fromDiffConstsConvftoll:4239; P8BE: # %bb.0: # %entry4240; P8BE-NEXT: addis r3, r2, .LCPI80_0@toc@ha4241; P8BE-NEXT: addi r3, r3, .LCPI80_0@toc@l4242; P8BE-NEXT: lxvd2x v2, 0, r34243; P8BE-NEXT: blr4244;4245; P8LE-LABEL: fromDiffConstsConvftoll:4246; P8LE: # %bb.0: # %entry4247; P8LE-NEXT: addis r3, r2, .LCPI80_0@toc@ha4248; P8LE-NEXT: addi r3, r3, .LCPI80_0@toc@l4249; P8LE-NEXT: lxvd2x vs0, 0, r34250; P8LE-NEXT: xxswapd v2, vs04251; P8LE-NEXT: blr4252entry:4253 ret <2 x i64> <i64 24, i64 234>4254}4255 4256define <2 x i64> @fromDiffMemConsAConvftoll(ptr nocapture readonly %ptr) {4257; P9BE-LABEL: fromDiffMemConsAConvftoll:4258; P9BE: # %bb.0: # %entry4259; P9BE-NEXT: lfs f0, 0(r3)4260; P9BE-NEXT: lfs f1, 4(r3)4261; P9BE-NEXT: xxmrghd vs0, vs0, vs14262; P9BE-NEXT: xvcvdpsxds v2, vs04263; P9BE-NEXT: blr4264;4265; P9LE-LABEL: fromDiffMemConsAConvftoll:4266; P9LE: # %bb.0: # %entry4267; P9LE-NEXT: lfs f0, 0(r3)4268; P9LE-NEXT: lfs f1, 4(r3)4269; P9LE-NEXT: xxmrghd vs0, vs1, vs04270; P9LE-NEXT: xvcvdpsxds v2, vs04271; P9LE-NEXT: blr4272;4273; P8BE-LABEL: fromDiffMemConsAConvftoll:4274; P8BE: # %bb.0: # %entry4275; P8BE-NEXT: lfs f0, 0(r3)4276; P8BE-NEXT: lfs f1, 4(r3)4277; P8BE-NEXT: xxmrghd vs0, vs0, vs14278; P8BE-NEXT: xvcvdpsxds v2, vs04279; P8BE-NEXT: blr4280;4281; P8LE-LABEL: fromDiffMemConsAConvftoll:4282; P8LE: # %bb.0: # %entry4283; P8LE-NEXT: lfs f0, 0(r3)4284; P8LE-NEXT: lfs f1, 4(r3)4285; P8LE-NEXT: xxmrghd vs0, vs1, vs04286; P8LE-NEXT: xvcvdpsxds v2, vs04287; P8LE-NEXT: blr4288entry:4289 %0 = load float, ptr %ptr, align 44290 %conv = fptosi float %0 to i644291 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 04292 %arrayidx1 = getelementptr inbounds float, ptr %ptr, i64 14293 %1 = load float, ptr %arrayidx1, align 44294 %conv2 = fptosi float %1 to i644295 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 14296 ret <2 x i64> %vecinit34297}4298 4299define <2 x i64> @fromDiffMemConsDConvftoll(ptr nocapture readonly %ptr) {4300; P9BE-LABEL: fromDiffMemConsDConvftoll:4301; P9BE: # %bb.0: # %entry4302; P9BE-NEXT: lfs f0, 12(r3)4303; P9BE-NEXT: lfs f1, 8(r3)4304; P9BE-NEXT: xxmrghd vs0, vs0, vs14305; P9BE-NEXT: xvcvdpsxds v2, vs04306; P9BE-NEXT: blr4307;4308; P9LE-LABEL: fromDiffMemConsDConvftoll:4309; P9LE: # %bb.0: # %entry4310; P9LE-NEXT: lfs f0, 12(r3)4311; P9LE-NEXT: lfs f1, 8(r3)4312; P9LE-NEXT: xxmrghd vs0, vs1, vs04313; P9LE-NEXT: xvcvdpsxds v2, vs04314; P9LE-NEXT: blr4315;4316; P8BE-LABEL: fromDiffMemConsDConvftoll:4317; P8BE: # %bb.0: # %entry4318; P8BE-NEXT: lfs f0, 12(r3)4319; P8BE-NEXT: lfs f1, 8(r3)4320; P8BE-NEXT: xxmrghd vs0, vs0, vs14321; P8BE-NEXT: xvcvdpsxds v2, vs04322; P8BE-NEXT: blr4323;4324; P8LE-LABEL: fromDiffMemConsDConvftoll:4325; P8LE: # %bb.0: # %entry4326; P8LE-NEXT: lfs f0, 12(r3)4327; P8LE-NEXT: lfs f1, 8(r3)4328; P8LE-NEXT: xxmrghd vs0, vs1, vs04329; P8LE-NEXT: xvcvdpsxds v2, vs04330; P8LE-NEXT: blr4331entry:4332 %arrayidx = getelementptr inbounds float, ptr %ptr, i64 34333 %0 = load float, ptr %arrayidx, align 44334 %conv = fptosi float %0 to i644335 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 04336 %arrayidx1 = getelementptr inbounds float, ptr %ptr, i64 24337 %1 = load float, ptr %arrayidx1, align 44338 %conv2 = fptosi float %1 to i644339 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 14340 ret <2 x i64> %vecinit34341}4342 4343define <2 x i64> @fromDiffMemVarAConvftoll(ptr nocapture readonly %arr, i32 signext %elem) {4344; P9BE-LABEL: fromDiffMemVarAConvftoll:4345; P9BE: # %bb.0: # %entry4346; P9BE-NEXT: sldi r4, r4, 24347; P9BE-NEXT: lfsux f0, r3, r44348; P9BE-NEXT: lfs f1, 4(r3)4349; P9BE-NEXT: xxmrghd vs0, vs0, vs14350; P9BE-NEXT: xvcvdpsxds v2, vs04351; P9BE-NEXT: blr4352;4353; P9LE-LABEL: fromDiffMemVarAConvftoll:4354; P9LE: # %bb.0: # %entry4355; P9LE-NEXT: sldi r4, r4, 24356; P9LE-NEXT: lfsux f0, r3, r44357; P9LE-NEXT: lfs f1, 4(r3)4358; P9LE-NEXT: xxmrghd vs0, vs1, vs04359; P9LE-NEXT: xvcvdpsxds v2, vs04360; P9LE-NEXT: blr4361;4362; P8BE-LABEL: fromDiffMemVarAConvftoll:4363; P8BE: # %bb.0: # %entry4364; P8BE-NEXT: sldi r4, r4, 24365; P8BE-NEXT: lfsux f0, r3, r44366; P8BE-NEXT: lfs f1, 4(r3)4367; P8BE-NEXT: xxmrghd vs0, vs0, vs14368; P8BE-NEXT: xvcvdpsxds v2, vs04369; P8BE-NEXT: blr4370;4371; P8LE-LABEL: fromDiffMemVarAConvftoll:4372; P8LE: # %bb.0: # %entry4373; P8LE-NEXT: sldi r4, r4, 24374; P8LE-NEXT: lfsux f0, r3, r44375; P8LE-NEXT: lfs f1, 4(r3)4376; P8LE-NEXT: xxmrghd vs0, vs1, vs04377; P8LE-NEXT: xvcvdpsxds v2, vs04378; P8LE-NEXT: blr4379entry:4380 %idxprom = sext i32 %elem to i644381 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom4382 %0 = load float, ptr %arrayidx, align 44383 %conv = fptosi float %0 to i644384 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 04385 %add = add nsw i32 %elem, 14386 %idxprom1 = sext i32 %add to i644387 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom14388 %1 = load float, ptr %arrayidx2, align 44389 %conv3 = fptosi float %1 to i644390 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 14391 ret <2 x i64> %vecinit44392}4393 4394define <2 x i64> @fromDiffMemVarDConvftoll(ptr nocapture readonly %arr, i32 signext %elem) {4395; P9BE-LABEL: fromDiffMemVarDConvftoll:4396; P9BE: # %bb.0: # %entry4397; P9BE-NEXT: sldi r4, r4, 24398; P9BE-NEXT: lfsux f0, r3, r44399; P9BE-NEXT: lfs f1, -4(r3)4400; P9BE-NEXT: xxmrghd vs0, vs0, vs14401; P9BE-NEXT: xvcvdpsxds v2, vs04402; P9BE-NEXT: blr4403;4404; P9LE-LABEL: fromDiffMemVarDConvftoll:4405; P9LE: # %bb.0: # %entry4406; P9LE-NEXT: sldi r4, r4, 24407; P9LE-NEXT: lfsux f0, r3, r44408; P9LE-NEXT: lfs f1, -4(r3)4409; P9LE-NEXT: xxmrghd vs0, vs1, vs04410; P9LE-NEXT: xvcvdpsxds v2, vs04411; P9LE-NEXT: blr4412;4413; P8BE-LABEL: fromDiffMemVarDConvftoll:4414; P8BE: # %bb.0: # %entry4415; P8BE-NEXT: sldi r4, r4, 24416; P8BE-NEXT: lfsux f0, r3, r44417; P8BE-NEXT: lfs f1, -4(r3)4418; P8BE-NEXT: xxmrghd vs0, vs0, vs14419; P8BE-NEXT: xvcvdpsxds v2, vs04420; P8BE-NEXT: blr4421;4422; P8LE-LABEL: fromDiffMemVarDConvftoll:4423; P8LE: # %bb.0: # %entry4424; P8LE-NEXT: sldi r4, r4, 24425; P8LE-NEXT: lfsux f0, r3, r44426; P8LE-NEXT: lfs f1, -4(r3)4427; P8LE-NEXT: xxmrghd vs0, vs1, vs04428; P8LE-NEXT: xvcvdpsxds v2, vs04429; P8LE-NEXT: blr4430entry:4431 %idxprom = sext i32 %elem to i644432 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom4433 %0 = load float, ptr %arrayidx, align 44434 %conv = fptosi float %0 to i644435 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 04436 %sub = add nsw i32 %elem, -14437 %idxprom1 = sext i32 %sub to i644438 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom14439 %1 = load float, ptr %arrayidx2, align 44440 %conv3 = fptosi float %1 to i644441 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 14442 ret <2 x i64> %vecinit44443}4444 4445define <2 x i64> @spltRegValConvftoll(float %val) {4446; P9BE-LABEL: spltRegValConvftoll:4447; P9BE: # %bb.0: # %entry4448; P9BE-NEXT: xscvdpsxds f0, f14449; P9BE-NEXT: xxspltd v2, f0, 04450; P9BE-NEXT: blr4451;4452; P9LE-LABEL: spltRegValConvftoll:4453; P9LE: # %bb.0: # %entry4454; P9LE-NEXT: xscvdpsxds f0, f14455; P9LE-NEXT: xxspltd v2, f0, 04456; P9LE-NEXT: blr4457;4458; P8BE-LABEL: spltRegValConvftoll:4459; P8BE: # %bb.0: # %entry4460; P8BE-NEXT: xscvdpsxds f0, f14461; P8BE-NEXT: xxspltd v2, f0, 04462; P8BE-NEXT: blr4463;4464; P8LE-LABEL: spltRegValConvftoll:4465; P8LE: # %bb.0: # %entry4466; P8LE-NEXT: xscvdpsxds f0, f14467; P8LE-NEXT: xxspltd v2, f0, 04468; P8LE-NEXT: blr4469entry:4470 %conv = fptosi float %val to i644471 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 04472 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer4473 ret <2 x i64> %splat.splat4474}4475 4476define <2 x i64> @spltMemValConvftoll(ptr nocapture readonly %ptr) {4477; P9BE-LABEL: spltMemValConvftoll:4478; P9BE: # %bb.0: # %entry4479; P9BE-NEXT: lfs f0, 0(r3)4480; P9BE-NEXT: xscvdpsxds f0, f04481; P9BE-NEXT: xxspltd v2, f0, 04482; P9BE-NEXT: blr4483;4484; P9LE-LABEL: spltMemValConvftoll:4485; P9LE: # %bb.0: # %entry4486; P9LE-NEXT: lfs f0, 0(r3)4487; P9LE-NEXT: xscvdpsxds f0, f04488; P9LE-NEXT: xxspltd v2, vs0, 04489; P9LE-NEXT: blr4490;4491; P8BE-LABEL: spltMemValConvftoll:4492; P8BE: # %bb.0: # %entry4493; P8BE-NEXT: lfsx f0, 0, r34494; P8BE-NEXT: xscvdpsxds f0, f04495; P8BE-NEXT: xxspltd v2, f0, 04496; P8BE-NEXT: blr4497;4498; P8LE-LABEL: spltMemValConvftoll:4499; P8LE: # %bb.0: # %entry4500; P8LE-NEXT: lfsx f0, 0, r34501; P8LE-NEXT: xscvdpsxds f0, f04502; P8LE-NEXT: xxspltd v2, vs0, 04503; P8LE-NEXT: blr4504entry:4505 %0 = load float, ptr %ptr, align 44506 %conv = fptosi float %0 to i644507 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 04508 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer4509 ret <2 x i64> %splat.splat4510}4511 4512define <2 x i64> @spltCnstConvdtoll() {4513; P9BE-LABEL: spltCnstConvdtoll:4514; P9BE: # %bb.0: # %entry4515; P9BE-NEXT: vspltisw v2, 44516; P9BE-NEXT: vupklsw v2, v24517; P9BE-NEXT: blr4518;4519; P9LE-LABEL: spltCnstConvdtoll:4520; P9LE: # %bb.0: # %entry4521; P9LE-NEXT: vspltisw v2, 44522; P9LE-NEXT: vupklsw v2, v24523; P9LE-NEXT: blr4524;4525; P8BE-LABEL: spltCnstConvdtoll:4526; P8BE: # %bb.0: # %entry4527; P8BE-NEXT: vspltisw v2, 44528; P8BE-NEXT: vupklsw v2, v24529; P8BE-NEXT: blr4530;4531; P8LE-LABEL: spltCnstConvdtoll:4532; P8LE: # %bb.0: # %entry4533; P8LE-NEXT: vspltisw v2, 44534; P8LE-NEXT: vupklsw v2, v24535; P8LE-NEXT: blr4536entry:4537 ret <2 x i64> <i64 4, i64 4>4538}4539 4540define <2 x i64> @fromRegsConvdtoll(double %a, double %b) {4541; P9BE-LABEL: fromRegsConvdtoll:4542; P9BE: # %bb.0: # %entry4543; P9BE-NEXT: xxmrghd vs0, vs1, vs24544; P9BE-NEXT: xvcvdpsxds v2, vs04545; P9BE-NEXT: blr4546;4547; P9LE-LABEL: fromRegsConvdtoll:4548; P9LE: # %bb.0: # %entry4549; P9LE-NEXT: xxmrghd vs0, vs2, vs14550; P9LE-NEXT: xvcvdpsxds v2, vs04551; P9LE-NEXT: blr4552;4553; P8BE-LABEL: fromRegsConvdtoll:4554; P8BE: # %bb.0: # %entry4555; P8BE-NEXT: xxmrghd vs0, vs1, vs24556; P8BE-NEXT: xvcvdpsxds v2, vs04557; P8BE-NEXT: blr4558;4559; P8LE-LABEL: fromRegsConvdtoll:4560; P8LE: # %bb.0: # %entry4561; P8LE-NEXT: xxmrghd vs0, vs2, vs14562; P8LE-NEXT: xvcvdpsxds v2, vs04563; P8LE-NEXT: blr4564entry:4565 %conv = fptosi double %a to i644566 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 04567 %conv1 = fptosi double %b to i644568 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 14569 ret <2 x i64> %vecinit24570}4571 4572define <2 x i64> @fromDiffConstsConvdtoll() {4573; P9BE-LABEL: fromDiffConstsConvdtoll:4574; P9BE: # %bb.0: # %entry4575; P9BE-NEXT: addis r3, r2, .LCPI89_0@toc@ha4576; P9BE-NEXT: addi r3, r3, .LCPI89_0@toc@l4577; P9BE-NEXT: lxv v2, 0(r3)4578; P9BE-NEXT: blr4579;4580; P9LE-LABEL: fromDiffConstsConvdtoll:4581; P9LE: # %bb.0: # %entry4582; P9LE-NEXT: addis r3, r2, .LCPI89_0@toc@ha4583; P9LE-NEXT: addi r3, r3, .LCPI89_0@toc@l4584; P9LE-NEXT: lxv v2, 0(r3)4585; P9LE-NEXT: blr4586;4587; P8BE-LABEL: fromDiffConstsConvdtoll:4588; P8BE: # %bb.0: # %entry4589; P8BE-NEXT: addis r3, r2, .LCPI89_0@toc@ha4590; P8BE-NEXT: addi r3, r3, .LCPI89_0@toc@l4591; P8BE-NEXT: lxvd2x v2, 0, r34592; P8BE-NEXT: blr4593;4594; P8LE-LABEL: fromDiffConstsConvdtoll:4595; P8LE: # %bb.0: # %entry4596; P8LE-NEXT: addis r3, r2, .LCPI89_0@toc@ha4597; P8LE-NEXT: addi r3, r3, .LCPI89_0@toc@l4598; P8LE-NEXT: lxvd2x vs0, 0, r34599; P8LE-NEXT: xxswapd v2, vs04600; P8LE-NEXT: blr4601entry:4602 ret <2 x i64> <i64 24, i64 234>4603}4604 4605define <2 x i64> @fromDiffMemConsAConvdtoll(ptr nocapture readonly %ptr) {4606; P9BE-LABEL: fromDiffMemConsAConvdtoll:4607; P9BE: # %bb.0: # %entry4608; P9BE-NEXT: lxv vs0, 0(r3)4609; P9BE-NEXT: xvcvdpsxds v2, vs04610; P9BE-NEXT: blr4611;4612; P9LE-LABEL: fromDiffMemConsAConvdtoll:4613; P9LE: # %bb.0: # %entry4614; P9LE-NEXT: lxv vs0, 0(r3)4615; P9LE-NEXT: xvcvdpsxds v2, vs04616; P9LE-NEXT: blr4617;4618; P8BE-LABEL: fromDiffMemConsAConvdtoll:4619; P8BE: # %bb.0: # %entry4620; P8BE-NEXT: lxvd2x vs0, 0, r34621; P8BE-NEXT: xvcvdpsxds v2, vs04622; P8BE-NEXT: blr4623;4624; P8LE-LABEL: fromDiffMemConsAConvdtoll:4625; P8LE: # %bb.0: # %entry4626; P8LE-NEXT: lxvd2x vs0, 0, r34627; P8LE-NEXT: xxswapd vs0, vs04628; P8LE-NEXT: xvcvdpsxds v2, vs04629; P8LE-NEXT: blr4630entry:4631 %0 = load <2 x double>, ptr %ptr, align 84632 %1 = fptosi <2 x double> %0 to <2 x i64>4633 ret <2 x i64> %14634}4635 4636define <2 x i64> @fromDiffMemConsDConvdtoll(ptr nocapture readonly %ptr) {4637; P9BE-LABEL: fromDiffMemConsDConvdtoll:4638; P9BE: # %bb.0: # %entry4639; P9BE-NEXT: lxv vs0, 16(r3)4640; P9BE-NEXT: xxswapd vs0, vs04641; P9BE-NEXT: xvcvdpsxds v2, vs04642; P9BE-NEXT: blr4643;4644; P9LE-LABEL: fromDiffMemConsDConvdtoll:4645; P9LE: # %bb.0: # %entry4646; P9LE-NEXT: addi r3, r3, 164647; P9LE-NEXT: lxvd2x vs0, 0, r34648; P9LE-NEXT: xvcvdpsxds v2, vs04649; P9LE-NEXT: blr4650;4651; P8BE-LABEL: fromDiffMemConsDConvdtoll:4652; P8BE: # %bb.0: # %entry4653; P8BE-NEXT: addi r3, r3, 164654; P8BE-NEXT: lxvd2x vs0, 0, r34655; P8BE-NEXT: xxswapd vs0, vs04656; P8BE-NEXT: xvcvdpsxds v2, vs04657; P8BE-NEXT: blr4658;4659; P8LE-LABEL: fromDiffMemConsDConvdtoll:4660; P8LE: # %bb.0: # %entry4661; P8LE-NEXT: addi r3, r3, 164662; P8LE-NEXT: lxvd2x vs0, 0, r34663; P8LE-NEXT: xvcvdpsxds v2, vs04664; P8LE-NEXT: blr4665entry:4666 %arrayidx = getelementptr inbounds double, ptr %ptr, i64 34667 %0 = load double, ptr %arrayidx, align 84668 %conv = fptosi double %0 to i644669 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 04670 %arrayidx1 = getelementptr inbounds double, ptr %ptr, i64 24671 %1 = load double, ptr %arrayidx1, align 84672 %conv2 = fptosi double %1 to i644673 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 14674 ret <2 x i64> %vecinit34675}4676 4677define <2 x i64> @fromDiffMemVarAConvdtoll(ptr nocapture readonly %arr, i32 signext %elem) {4678; P9BE-LABEL: fromDiffMemVarAConvdtoll:4679; P9BE: # %bb.0: # %entry4680; P9BE-NEXT: sldi r4, r4, 34681; P9BE-NEXT: lxvx vs0, r3, r44682; P9BE-NEXT: xvcvdpsxds v2, vs04683; P9BE-NEXT: blr4684;4685; P9LE-LABEL: fromDiffMemVarAConvdtoll:4686; P9LE: # %bb.0: # %entry4687; P9LE-NEXT: sldi r4, r4, 34688; P9LE-NEXT: lxvx vs0, r3, r44689; P9LE-NEXT: xvcvdpsxds v2, vs04690; P9LE-NEXT: blr4691;4692; P8BE-LABEL: fromDiffMemVarAConvdtoll:4693; P8BE: # %bb.0: # %entry4694; P8BE-NEXT: sldi r4, r4, 34695; P8BE-NEXT: lxvd2x vs0, r3, r44696; P8BE-NEXT: xvcvdpsxds v2, vs04697; P8BE-NEXT: blr4698;4699; P8LE-LABEL: fromDiffMemVarAConvdtoll:4700; P8LE: # %bb.0: # %entry4701; P8LE-NEXT: sldi r4, r4, 34702; P8LE-NEXT: lxvd2x vs0, r3, r44703; P8LE-NEXT: xxswapd vs0, vs04704; P8LE-NEXT: xvcvdpsxds v2, vs04705; P8LE-NEXT: blr4706entry:4707 %idxprom = sext i32 %elem to i644708 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom4709 %0 = load double, ptr %arrayidx, align 84710 %conv = fptosi double %0 to i644711 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 04712 %add = add nsw i32 %elem, 14713 %idxprom1 = sext i32 %add to i644714 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom14715 %1 = load double, ptr %arrayidx2, align 84716 %conv3 = fptosi double %1 to i644717 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 14718 ret <2 x i64> %vecinit44719}4720 4721define <2 x i64> @fromDiffMemVarDConvdtoll(ptr nocapture readonly %arr, i32 signext %elem) {4722; P9BE-LABEL: fromDiffMemVarDConvdtoll:4723; P9BE: # %bb.0: # %entry4724; P9BE-NEXT: sldi r4, r4, 34725; P9BE-NEXT: add r3, r3, r44726; P9BE-NEXT: li r4, -84727; P9BE-NEXT: lxvx vs0, r3, r44728; P9BE-NEXT: xxswapd vs0, vs04729; P9BE-NEXT: xvcvdpsxds v2, vs04730; P9BE-NEXT: blr4731;4732; P9LE-LABEL: fromDiffMemVarDConvdtoll:4733; P9LE: # %bb.0: # %entry4734; P9LE-NEXT: sldi r4, r4, 34735; P9LE-NEXT: add r3, r3, r44736; P9LE-NEXT: addi r3, r3, -84737; P9LE-NEXT: lxvd2x vs0, 0, r34738; P9LE-NEXT: xvcvdpsxds v2, vs04739; P9LE-NEXT: blr4740;4741; P8BE-LABEL: fromDiffMemVarDConvdtoll:4742; P8BE: # %bb.0: # %entry4743; P8BE-NEXT: sldi r4, r4, 34744; P8BE-NEXT: add r3, r3, r44745; P8BE-NEXT: addi r3, r3, -84746; P8BE-NEXT: lxvd2x vs0, 0, r34747; P8BE-NEXT: xxswapd vs0, vs04748; P8BE-NEXT: xvcvdpsxds v2, vs04749; P8BE-NEXT: blr4750;4751; P8LE-LABEL: fromDiffMemVarDConvdtoll:4752; P8LE: # %bb.0: # %entry4753; P8LE-NEXT: sldi r4, r4, 34754; P8LE-NEXT: add r3, r3, r44755; P8LE-NEXT: addi r3, r3, -84756; P8LE-NEXT: lxvd2x vs0, 0, r34757; P8LE-NEXT: xvcvdpsxds v2, vs04758; P8LE-NEXT: blr4759entry:4760 %idxprom = sext i32 %elem to i644761 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom4762 %0 = load double, ptr %arrayidx, align 84763 %conv = fptosi double %0 to i644764 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 04765 %sub = add nsw i32 %elem, -14766 %idxprom1 = sext i32 %sub to i644767 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom14768 %1 = load double, ptr %arrayidx2, align 84769 %conv3 = fptosi double %1 to i644770 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 14771 ret <2 x i64> %vecinit44772}4773 4774define <2 x i64> @spltRegValConvdtoll(double %val) {4775; P9BE-LABEL: spltRegValConvdtoll:4776; P9BE: # %bb.0: # %entry4777; P9BE-NEXT: xscvdpsxds f0, f14778; P9BE-NEXT: xxspltd v2, vs0, 04779; P9BE-NEXT: blr4780;4781; P9LE-LABEL: spltRegValConvdtoll:4782; P9LE: # %bb.0: # %entry4783; P9LE-NEXT: xscvdpsxds f0, f14784; P9LE-NEXT: xxspltd v2, vs0, 04785; P9LE-NEXT: blr4786;4787; P8BE-LABEL: spltRegValConvdtoll:4788; P8BE: # %bb.0: # %entry4789; P8BE-NEXT: xscvdpsxds f0, f14790; P8BE-NEXT: xxspltd v2, vs0, 04791; P8BE-NEXT: blr4792;4793; P8LE-LABEL: spltRegValConvdtoll:4794; P8LE: # %bb.0: # %entry4795; P8LE-NEXT: xscvdpsxds f0, f14796; P8LE-NEXT: xxspltd v2, vs0, 04797; P8LE-NEXT: blr4798entry:4799 %conv = fptosi double %val to i644800 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 04801 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer4802 ret <2 x i64> %splat.splat4803}4804 4805define <2 x i64> @spltMemValConvdtoll(ptr nocapture readonly %ptr) {4806; P9BE-LABEL: spltMemValConvdtoll:4807; P9BE: # %bb.0: # %entry4808; P9BE-NEXT: lxvdsx vs0, 0, r34809; P9BE-NEXT: xvcvdpsxds v2, vs04810; P9BE-NEXT: blr4811;4812; P9LE-LABEL: spltMemValConvdtoll:4813; P9LE: # %bb.0: # %entry4814; P9LE-NEXT: lxvdsx vs0, 0, r34815; P9LE-NEXT: xvcvdpsxds v2, vs04816; P9LE-NEXT: blr4817;4818; P8BE-LABEL: spltMemValConvdtoll:4819; P8BE: # %bb.0: # %entry4820; P8BE-NEXT: lxvdsx vs0, 0, r34821; P8BE-NEXT: xvcvdpsxds v2, vs04822; P8BE-NEXT: blr4823;4824; P8LE-LABEL: spltMemValConvdtoll:4825; P8LE: # %bb.0: # %entry4826; P8LE-NEXT: lxvdsx vs0, 0, r34827; P8LE-NEXT: xvcvdpsxds v2, vs04828; P8LE-NEXT: blr4829entry:4830 %0 = load double, ptr %ptr, align 84831 %conv = fptosi double %0 to i644832 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 04833 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer4834 ret <2 x i64> %splat.splat4835}4836 4837define <2 x i64> @allZeroull() {4838; P9BE-LABEL: allZeroull:4839; P9BE: # %bb.0: # %entry4840; P9BE-NEXT: xxlxor v2, v2, v24841; P9BE-NEXT: blr4842;4843; P9LE-LABEL: allZeroull:4844; P9LE: # %bb.0: # %entry4845; P9LE-NEXT: xxlxor v2, v2, v24846; P9LE-NEXT: blr4847;4848; P8BE-LABEL: allZeroull:4849; P8BE: # %bb.0: # %entry4850; P8BE-NEXT: xxlxor v2, v2, v24851; P8BE-NEXT: blr4852;4853; P8LE-LABEL: allZeroull:4854; P8LE: # %bb.0: # %entry4855; P8LE-NEXT: xxlxor v2, v2, v24856; P8LE-NEXT: blr4857entry:4858 ret <2 x i64> zeroinitializer4859}4860 4861define <2 x i64> @spltConst1ull() {4862; P9BE-LABEL: spltConst1ull:4863; P9BE: # %bb.0: # %entry4864; P9BE-NEXT: vspltisw v2, 14865; P9BE-NEXT: vupklsw v2, v24866; P9BE-NEXT: blr4867;4868; P9LE-LABEL: spltConst1ull:4869; P9LE: # %bb.0: # %entry4870; P9LE-NEXT: vspltisw v2, 14871; P9LE-NEXT: vupklsw v2, v24872; P9LE-NEXT: blr4873;4874; P8BE-LABEL: spltConst1ull:4875; P8BE: # %bb.0: # %entry4876; P8BE-NEXT: vspltisw v2, 14877; P8BE-NEXT: vupklsw v2, v24878; P8BE-NEXT: blr4879;4880; P8LE-LABEL: spltConst1ull:4881; P8LE: # %bb.0: # %entry4882; P8LE-NEXT: vspltisw v2, 14883; P8LE-NEXT: vupklsw v2, v24884; P8LE-NEXT: blr4885entry:4886 ret <2 x i64> <i64 1, i64 1>4887}4888 4889define <2 x i64> @spltConst16kull() {4890; P9BE-LABEL: spltConst16kull:4891; P9BE: # %bb.0: # %entry4892; P9BE-NEXT: addis r3, r2, .LCPI98_0@toc@ha4893; P9BE-NEXT: addi r3, r3, .LCPI98_0@toc@l4894; P9BE-NEXT: lxv v2, 0(r3)4895; P9BE-NEXT: blr4896;4897; P9LE-LABEL: spltConst16kull:4898; P9LE: # %bb.0: # %entry4899; P9LE-NEXT: addis r3, r2, .LCPI98_0@toc@ha4900; P9LE-NEXT: addi r3, r3, .LCPI98_0@toc@l4901; P9LE-NEXT: lxv v2, 0(r3)4902; P9LE-NEXT: blr4903;4904; P8BE-LABEL: spltConst16kull:4905; P8BE: # %bb.0: # %entry4906; P8BE-NEXT: addis r3, r2, .LCPI98_0@toc@ha4907; P8BE-NEXT: addi r3, r3, .LCPI98_0@toc@l4908; P8BE-NEXT: lxvd2x v2, 0, r34909; P8BE-NEXT: blr4910;4911; P8LE-LABEL: spltConst16kull:4912; P8LE: # %bb.0: # %entry4913; P8LE-NEXT: addis r3, r2, .LCPI98_0@toc@ha4914; P8LE-NEXT: addi r3, r3, .LCPI98_0@toc@l4915; P8LE-NEXT: lxvd2x v2, 0, r34916; P8LE-NEXT: blr4917entry:4918 ret <2 x i64> <i64 32767, i64 32767>4919}4920 4921define <2 x i64> @spltConst32kull() {4922; P9BE-LABEL: spltConst32kull:4923; P9BE: # %bb.0: # %entry4924; P9BE-NEXT: addis r3, r2, .LCPI99_0@toc@ha4925; P9BE-NEXT: addi r3, r3, .LCPI99_0@toc@l4926; P9BE-NEXT: lxv v2, 0(r3)4927; P9BE-NEXT: blr4928;4929; P9LE-LABEL: spltConst32kull:4930; P9LE: # %bb.0: # %entry4931; P9LE-NEXT: addis r3, r2, .LCPI99_0@toc@ha4932; P9LE-NEXT: addi r3, r3, .LCPI99_0@toc@l4933; P9LE-NEXT: lxv v2, 0(r3)4934; P9LE-NEXT: blr4935;4936; P8BE-LABEL: spltConst32kull:4937; P8BE: # %bb.0: # %entry4938; P8BE-NEXT: addis r3, r2, .LCPI99_0@toc@ha4939; P8BE-NEXT: addi r3, r3, .LCPI99_0@toc@l4940; P8BE-NEXT: lxvd2x v2, 0, r34941; P8BE-NEXT: blr4942;4943; P8LE-LABEL: spltConst32kull:4944; P8LE: # %bb.0: # %entry4945; P8LE-NEXT: addis r3, r2, .LCPI99_0@toc@ha4946; P8LE-NEXT: addi r3, r3, .LCPI99_0@toc@l4947; P8LE-NEXT: lxvd2x v2, 0, r34948; P8LE-NEXT: blr4949entry:4950 ret <2 x i64> <i64 65535, i64 65535>4951}4952 4953define <2 x i64> @fromRegsull(i64 %a, i64 %b) {4954; P9BE-LABEL: fromRegsull:4955; P9BE: # %bb.0: # %entry4956; P9BE-NEXT: mtvsrdd v2, r3, r44957; P9BE-NEXT: blr4958;4959; P9LE-LABEL: fromRegsull:4960; P9LE: # %bb.0: # %entry4961; P9LE-NEXT: mtvsrdd v2, r4, r34962; P9LE-NEXT: blr4963;4964; P8BE-LABEL: fromRegsull:4965; P8BE: # %bb.0: # %entry4966; P8BE-NEXT: mtfprd f0, r44967; P8BE-NEXT: mtfprd f1, r34968; P8BE-NEXT: xxmrghd v2, vs1, vs04969; P8BE-NEXT: blr4970;4971; P8LE-LABEL: fromRegsull:4972; P8LE: # %bb.0: # %entry4973; P8LE-NEXT: mtfprd f0, r34974; P8LE-NEXT: mtfprd f1, r44975; P8LE-NEXT: xxmrghd v2, vs1, vs04976; P8LE-NEXT: blr4977entry:4978 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 04979 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 14980 ret <2 x i64> %vecinit14981}4982 4983define <2 x i64> @fromDiffConstsull() {4984; P9BE-LABEL: fromDiffConstsull:4985; P9BE: # %bb.0: # %entry4986; P9BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha4987; P9BE-NEXT: addi r3, r3, .LCPI101_0@toc@l4988; P9BE-NEXT: lxv v2, 0(r3)4989; P9BE-NEXT: blr4990;4991; P9LE-LABEL: fromDiffConstsull:4992; P9LE: # %bb.0: # %entry4993; P9LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha4994; P9LE-NEXT: addi r3, r3, .LCPI101_0@toc@l4995; P9LE-NEXT: lxv v2, 0(r3)4996; P9LE-NEXT: blr4997;4998; P8BE-LABEL: fromDiffConstsull:4999; P8BE: # %bb.0: # %entry5000; P8BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha5001; P8BE-NEXT: addi r3, r3, .LCPI101_0@toc@l5002; P8BE-NEXT: lxvd2x v2, 0, r35003; P8BE-NEXT: blr5004;5005; P8LE-LABEL: fromDiffConstsull:5006; P8LE: # %bb.0: # %entry5007; P8LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha5008; P8LE-NEXT: addi r3, r3, .LCPI101_0@toc@l5009; P8LE-NEXT: lxvd2x vs0, 0, r35010; P8LE-NEXT: xxswapd v2, vs05011; P8LE-NEXT: blr5012entry:5013 ret <2 x i64> <i64 242, i64 -113>5014}5015 5016define <2 x i64> @fromDiffMemConsAull(ptr nocapture readonly %arr) {5017; P9BE-LABEL: fromDiffMemConsAull:5018; P9BE: # %bb.0: # %entry5019; P9BE-NEXT: lxv v2, 0(r3)5020; P9BE-NEXT: blr5021;5022; P9LE-LABEL: fromDiffMemConsAull:5023; P9LE: # %bb.0: # %entry5024; P9LE-NEXT: lxv v2, 0(r3)5025; P9LE-NEXT: blr5026;5027; P8BE-LABEL: fromDiffMemConsAull:5028; P8BE: # %bb.0: # %entry5029; P8BE-NEXT: lxvd2x v2, 0, r35030; P8BE-NEXT: blr5031;5032; P8LE-LABEL: fromDiffMemConsAull:5033; P8LE: # %bb.0: # %entry5034; P8LE-NEXT: lxvd2x vs0, 0, r35035; P8LE-NEXT: xxswapd v2, vs05036; P8LE-NEXT: blr5037entry:5038 %0 = load i64, ptr %arr, align 85039 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 05040 %arrayidx1 = getelementptr inbounds i64, ptr %arr, i64 15041 %1 = load i64, ptr %arrayidx1, align 85042 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 15043 ret <2 x i64> %vecinit25044}5045 5046define <2 x i64> @fromDiffMemConsDull(ptr nocapture readonly %arr) {5047; P9BE-LABEL: fromDiffMemConsDull:5048; P9BE: # %bb.0: # %entry5049; P9BE-NEXT: lxv v2, 16(r3)5050; P9BE-NEXT: xxswapd v2, v25051; P9BE-NEXT: blr5052;5053; P9LE-LABEL: fromDiffMemConsDull:5054; P9LE: # %bb.0: # %entry5055; P9LE-NEXT: addi r3, r3, 165056; P9LE-NEXT: lxvd2x v2, 0, r35057; P9LE-NEXT: blr5058;5059; P8BE-LABEL: fromDiffMemConsDull:5060; P8BE: # %bb.0: # %entry5061; P8BE-NEXT: addi r3, r3, 165062; P8BE-NEXT: lxvd2x v2, 0, r35063; P8BE-NEXT: xxswapd v2, v25064; P8BE-NEXT: blr5065;5066; P8LE-LABEL: fromDiffMemConsDull:5067; P8LE: # %bb.0: # %entry5068; P8LE-NEXT: addi r3, r3, 165069; P8LE-NEXT: lxvd2x v2, 0, r35070; P8LE-NEXT: blr5071entry:5072 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 35073 %0 = load i64, ptr %arrayidx, align 85074 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 05075 %arrayidx1 = getelementptr inbounds i64, ptr %arr, i64 25076 %1 = load i64, ptr %arrayidx1, align 85077 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 15078 ret <2 x i64> %vecinit25079}5080 5081define <2 x i64> @fromDiffMemVarAull(ptr nocapture readonly %arr, i32 signext %elem) {5082; P9BE-LABEL: fromDiffMemVarAull:5083; P9BE: # %bb.0: # %entry5084; P9BE-NEXT: sldi r4, r4, 35085; P9BE-NEXT: lxvx v2, r3, r45086; P9BE-NEXT: blr5087;5088; P9LE-LABEL: fromDiffMemVarAull:5089; P9LE: # %bb.0: # %entry5090; P9LE-NEXT: sldi r4, r4, 35091; P9LE-NEXT: lxvx v2, r3, r45092; P9LE-NEXT: blr5093;5094; P8BE-LABEL: fromDiffMemVarAull:5095; P8BE: # %bb.0: # %entry5096; P8BE-NEXT: sldi r4, r4, 35097; P8BE-NEXT: lxvd2x v2, r3, r45098; P8BE-NEXT: blr5099;5100; P8LE-LABEL: fromDiffMemVarAull:5101; P8LE: # %bb.0: # %entry5102; P8LE-NEXT: sldi r4, r4, 35103; P8LE-NEXT: lxvd2x vs0, r3, r45104; P8LE-NEXT: xxswapd v2, vs05105; P8LE-NEXT: blr5106entry:5107 %idxprom = sext i32 %elem to i645108 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 %idxprom5109 %0 = load i64, ptr %arrayidx, align 85110 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 05111 %add = add nsw i32 %elem, 15112 %idxprom1 = sext i32 %add to i645113 %arrayidx2 = getelementptr inbounds i64, ptr %arr, i64 %idxprom15114 %1 = load i64, ptr %arrayidx2, align 85115 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 15116 ret <2 x i64> %vecinit35117}5118 5119define <2 x i64> @fromDiffMemVarDull(ptr nocapture readonly %arr, i32 signext %elem) {5120; P9BE-LABEL: fromDiffMemVarDull:5121; P9BE: # %bb.0: # %entry5122; P9BE-NEXT: sldi r4, r4, 35123; P9BE-NEXT: add r3, r3, r45124; P9BE-NEXT: li r4, -85125; P9BE-NEXT: lxvx v2, r3, r45126; P9BE-NEXT: xxswapd v2, v25127; P9BE-NEXT: blr5128;5129; P9LE-LABEL: fromDiffMemVarDull:5130; P9LE: # %bb.0: # %entry5131; P9LE-NEXT: sldi r4, r4, 35132; P9LE-NEXT: add r3, r3, r45133; P9LE-NEXT: addi r3, r3, -85134; P9LE-NEXT: lxvd2x v2, 0, r35135; P9LE-NEXT: blr5136;5137; P8BE-LABEL: fromDiffMemVarDull:5138; P8BE: # %bb.0: # %entry5139; P8BE-NEXT: sldi r4, r4, 35140; P8BE-NEXT: add r3, r3, r45141; P8BE-NEXT: addi r3, r3, -85142; P8BE-NEXT: lxvd2x v2, 0, r35143; P8BE-NEXT: xxswapd v2, v25144; P8BE-NEXT: blr5145;5146; P8LE-LABEL: fromDiffMemVarDull:5147; P8LE: # %bb.0: # %entry5148; P8LE-NEXT: sldi r4, r4, 35149; P8LE-NEXT: add r3, r3, r45150; P8LE-NEXT: addi r3, r3, -85151; P8LE-NEXT: lxvd2x v2, 0, r35152; P8LE-NEXT: blr5153entry:5154 %idxprom = sext i32 %elem to i645155 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 %idxprom5156 %0 = load i64, ptr %arrayidx, align 85157 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 05158 %sub = add nsw i32 %elem, -15159 %idxprom1 = sext i32 %sub to i645160 %arrayidx2 = getelementptr inbounds i64, ptr %arr, i64 %idxprom15161 %1 = load i64, ptr %arrayidx2, align 85162 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 15163 ret <2 x i64> %vecinit35164}5165 5166define <2 x i64> @fromRandMemConsull(ptr nocapture readonly %arr) {5167; P9BE-LABEL: fromRandMemConsull:5168; P9BE: # %bb.0: # %entry5169; P9BE-NEXT: ld r4, 32(r3)5170; P9BE-NEXT: ld r3, 144(r3)5171; P9BE-NEXT: mtvsrdd v2, r4, r35172; P9BE-NEXT: blr5173;5174; P9LE-LABEL: fromRandMemConsull:5175; P9LE: # %bb.0: # %entry5176; P9LE-NEXT: ld r4, 32(r3)5177; P9LE-NEXT: ld r3, 144(r3)5178; P9LE-NEXT: mtvsrdd v2, r3, r45179; P9LE-NEXT: blr5180;5181; P8BE-LABEL: fromRandMemConsull:5182; P8BE: # %bb.0: # %entry5183; P8BE-NEXT: ld r4, 32(r3)5184; P8BE-NEXT: ld r3, 144(r3)5185; P8BE-NEXT: mtfprd f0, r35186; P8BE-NEXT: mtfprd f1, r45187; P8BE-NEXT: xxmrghd v2, vs1, vs05188; P8BE-NEXT: blr5189;5190; P8LE-LABEL: fromRandMemConsull:5191; P8LE: # %bb.0: # %entry5192; P8LE-NEXT: ld r4, 32(r3)5193; P8LE-NEXT: ld r3, 144(r3)5194; P8LE-NEXT: mtfprd f0, r45195; P8LE-NEXT: mtfprd f1, r35196; P8LE-NEXT: xxmrghd v2, vs1, vs05197; P8LE-NEXT: blr5198entry:5199 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 45200 %0 = load i64, ptr %arrayidx, align 85201 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 05202 %arrayidx1 = getelementptr inbounds i64, ptr %arr, i64 185203 %1 = load i64, ptr %arrayidx1, align 85204 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 15205 ret <2 x i64> %vecinit25206}5207 5208define <2 x i64> @fromRandMemVarull(ptr nocapture readonly %arr, i32 signext %elem) {5209; P9BE-LABEL: fromRandMemVarull:5210; P9BE: # %bb.0: # %entry5211; P9BE-NEXT: sldi r4, r4, 35212; P9BE-NEXT: add r3, r3, r45213; P9BE-NEXT: ld r4, 32(r3)5214; P9BE-NEXT: ld r3, 8(r3)5215; P9BE-NEXT: mtvsrdd v2, r4, r35216; P9BE-NEXT: blr5217;5218; P9LE-LABEL: fromRandMemVarull:5219; P9LE: # %bb.0: # %entry5220; P9LE-NEXT: sldi r4, r4, 35221; P9LE-NEXT: add r3, r3, r45222; P9LE-NEXT: ld r4, 32(r3)5223; P9LE-NEXT: ld r3, 8(r3)5224; P9LE-NEXT: mtvsrdd v2, r3, r45225; P9LE-NEXT: blr5226;5227; P8BE-LABEL: fromRandMemVarull:5228; P8BE: # %bb.0: # %entry5229; P8BE-NEXT: sldi r4, r4, 35230; P8BE-NEXT: add r3, r3, r45231; P8BE-NEXT: ld r4, 32(r3)5232; P8BE-NEXT: ld r3, 8(r3)5233; P8BE-NEXT: mtfprd f0, r35234; P8BE-NEXT: mtfprd f1, r45235; P8BE-NEXT: xxmrghd v2, vs1, vs05236; P8BE-NEXT: blr5237;5238; P8LE-LABEL: fromRandMemVarull:5239; P8LE: # %bb.0: # %entry5240; P8LE-NEXT: sldi r4, r4, 35241; P8LE-NEXT: add r3, r3, r45242; P8LE-NEXT: ld r4, 32(r3)5243; P8LE-NEXT: ld r3, 8(r3)5244; P8LE-NEXT: mtfprd f0, r45245; P8LE-NEXT: mtfprd f1, r35246; P8LE-NEXT: xxmrghd v2, vs1, vs05247; P8LE-NEXT: blr5248entry:5249 %add = add nsw i32 %elem, 45250 %idxprom = sext i32 %add to i645251 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 %idxprom5252 %0 = load i64, ptr %arrayidx, align 85253 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 05254 %add1 = add nsw i32 %elem, 15255 %idxprom2 = sext i32 %add1 to i645256 %arrayidx3 = getelementptr inbounds i64, ptr %arr, i64 %idxprom25257 %1 = load i64, ptr %arrayidx3, align 85258 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 15259 ret <2 x i64> %vecinit45260}5261 5262define <2 x i64> @spltRegValull(i64 %val) {5263; P9BE-LABEL: spltRegValull:5264; P9BE: # %bb.0: # %entry5265; P9BE-NEXT: mtvsrdd v2, r3, r35266; P9BE-NEXT: blr5267;5268; P9LE-LABEL: spltRegValull:5269; P9LE: # %bb.0: # %entry5270; P9LE-NEXT: mtvsrdd v2, r3, r35271; P9LE-NEXT: blr5272;5273; P8BE-LABEL: spltRegValull:5274; P8BE: # %bb.0: # %entry5275; P8BE-NEXT: mtfprd f0, r35276; P8BE-NEXT: xxspltd v2, vs0, 05277; P8BE-NEXT: blr5278;5279; P8LE-LABEL: spltRegValull:5280; P8LE: # %bb.0: # %entry5281; P8LE-NEXT: mtfprd f0, r35282; P8LE-NEXT: xxspltd v2, vs0, 05283; P8LE-NEXT: blr5284entry:5285 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 05286 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer5287 ret <2 x i64> %splat.splat5288}5289 5290define <2 x i64> @spltMemValull(ptr nocapture readonly %ptr) {5291; P9BE-LABEL: spltMemValull:5292; P9BE: # %bb.0: # %entry5293; P9BE-NEXT: lxvdsx v2, 0, r35294; P9BE-NEXT: blr5295;5296; P9LE-LABEL: spltMemValull:5297; P9LE: # %bb.0: # %entry5298; P9LE-NEXT: lxvdsx v2, 0, r35299; P9LE-NEXT: blr5300;5301; P8BE-LABEL: spltMemValull:5302; P8BE: # %bb.0: # %entry5303; P8BE-NEXT: lxvdsx v2, 0, r35304; P8BE-NEXT: blr5305;5306; P8LE-LABEL: spltMemValull:5307; P8LE: # %bb.0: # %entry5308; P8LE-NEXT: lxvdsx v2, 0, r35309; P8LE-NEXT: blr5310entry:5311 %0 = load i64, ptr %ptr, align 85312 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 05313 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer5314 ret <2 x i64> %splat.splat5315}5316 5317define <2 x i64> @spltCnstConvftoull() {5318; P9BE-LABEL: spltCnstConvftoull:5319; P9BE: # %bb.0: # %entry5320; P9BE-NEXT: vspltisw v2, 45321; P9BE-NEXT: vupklsw v2, v25322; P9BE-NEXT: blr5323;5324; P9LE-LABEL: spltCnstConvftoull:5325; P9LE: # %bb.0: # %entry5326; P9LE-NEXT: vspltisw v2, 45327; P9LE-NEXT: vupklsw v2, v25328; P9LE-NEXT: blr5329;5330; P8BE-LABEL: spltCnstConvftoull:5331; P8BE: # %bb.0: # %entry5332; P8BE-NEXT: vspltisw v2, 45333; P8BE-NEXT: vupklsw v2, v25334; P8BE-NEXT: blr5335;5336; P8LE-LABEL: spltCnstConvftoull:5337; P8LE: # %bb.0: # %entry5338; P8LE-NEXT: vspltisw v2, 45339; P8LE-NEXT: vupklsw v2, v25340; P8LE-NEXT: blr5341entry:5342 ret <2 x i64> <i64 4, i64 4>5343}5344 5345define <2 x i64> @fromRegsConvftoull(float %a, float %b) {5346; P9BE-LABEL: fromRegsConvftoull:5347; P9BE: # %bb.0: # %entry5348; P9BE-NEXT: xxmrghd vs0, vs1, vs25349; P9BE-NEXT: xvcvdpuxds v2, vs05350; P9BE-NEXT: blr5351;5352; P9LE-LABEL: fromRegsConvftoull:5353; P9LE: # %bb.0: # %entry5354; P9LE-NEXT: xxmrghd vs0, vs2, vs15355; P9LE-NEXT: xvcvdpuxds v2, vs05356; P9LE-NEXT: blr5357;5358; P8BE-LABEL: fromRegsConvftoull:5359; P8BE: # %bb.0: # %entry5360; P8BE-NEXT: xxmrghd vs0, vs1, vs25361; P8BE-NEXT: xvcvdpuxds v2, vs05362; P8BE-NEXT: blr5363;5364; P8LE-LABEL: fromRegsConvftoull:5365; P8LE: # %bb.0: # %entry5366; P8LE-NEXT: xxmrghd vs0, vs2, vs15367; P8LE-NEXT: xvcvdpuxds v2, vs05368; P8LE-NEXT: blr5369entry:5370 %conv = fptoui float %a to i645371 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 05372 %conv1 = fptoui float %b to i645373 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 15374 ret <2 x i64> %vecinit25375}5376 5377define <2 x i64> @fromDiffConstsConvftoull() {5378; P9BE-LABEL: fromDiffConstsConvftoull:5379; P9BE: # %bb.0: # %entry5380; P9BE-NEXT: addis r3, r2, .LCPI112_0@toc@ha5381; P9BE-NEXT: addi r3, r3, .LCPI112_0@toc@l5382; P9BE-NEXT: lxv v2, 0(r3)5383; P9BE-NEXT: blr5384;5385; P9LE-LABEL: fromDiffConstsConvftoull:5386; P9LE: # %bb.0: # %entry5387; P9LE-NEXT: addis r3, r2, .LCPI112_0@toc@ha5388; P9LE-NEXT: addi r3, r3, .LCPI112_0@toc@l5389; P9LE-NEXT: lxv v2, 0(r3)5390; P9LE-NEXT: blr5391;5392; P8BE-LABEL: fromDiffConstsConvftoull:5393; P8BE: # %bb.0: # %entry5394; P8BE-NEXT: addis r3, r2, .LCPI112_0@toc@ha5395; P8BE-NEXT: addi r3, r3, .LCPI112_0@toc@l5396; P8BE-NEXT: lxvd2x v2, 0, r35397; P8BE-NEXT: blr5398;5399; P8LE-LABEL: fromDiffConstsConvftoull:5400; P8LE: # %bb.0: # %entry5401; P8LE-NEXT: addis r3, r2, .LCPI112_0@toc@ha5402; P8LE-NEXT: addi r3, r3, .LCPI112_0@toc@l5403; P8LE-NEXT: lxvd2x vs0, 0, r35404; P8LE-NEXT: xxswapd v2, vs05405; P8LE-NEXT: blr5406entry:5407 ret <2 x i64> <i64 24, i64 234>5408}5409 5410define <2 x i64> @fromDiffMemConsAConvftoull(ptr nocapture readonly %ptr) {5411; P9BE-LABEL: fromDiffMemConsAConvftoull:5412; P9BE: # %bb.0: # %entry5413; P9BE-NEXT: lfs f0, 0(r3)5414; P9BE-NEXT: lfs f1, 4(r3)5415; P9BE-NEXT: xxmrghd vs0, vs0, vs15416; P9BE-NEXT: xvcvdpuxds v2, vs05417; P9BE-NEXT: blr5418;5419; P9LE-LABEL: fromDiffMemConsAConvftoull:5420; P9LE: # %bb.0: # %entry5421; P9LE-NEXT: lfs f0, 0(r3)5422; P9LE-NEXT: lfs f1, 4(r3)5423; P9LE-NEXT: xxmrghd vs0, vs1, vs05424; P9LE-NEXT: xvcvdpuxds v2, vs05425; P9LE-NEXT: blr5426;5427; P8BE-LABEL: fromDiffMemConsAConvftoull:5428; P8BE: # %bb.0: # %entry5429; P8BE-NEXT: lfs f0, 0(r3)5430; P8BE-NEXT: lfs f1, 4(r3)5431; P8BE-NEXT: xxmrghd vs0, vs0, vs15432; P8BE-NEXT: xvcvdpuxds v2, vs05433; P8BE-NEXT: blr5434;5435; P8LE-LABEL: fromDiffMemConsAConvftoull:5436; P8LE: # %bb.0: # %entry5437; P8LE-NEXT: lfs f0, 0(r3)5438; P8LE-NEXT: lfs f1, 4(r3)5439; P8LE-NEXT: xxmrghd vs0, vs1, vs05440; P8LE-NEXT: xvcvdpuxds v2, vs05441; P8LE-NEXT: blr5442entry:5443 %0 = load float, ptr %ptr, align 45444 %conv = fptoui float %0 to i645445 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 05446 %arrayidx1 = getelementptr inbounds float, ptr %ptr, i64 15447 %1 = load float, ptr %arrayidx1, align 45448 %conv2 = fptoui float %1 to i645449 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 15450 ret <2 x i64> %vecinit35451}5452 5453define <2 x i64> @fromDiffMemConsDConvftoull(ptr nocapture readonly %ptr) {5454; P9BE-LABEL: fromDiffMemConsDConvftoull:5455; P9BE: # %bb.0: # %entry5456; P9BE-NEXT: lfs f0, 12(r3)5457; P9BE-NEXT: lfs f1, 8(r3)5458; P9BE-NEXT: xxmrghd vs0, vs0, vs15459; P9BE-NEXT: xvcvdpuxds v2, vs05460; P9BE-NEXT: blr5461;5462; P9LE-LABEL: fromDiffMemConsDConvftoull:5463; P9LE: # %bb.0: # %entry5464; P9LE-NEXT: lfs f0, 12(r3)5465; P9LE-NEXT: lfs f1, 8(r3)5466; P9LE-NEXT: xxmrghd vs0, vs1, vs05467; P9LE-NEXT: xvcvdpuxds v2, vs05468; P9LE-NEXT: blr5469;5470; P8BE-LABEL: fromDiffMemConsDConvftoull:5471; P8BE: # %bb.0: # %entry5472; P8BE-NEXT: lfs f0, 12(r3)5473; P8BE-NEXT: lfs f1, 8(r3)5474; P8BE-NEXT: xxmrghd vs0, vs0, vs15475; P8BE-NEXT: xvcvdpuxds v2, vs05476; P8BE-NEXT: blr5477;5478; P8LE-LABEL: fromDiffMemConsDConvftoull:5479; P8LE: # %bb.0: # %entry5480; P8LE-NEXT: lfs f0, 12(r3)5481; P8LE-NEXT: lfs f1, 8(r3)5482; P8LE-NEXT: xxmrghd vs0, vs1, vs05483; P8LE-NEXT: xvcvdpuxds v2, vs05484; P8LE-NEXT: blr5485entry:5486 %arrayidx = getelementptr inbounds float, ptr %ptr, i64 35487 %0 = load float, ptr %arrayidx, align 45488 %conv = fptoui float %0 to i645489 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 05490 %arrayidx1 = getelementptr inbounds float, ptr %ptr, i64 25491 %1 = load float, ptr %arrayidx1, align 45492 %conv2 = fptoui float %1 to i645493 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 15494 ret <2 x i64> %vecinit35495}5496 5497define <2 x i64> @fromDiffMemVarAConvftoull(ptr nocapture readonly %arr, i32 signext %elem) {5498; P9BE-LABEL: fromDiffMemVarAConvftoull:5499; P9BE: # %bb.0: # %entry5500; P9BE-NEXT: sldi r4, r4, 25501; P9BE-NEXT: lfsux f0, r3, r45502; P9BE-NEXT: lfs f1, 4(r3)5503; P9BE-NEXT: xxmrghd vs0, vs0, vs15504; P9BE-NEXT: xvcvdpuxds v2, vs05505; P9BE-NEXT: blr5506;5507; P9LE-LABEL: fromDiffMemVarAConvftoull:5508; P9LE: # %bb.0: # %entry5509; P9LE-NEXT: sldi r4, r4, 25510; P9LE-NEXT: lfsux f0, r3, r45511; P9LE-NEXT: lfs f1, 4(r3)5512; P9LE-NEXT: xxmrghd vs0, vs1, vs05513; P9LE-NEXT: xvcvdpuxds v2, vs05514; P9LE-NEXT: blr5515;5516; P8BE-LABEL: fromDiffMemVarAConvftoull:5517; P8BE: # %bb.0: # %entry5518; P8BE-NEXT: sldi r4, r4, 25519; P8BE-NEXT: lfsux f0, r3, r45520; P8BE-NEXT: lfs f1, 4(r3)5521; P8BE-NEXT: xxmrghd vs0, vs0, vs15522; P8BE-NEXT: xvcvdpuxds v2, vs05523; P8BE-NEXT: blr5524;5525; P8LE-LABEL: fromDiffMemVarAConvftoull:5526; P8LE: # %bb.0: # %entry5527; P8LE-NEXT: sldi r4, r4, 25528; P8LE-NEXT: lfsux f0, r3, r45529; P8LE-NEXT: lfs f1, 4(r3)5530; P8LE-NEXT: xxmrghd vs0, vs1, vs05531; P8LE-NEXT: xvcvdpuxds v2, vs05532; P8LE-NEXT: blr5533entry:5534 %idxprom = sext i32 %elem to i645535 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom5536 %0 = load float, ptr %arrayidx, align 45537 %conv = fptoui float %0 to i645538 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 05539 %add = add nsw i32 %elem, 15540 %idxprom1 = sext i32 %add to i645541 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom15542 %1 = load float, ptr %arrayidx2, align 45543 %conv3 = fptoui float %1 to i645544 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 15545 ret <2 x i64> %vecinit45546}5547 5548define <2 x i64> @fromDiffMemVarDConvftoull(ptr nocapture readonly %arr, i32 signext %elem) {5549; P9BE-LABEL: fromDiffMemVarDConvftoull:5550; P9BE: # %bb.0: # %entry5551; P9BE-NEXT: sldi r4, r4, 25552; P9BE-NEXT: lfsux f0, r3, r45553; P9BE-NEXT: lfs f1, -4(r3)5554; P9BE-NEXT: xxmrghd vs0, vs0, vs15555; P9BE-NEXT: xvcvdpuxds v2, vs05556; P9BE-NEXT: blr5557;5558; P9LE-LABEL: fromDiffMemVarDConvftoull:5559; P9LE: # %bb.0: # %entry5560; P9LE-NEXT: sldi r4, r4, 25561; P9LE-NEXT: lfsux f0, r3, r45562; P9LE-NEXT: lfs f1, -4(r3)5563; P9LE-NEXT: xxmrghd vs0, vs1, vs05564; P9LE-NEXT: xvcvdpuxds v2, vs05565; P9LE-NEXT: blr5566;5567; P8BE-LABEL: fromDiffMemVarDConvftoull:5568; P8BE: # %bb.0: # %entry5569; P8BE-NEXT: sldi r4, r4, 25570; P8BE-NEXT: lfsux f0, r3, r45571; P8BE-NEXT: lfs f1, -4(r3)5572; P8BE-NEXT: xxmrghd vs0, vs0, vs15573; P8BE-NEXT: xvcvdpuxds v2, vs05574; P8BE-NEXT: blr5575;5576; P8LE-LABEL: fromDiffMemVarDConvftoull:5577; P8LE: # %bb.0: # %entry5578; P8LE-NEXT: sldi r4, r4, 25579; P8LE-NEXT: lfsux f0, r3, r45580; P8LE-NEXT: lfs f1, -4(r3)5581; P8LE-NEXT: xxmrghd vs0, vs1, vs05582; P8LE-NEXT: xvcvdpuxds v2, vs05583; P8LE-NEXT: blr5584entry:5585 %idxprom = sext i32 %elem to i645586 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom5587 %0 = load float, ptr %arrayidx, align 45588 %conv = fptoui float %0 to i645589 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 05590 %sub = add nsw i32 %elem, -15591 %idxprom1 = sext i32 %sub to i645592 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom15593 %1 = load float, ptr %arrayidx2, align 45594 %conv3 = fptoui float %1 to i645595 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 15596 ret <2 x i64> %vecinit45597}5598 5599define <2 x i64> @spltRegValConvftoull(float %val) {5600; P9BE-LABEL: spltRegValConvftoull:5601; P9BE: # %bb.0: # %entry5602; P9BE-NEXT: xscvdpuxds f0, f15603; P9BE-NEXT: xxspltd v2, f0, 05604; P9BE-NEXT: blr5605;5606; P9LE-LABEL: spltRegValConvftoull:5607; P9LE: # %bb.0: # %entry5608; P9LE-NEXT: xscvdpuxds f0, f15609; P9LE-NEXT: xxspltd v2, f0, 05610; P9LE-NEXT: blr5611;5612; P8BE-LABEL: spltRegValConvftoull:5613; P8BE: # %bb.0: # %entry5614; P8BE-NEXT: xscvdpuxds f0, f15615; P8BE-NEXT: xxspltd v2, f0, 05616; P8BE-NEXT: blr5617;5618; P8LE-LABEL: spltRegValConvftoull:5619; P8LE: # %bb.0: # %entry5620; P8LE-NEXT: xscvdpuxds f0, f15621; P8LE-NEXT: xxspltd v2, f0, 05622; P8LE-NEXT: blr5623entry:5624 %conv = fptoui float %val to i645625 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 05626 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer5627 ret <2 x i64> %splat.splat5628}5629 5630define <2 x i64> @spltMemValConvftoull(ptr nocapture readonly %ptr) {5631; P9BE-LABEL: spltMemValConvftoull:5632; P9BE: # %bb.0: # %entry5633; P9BE-NEXT: lfs f0, 0(r3)5634; P9BE-NEXT: xscvdpuxds f0, f05635; P9BE-NEXT: xxspltd v2, f0, 05636; P9BE-NEXT: blr5637;5638; P9LE-LABEL: spltMemValConvftoull:5639; P9LE: # %bb.0: # %entry5640; P9LE-NEXT: lfs f0, 0(r3)5641; P9LE-NEXT: xscvdpuxds f0, f05642; P9LE-NEXT: xxspltd v2, vs0, 05643; P9LE-NEXT: blr5644;5645; P8BE-LABEL: spltMemValConvftoull:5646; P8BE: # %bb.0: # %entry5647; P8BE-NEXT: lfsx f0, 0, r35648; P8BE-NEXT: xscvdpuxds f0, f05649; P8BE-NEXT: xxspltd v2, f0, 05650; P8BE-NEXT: blr5651;5652; P8LE-LABEL: spltMemValConvftoull:5653; P8LE: # %bb.0: # %entry5654; P8LE-NEXT: lfsx f0, 0, r35655; P8LE-NEXT: xscvdpuxds f0, f05656; P8LE-NEXT: xxspltd v2, vs0, 05657; P8LE-NEXT: blr5658entry:5659 %0 = load float, ptr %ptr, align 45660 %conv = fptoui float %0 to i645661 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 05662 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer5663 ret <2 x i64> %splat.splat5664}5665 5666define <2 x i64> @spltCnstConvdtoull() {5667; P9BE-LABEL: spltCnstConvdtoull:5668; P9BE: # %bb.0: # %entry5669; P9BE-NEXT: vspltisw v2, 45670; P9BE-NEXT: vupklsw v2, v25671; P9BE-NEXT: blr5672;5673; P9LE-LABEL: spltCnstConvdtoull:5674; P9LE: # %bb.0: # %entry5675; P9LE-NEXT: vspltisw v2, 45676; P9LE-NEXT: vupklsw v2, v25677; P9LE-NEXT: blr5678;5679; P8BE-LABEL: spltCnstConvdtoull:5680; P8BE: # %bb.0: # %entry5681; P8BE-NEXT: vspltisw v2, 45682; P8BE-NEXT: vupklsw v2, v25683; P8BE-NEXT: blr5684;5685; P8LE-LABEL: spltCnstConvdtoull:5686; P8LE: # %bb.0: # %entry5687; P8LE-NEXT: vspltisw v2, 45688; P8LE-NEXT: vupklsw v2, v25689; P8LE-NEXT: blr5690entry:5691 ret <2 x i64> <i64 4, i64 4>5692}5693 5694define <2 x i64> @fromRegsConvdtoull(double %a, double %b) {5695; P9BE-LABEL: fromRegsConvdtoull:5696; P9BE: # %bb.0: # %entry5697; P9BE-NEXT: xxmrghd vs0, vs1, vs25698; P9BE-NEXT: xvcvdpuxds v2, vs05699; P9BE-NEXT: blr5700;5701; P9LE-LABEL: fromRegsConvdtoull:5702; P9LE: # %bb.0: # %entry5703; P9LE-NEXT: xxmrghd vs0, vs2, vs15704; P9LE-NEXT: xvcvdpuxds v2, vs05705; P9LE-NEXT: blr5706;5707; P8BE-LABEL: fromRegsConvdtoull:5708; P8BE: # %bb.0: # %entry5709; P8BE-NEXT: xxmrghd vs0, vs1, vs25710; P8BE-NEXT: xvcvdpuxds v2, vs05711; P8BE-NEXT: blr5712;5713; P8LE-LABEL: fromRegsConvdtoull:5714; P8LE: # %bb.0: # %entry5715; P8LE-NEXT: xxmrghd vs0, vs2, vs15716; P8LE-NEXT: xvcvdpuxds v2, vs05717; P8LE-NEXT: blr5718entry:5719 %conv = fptoui double %a to i645720 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 05721 %conv1 = fptoui double %b to i645722 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 15723 ret <2 x i64> %vecinit25724}5725 5726define <2 x i64> @fromDiffConstsConvdtoull() {5727; P9BE-LABEL: fromDiffConstsConvdtoull:5728; P9BE: # %bb.0: # %entry5729; P9BE-NEXT: addis r3, r2, .LCPI121_0@toc@ha5730; P9BE-NEXT: addi r3, r3, .LCPI121_0@toc@l5731; P9BE-NEXT: lxv v2, 0(r3)5732; P9BE-NEXT: blr5733;5734; P9LE-LABEL: fromDiffConstsConvdtoull:5735; P9LE: # %bb.0: # %entry5736; P9LE-NEXT: addis r3, r2, .LCPI121_0@toc@ha5737; P9LE-NEXT: addi r3, r3, .LCPI121_0@toc@l5738; P9LE-NEXT: lxv v2, 0(r3)5739; P9LE-NEXT: blr5740;5741; P8BE-LABEL: fromDiffConstsConvdtoull:5742; P8BE: # %bb.0: # %entry5743; P8BE-NEXT: addis r3, r2, .LCPI121_0@toc@ha5744; P8BE-NEXT: addi r3, r3, .LCPI121_0@toc@l5745; P8BE-NEXT: lxvd2x v2, 0, r35746; P8BE-NEXT: blr5747;5748; P8LE-LABEL: fromDiffConstsConvdtoull:5749; P8LE: # %bb.0: # %entry5750; P8LE-NEXT: addis r3, r2, .LCPI121_0@toc@ha5751; P8LE-NEXT: addi r3, r3, .LCPI121_0@toc@l5752; P8LE-NEXT: lxvd2x vs0, 0, r35753; P8LE-NEXT: xxswapd v2, vs05754; P8LE-NEXT: blr5755entry:5756 ret <2 x i64> <i64 24, i64 234>5757}5758 5759define <2 x i64> @fromDiffMemConsAConvdtoull(ptr nocapture readonly %ptr) {5760; P9BE-LABEL: fromDiffMemConsAConvdtoull:5761; P9BE: # %bb.0: # %entry5762; P9BE-NEXT: lxv vs0, 0(r3)5763; P9BE-NEXT: xvcvdpuxds v2, vs05764; P9BE-NEXT: blr5765;5766; P9LE-LABEL: fromDiffMemConsAConvdtoull:5767; P9LE: # %bb.0: # %entry5768; P9LE-NEXT: lxv vs0, 0(r3)5769; P9LE-NEXT: xvcvdpuxds v2, vs05770; P9LE-NEXT: blr5771;5772; P8BE-LABEL: fromDiffMemConsAConvdtoull:5773; P8BE: # %bb.0: # %entry5774; P8BE-NEXT: lxvd2x vs0, 0, r35775; P8BE-NEXT: xvcvdpuxds v2, vs05776; P8BE-NEXT: blr5777;5778; P8LE-LABEL: fromDiffMemConsAConvdtoull:5779; P8LE: # %bb.0: # %entry5780; P8LE-NEXT: lxvd2x vs0, 0, r35781; P8LE-NEXT: xxswapd vs0, vs05782; P8LE-NEXT: xvcvdpuxds v2, vs05783; P8LE-NEXT: blr5784entry:5785 %0 = load <2 x double>, ptr %ptr, align 85786 %1 = fptoui <2 x double> %0 to <2 x i64>5787 ret <2 x i64> %15788}5789 5790define <2 x i64> @fromDiffMemConsDConvdtoull(ptr nocapture readonly %ptr) {5791; P9BE-LABEL: fromDiffMemConsDConvdtoull:5792; P9BE: # %bb.0: # %entry5793; P9BE-NEXT: lxv vs0, 16(r3)5794; P9BE-NEXT: xxswapd vs0, vs05795; P9BE-NEXT: xvcvdpuxds v2, vs05796; P9BE-NEXT: blr5797;5798; P9LE-LABEL: fromDiffMemConsDConvdtoull:5799; P9LE: # %bb.0: # %entry5800; P9LE-NEXT: addi r3, r3, 165801; P9LE-NEXT: lxvd2x vs0, 0, r35802; P9LE-NEXT: xvcvdpuxds v2, vs05803; P9LE-NEXT: blr5804;5805; P8BE-LABEL: fromDiffMemConsDConvdtoull:5806; P8BE: # %bb.0: # %entry5807; P8BE-NEXT: addi r3, r3, 165808; P8BE-NEXT: lxvd2x vs0, 0, r35809; P8BE-NEXT: xxswapd vs0, vs05810; P8BE-NEXT: xvcvdpuxds v2, vs05811; P8BE-NEXT: blr5812;5813; P8LE-LABEL: fromDiffMemConsDConvdtoull:5814; P8LE: # %bb.0: # %entry5815; P8LE-NEXT: addi r3, r3, 165816; P8LE-NEXT: lxvd2x vs0, 0, r35817; P8LE-NEXT: xvcvdpuxds v2, vs05818; P8LE-NEXT: blr5819entry:5820 %arrayidx = getelementptr inbounds double, ptr %ptr, i64 35821 %0 = load double, ptr %arrayidx, align 85822 %conv = fptoui double %0 to i645823 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 05824 %arrayidx1 = getelementptr inbounds double, ptr %ptr, i64 25825 %1 = load double, ptr %arrayidx1, align 85826 %conv2 = fptoui double %1 to i645827 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 15828 ret <2 x i64> %vecinit35829}5830 5831define <2 x i64> @fromDiffMemVarAConvdtoull(ptr nocapture readonly %arr, i32 signext %elem) {5832; P9BE-LABEL: fromDiffMemVarAConvdtoull:5833; P9BE: # %bb.0: # %entry5834; P9BE-NEXT: sldi r4, r4, 35835; P9BE-NEXT: lxvx vs0, r3, r45836; P9BE-NEXT: xvcvdpuxds v2, vs05837; P9BE-NEXT: blr5838;5839; P9LE-LABEL: fromDiffMemVarAConvdtoull:5840; P9LE: # %bb.0: # %entry5841; P9LE-NEXT: sldi r4, r4, 35842; P9LE-NEXT: lxvx vs0, r3, r45843; P9LE-NEXT: xvcvdpuxds v2, vs05844; P9LE-NEXT: blr5845;5846; P8BE-LABEL: fromDiffMemVarAConvdtoull:5847; P8BE: # %bb.0: # %entry5848; P8BE-NEXT: sldi r4, r4, 35849; P8BE-NEXT: lxvd2x vs0, r3, r45850; P8BE-NEXT: xvcvdpuxds v2, vs05851; P8BE-NEXT: blr5852;5853; P8LE-LABEL: fromDiffMemVarAConvdtoull:5854; P8LE: # %bb.0: # %entry5855; P8LE-NEXT: sldi r4, r4, 35856; P8LE-NEXT: lxvd2x vs0, r3, r45857; P8LE-NEXT: xxswapd vs0, vs05858; P8LE-NEXT: xvcvdpuxds v2, vs05859; P8LE-NEXT: blr5860entry:5861 %idxprom = sext i32 %elem to i645862 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom5863 %0 = load double, ptr %arrayidx, align 85864 %conv = fptoui double %0 to i645865 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 05866 %add = add nsw i32 %elem, 15867 %idxprom1 = sext i32 %add to i645868 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom15869 %1 = load double, ptr %arrayidx2, align 85870 %conv3 = fptoui double %1 to i645871 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 15872 ret <2 x i64> %vecinit45873}5874 5875define <2 x i64> @fromDiffMemVarDConvdtoull(ptr nocapture readonly %arr, i32 signext %elem) {5876; P9BE-LABEL: fromDiffMemVarDConvdtoull:5877; P9BE: # %bb.0: # %entry5878; P9BE-NEXT: sldi r4, r4, 35879; P9BE-NEXT: add r3, r3, r45880; P9BE-NEXT: li r4, -85881; P9BE-NEXT: lxvx vs0, r3, r45882; P9BE-NEXT: xxswapd vs0, vs05883; P9BE-NEXT: xvcvdpuxds v2, vs05884; P9BE-NEXT: blr5885;5886; P9LE-LABEL: fromDiffMemVarDConvdtoull:5887; P9LE: # %bb.0: # %entry5888; P9LE-NEXT: sldi r4, r4, 35889; P9LE-NEXT: add r3, r3, r45890; P9LE-NEXT: addi r3, r3, -85891; P9LE-NEXT: lxvd2x vs0, 0, r35892; P9LE-NEXT: xvcvdpuxds v2, vs05893; P9LE-NEXT: blr5894;5895; P8BE-LABEL: fromDiffMemVarDConvdtoull:5896; P8BE: # %bb.0: # %entry5897; P8BE-NEXT: sldi r4, r4, 35898; P8BE-NEXT: add r3, r3, r45899; P8BE-NEXT: addi r3, r3, -85900; P8BE-NEXT: lxvd2x vs0, 0, r35901; P8BE-NEXT: xxswapd vs0, vs05902; P8BE-NEXT: xvcvdpuxds v2, vs05903; P8BE-NEXT: blr5904;5905; P8LE-LABEL: fromDiffMemVarDConvdtoull:5906; P8LE: # %bb.0: # %entry5907; P8LE-NEXT: sldi r4, r4, 35908; P8LE-NEXT: add r3, r3, r45909; P8LE-NEXT: addi r3, r3, -85910; P8LE-NEXT: lxvd2x vs0, 0, r35911; P8LE-NEXT: xvcvdpuxds v2, vs05912; P8LE-NEXT: blr5913entry:5914 %idxprom = sext i32 %elem to i645915 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom5916 %0 = load double, ptr %arrayidx, align 85917 %conv = fptoui double %0 to i645918 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 05919 %sub = add nsw i32 %elem, -15920 %idxprom1 = sext i32 %sub to i645921 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom15922 %1 = load double, ptr %arrayidx2, align 85923 %conv3 = fptoui double %1 to i645924 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 15925 ret <2 x i64> %vecinit45926}5927 5928define <2 x i64> @spltRegValConvdtoull(double %val) {5929; P9BE-LABEL: spltRegValConvdtoull:5930; P9BE: # %bb.0: # %entry5931; P9BE-NEXT: xscvdpuxds f0, f15932; P9BE-NEXT: xxspltd v2, vs0, 05933; P9BE-NEXT: blr5934;5935; P9LE-LABEL: spltRegValConvdtoull:5936; P9LE: # %bb.0: # %entry5937; P9LE-NEXT: xscvdpuxds f0, f15938; P9LE-NEXT: xxspltd v2, vs0, 05939; P9LE-NEXT: blr5940;5941; P8BE-LABEL: spltRegValConvdtoull:5942; P8BE: # %bb.0: # %entry5943; P8BE-NEXT: xscvdpuxds f0, f15944; P8BE-NEXT: xxspltd v2, vs0, 05945; P8BE-NEXT: blr5946;5947; P8LE-LABEL: spltRegValConvdtoull:5948; P8LE: # %bb.0: # %entry5949; P8LE-NEXT: xscvdpuxds f0, f15950; P8LE-NEXT: xxspltd v2, vs0, 05951; P8LE-NEXT: blr5952entry:5953 %conv = fptoui double %val to i645954 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 05955 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer5956 ret <2 x i64> %splat.splat5957}5958 5959define <2 x i64> @spltMemValConvdtoull(ptr nocapture readonly %ptr) {5960; P9BE-LABEL: spltMemValConvdtoull:5961; P9BE: # %bb.0: # %entry5962; P9BE-NEXT: lxvdsx vs0, 0, r35963; P9BE-NEXT: xvcvdpuxds v2, vs05964; P9BE-NEXT: blr5965;5966; P9LE-LABEL: spltMemValConvdtoull:5967; P9LE: # %bb.0: # %entry5968; P9LE-NEXT: lxvdsx vs0, 0, r35969; P9LE-NEXT: xvcvdpuxds v2, vs05970; P9LE-NEXT: blr5971;5972; P8BE-LABEL: spltMemValConvdtoull:5973; P8BE: # %bb.0: # %entry5974; P8BE-NEXT: lxvdsx vs0, 0, r35975; P8BE-NEXT: xvcvdpuxds v2, vs05976; P8BE-NEXT: blr5977;5978; P8LE-LABEL: spltMemValConvdtoull:5979; P8LE: # %bb.0: # %entry5980; P8LE-NEXT: lxvdsx vs0, 0, r35981; P8LE-NEXT: xvcvdpuxds v2, vs05982; P8LE-NEXT: blr5983entry:5984 %0 = load double, ptr %ptr, align 85985 %conv = fptoui double %0 to i645986 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 05987 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer5988 ret <2 x i64> %splat.splat5989}5990 5991; Some additional patterns that come up in real code.5992define dso_local <2 x double> @sint_to_fp_widen02(<4 x i32> %a) {5993; P9BE-LABEL: sint_to_fp_widen02:5994; P9BE: # %bb.0: # %entry5995; P9BE-NEXT: xvcvsxwdp v2, v25996; P9BE-NEXT: blr5997;5998; P9LE-LABEL: sint_to_fp_widen02:5999; P9LE: # %bb.0: # %entry6000; P9LE-NEXT: xxsldwi vs0, v2, v2, 16001; P9LE-NEXT: xvcvsxwdp v2, vs06002; P9LE-NEXT: blr6003;6004; P8BE-LABEL: sint_to_fp_widen02:6005; P8BE: # %bb.0: # %entry6006; P8BE-NEXT: xvcvsxwdp v2, v26007; P8BE-NEXT: blr6008;6009; P8LE-LABEL: sint_to_fp_widen02:6010; P8LE: # %bb.0: # %entry6011; P8LE-NEXT: xxsldwi vs0, v2, v2, 16012; P8LE-NEXT: xvcvsxwdp v2, vs06013; P8LE-NEXT: blr6014entry:6015 %vecext = extractelement <4 x i32> %a, i32 06016 %conv = sitofp i32 %vecext to double6017 %vecinit = insertelement <2 x double> undef, double %conv, i32 06018 %vecext1 = extractelement <4 x i32> %a, i32 26019 %conv2 = sitofp i32 %vecext1 to double6020 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 16021 ret <2 x double> %vecinit36022}6023 6024define dso_local <2 x double> @sint_to_fp_widen13(<4 x i32> %a) {6025; P9BE-LABEL: sint_to_fp_widen13:6026; P9BE: # %bb.0: # %entry6027; P9BE-NEXT: xxsldwi vs0, v2, v2, 16028; P9BE-NEXT: xvcvsxwdp v2, vs06029; P9BE-NEXT: blr6030;6031; P9LE-LABEL: sint_to_fp_widen13:6032; P9LE: # %bb.0: # %entry6033; P9LE-NEXT: xvcvsxwdp v2, v26034; P9LE-NEXT: blr6035;6036; P8BE-LABEL: sint_to_fp_widen13:6037; P8BE: # %bb.0: # %entry6038; P8BE-NEXT: xxsldwi vs0, v2, v2, 16039; P8BE-NEXT: xvcvsxwdp v2, vs06040; P8BE-NEXT: blr6041;6042; P8LE-LABEL: sint_to_fp_widen13:6043; P8LE: # %bb.0: # %entry6044; P8LE-NEXT: xvcvsxwdp v2, v26045; P8LE-NEXT: blr6046entry:6047 %vecext = extractelement <4 x i32> %a, i32 16048 %conv = sitofp i32 %vecext to double6049 %vecinit = insertelement <2 x double> undef, double %conv, i32 06050 %vecext1 = extractelement <4 x i32> %a, i32 36051 %conv2 = sitofp i32 %vecext1 to double6052 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 16053 ret <2 x double> %vecinit36054}6055 6056define dso_local <2 x double> @uint_to_fp_widen02(<4 x i32> %a) {6057; P9BE-LABEL: uint_to_fp_widen02:6058; P9BE: # %bb.0: # %entry6059; P9BE-NEXT: xvcvuxwdp v2, v26060; P9BE-NEXT: blr6061;6062; P9LE-LABEL: uint_to_fp_widen02:6063; P9LE: # %bb.0: # %entry6064; P9LE-NEXT: xxsldwi vs0, v2, v2, 16065; P9LE-NEXT: xvcvuxwdp v2, vs06066; P9LE-NEXT: blr6067;6068; P8BE-LABEL: uint_to_fp_widen02:6069; P8BE: # %bb.0: # %entry6070; P8BE-NEXT: xvcvuxwdp v2, v26071; P8BE-NEXT: blr6072;6073; P8LE-LABEL: uint_to_fp_widen02:6074; P8LE: # %bb.0: # %entry6075; P8LE-NEXT: xxsldwi vs0, v2, v2, 16076; P8LE-NEXT: xvcvuxwdp v2, vs06077; P8LE-NEXT: blr6078entry:6079 %vecext = extractelement <4 x i32> %a, i32 06080 %conv = uitofp i32 %vecext to double6081 %vecinit = insertelement <2 x double> undef, double %conv, i32 06082 %vecext1 = extractelement <4 x i32> %a, i32 26083 %conv2 = uitofp i32 %vecext1 to double6084 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 16085 ret <2 x double> %vecinit36086}6087 6088define dso_local <2 x double> @uint_to_fp_widen13(<4 x i32> %a) {6089; P9BE-LABEL: uint_to_fp_widen13:6090; P9BE: # %bb.0: # %entry6091; P9BE-NEXT: xxsldwi vs0, v2, v2, 16092; P9BE-NEXT: xvcvuxwdp v2, vs06093; P9BE-NEXT: blr6094;6095; P9LE-LABEL: uint_to_fp_widen13:6096; P9LE: # %bb.0: # %entry6097; P9LE-NEXT: xvcvuxwdp v2, v26098; P9LE-NEXT: blr6099;6100; P8BE-LABEL: uint_to_fp_widen13:6101; P8BE: # %bb.0: # %entry6102; P8BE-NEXT: xxsldwi vs0, v2, v2, 16103; P8BE-NEXT: xvcvuxwdp v2, vs06104; P8BE-NEXT: blr6105;6106; P8LE-LABEL: uint_to_fp_widen13:6107; P8LE: # %bb.0: # %entry6108; P8LE-NEXT: xvcvuxwdp v2, v26109; P8LE-NEXT: blr6110entry:6111 %vecext = extractelement <4 x i32> %a, i32 16112 %conv = uitofp i32 %vecext to double6113 %vecinit = insertelement <2 x double> undef, double %conv, i32 06114 %vecext1 = extractelement <4 x i32> %a, i32 36115 %conv2 = uitofp i32 %vecext1 to double6116 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 16117 ret <2 x double> %vecinit36118}6119 6120define dso_local <2 x double> @fp_extend01(<4 x float> %a) {6121; P9BE-LABEL: fp_extend01:6122; P9BE: # %bb.0: # %entry6123; P9BE-NEXT: xxmrghw vs0, v2, v26124; P9BE-NEXT: xvcvspdp v2, vs06125; P9BE-NEXT: blr6126;6127; P9LE-LABEL: fp_extend01:6128; P9LE: # %bb.0: # %entry6129; P9LE-NEXT: xxmrglw vs0, v2, v26130; P9LE-NEXT: xvcvspdp v2, vs06131; P9LE-NEXT: blr6132;6133; P8BE-LABEL: fp_extend01:6134; P8BE: # %bb.0: # %entry6135; P8BE-NEXT: xxmrghw vs0, v2, v26136; P8BE-NEXT: xvcvspdp v2, vs06137; P8BE-NEXT: blr6138;6139; P8LE-LABEL: fp_extend01:6140; P8LE: # %bb.0: # %entry6141; P8LE-NEXT: xxmrglw vs0, v2, v26142; P8LE-NEXT: xvcvspdp v2, vs06143; P8LE-NEXT: blr6144entry:6145 %vecext = extractelement <4 x float> %a, i32 06146 %conv = fpext float %vecext to double6147 %vecinit = insertelement <2 x double> undef, double %conv, i32 06148 %vecext1 = extractelement <4 x float> %a, i32 16149 %conv2 = fpext float %vecext1 to double6150 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 16151 ret <2 x double> %vecinit36152}6153 6154define dso_local <2 x double> @fp_extend10(<4 x float> %a) {6155; P9BE-LABEL: fp_extend10:6156; P9BE: # %bb.0: # %entry6157; P9BE-NEXT: xxmrghw vs0, v2, v26158; P9BE-NEXT: xvcvspdp vs0, vs06159; P9BE-NEXT: xxswapd v2, vs06160; P9BE-NEXT: blr6161;6162; P9LE-LABEL: fp_extend10:6163; P9LE: # %bb.0: # %entry6164; P9LE-NEXT: xxmrglw vs0, v2, v26165; P9LE-NEXT: xvcvspdp vs0, vs06166; P9LE-NEXT: xxswapd v2, vs06167; P9LE-NEXT: blr6168;6169; P8BE-LABEL: fp_extend10:6170; P8BE: # %bb.0: # %entry6171; P8BE-NEXT: xxmrghw vs0, v2, v26172; P8BE-NEXT: xvcvspdp vs0, vs06173; P8BE-NEXT: xxswapd v2, vs06174; P8BE-NEXT: blr6175;6176; P8LE-LABEL: fp_extend10:6177; P8LE: # %bb.0: # %entry6178; P8LE-NEXT: xxmrglw vs0, v2, v26179; P8LE-NEXT: xvcvspdp vs0, vs06180; P8LE-NEXT: xxswapd v2, vs06181; P8LE-NEXT: blr6182entry:6183 %vecext = extractelement <4 x float> %a, i32 16184 %conv = fpext float %vecext to double6185 %vecinit = insertelement <2 x double> undef, double %conv, i32 06186 %vecext1 = extractelement <4 x float> %a, i32 06187 %conv2 = fpext float %vecext1 to double6188 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 16189 ret <2 x double> %vecinit36190}6191 6192define dso_local <2 x double> @fp_extend02(<4 x float> %a) {6193; P9BE-LABEL: fp_extend02:6194; P9BE: # %bb.0: # %entry6195; P9BE-NEXT: xvcvspdp v2, v26196; P9BE-NEXT: blr6197;6198; P9LE-LABEL: fp_extend02:6199; P9LE: # %bb.0: # %entry6200; P9LE-NEXT: xxsldwi vs0, v2, v2, 16201; P9LE-NEXT: xvcvspdp v2, vs06202; P9LE-NEXT: blr6203;6204; P8BE-LABEL: fp_extend02:6205; P8BE: # %bb.0: # %entry6206; P8BE-NEXT: xvcvspdp v2, v26207; P8BE-NEXT: blr6208;6209; P8LE-LABEL: fp_extend02:6210; P8LE: # %bb.0: # %entry6211; P8LE-NEXT: xxsldwi vs0, v2, v2, 16212; P8LE-NEXT: xvcvspdp v2, vs06213; P8LE-NEXT: blr6214entry:6215 %vecext = extractelement <4 x float> %a, i32 06216 %conv = fpext float %vecext to double6217 %vecinit = insertelement <2 x double> undef, double %conv, i32 06218 %vecext1 = extractelement <4 x float> %a, i32 26219 %conv2 = fpext float %vecext1 to double6220 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 16221 ret <2 x double> %vecinit36222}6223 6224define dso_local <2 x double> @fp_extend13(<4 x float> %a) {6225; P9BE-LABEL: fp_extend13:6226; P9BE: # %bb.0: # %entry6227; P9BE-NEXT: xxsldwi vs0, v2, v2, 16228; P9BE-NEXT: xvcvspdp v2, vs06229; P9BE-NEXT: blr6230;6231; P9LE-LABEL: fp_extend13:6232; P9LE: # %bb.0: # %entry6233; P9LE-NEXT: xvcvspdp v2, v26234; P9LE-NEXT: blr6235;6236; P8BE-LABEL: fp_extend13:6237; P8BE: # %bb.0: # %entry6238; P8BE-NEXT: xxsldwi vs0, v2, v2, 16239; P8BE-NEXT: xvcvspdp v2, vs06240; P8BE-NEXT: blr6241;6242; P8LE-LABEL: fp_extend13:6243; P8LE: # %bb.0: # %entry6244; P8LE-NEXT: xvcvspdp v2, v26245; P8LE-NEXT: blr6246entry:6247 %vecext = extractelement <4 x float> %a, i32 16248 %conv = fpext float %vecext to double6249 %vecinit = insertelement <2 x double> undef, double %conv, i32 06250 %vecext1 = extractelement <4 x float> %a, i32 36251 %conv2 = fpext float %vecext1 to double6252 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 16253 ret <2 x double> %vecinit36254}6255 6256define dso_local <2 x double> @fp_extend23(<4 x float> %a) {6257; P9BE-LABEL: fp_extend23:6258; P9BE: # %bb.0: # %entry6259; P9BE-NEXT: xxmrglw vs0, v2, v26260; P9BE-NEXT: xvcvspdp v2, vs06261; P9BE-NEXT: blr6262;6263; P9LE-LABEL: fp_extend23:6264; P9LE: # %bb.0: # %entry6265; P9LE-NEXT: xxmrghw vs0, v2, v26266; P9LE-NEXT: xvcvspdp v2, vs06267; P9LE-NEXT: blr6268;6269; P8BE-LABEL: fp_extend23:6270; P8BE: # %bb.0: # %entry6271; P8BE-NEXT: xxmrglw vs0, v2, v26272; P8BE-NEXT: xvcvspdp v2, vs06273; P8BE-NEXT: blr6274;6275; P8LE-LABEL: fp_extend23:6276; P8LE: # %bb.0: # %entry6277; P8LE-NEXT: xxmrghw vs0, v2, v26278; P8LE-NEXT: xvcvspdp v2, vs06279; P8LE-NEXT: blr6280entry:6281 %vecext = extractelement <4 x float> %a, i32 26282 %conv = fpext float %vecext to double6283 %vecinit = insertelement <2 x double> undef, double %conv, i32 06284 %vecext1 = extractelement <4 x float> %a, i32 36285 %conv2 = fpext float %vecext1 to double6286 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 16287 ret <2 x double> %vecinit36288}6289 6290define dso_local <2 x double> @fp_extend32(<4 x float> %a) {6291; P9BE-LABEL: fp_extend32:6292; P9BE: # %bb.0: # %entry6293; P9BE-NEXT: xxmrglw vs0, v2, v26294; P9BE-NEXT: xvcvspdp vs0, vs06295; P9BE-NEXT: xxswapd v2, vs06296; P9BE-NEXT: blr6297;6298; P9LE-LABEL: fp_extend32:6299; P9LE: # %bb.0: # %entry6300; P9LE-NEXT: xxmrghw vs0, v2, v26301; P9LE-NEXT: xvcvspdp vs0, vs06302; P9LE-NEXT: xxswapd v2, vs06303; P9LE-NEXT: blr6304;6305; P8BE-LABEL: fp_extend32:6306; P8BE: # %bb.0: # %entry6307; P8BE-NEXT: xxmrglw vs0, v2, v26308; P8BE-NEXT: xvcvspdp vs0, vs06309; P8BE-NEXT: xxswapd v2, vs06310; P8BE-NEXT: blr6311;6312; P8LE-LABEL: fp_extend32:6313; P8LE: # %bb.0: # %entry6314; P8LE-NEXT: xxmrghw vs0, v2, v26315; P8LE-NEXT: xvcvspdp vs0, vs06316; P8LE-NEXT: xxswapd v2, vs06317; P8LE-NEXT: blr6318entry:6319 %vecext = extractelement <4 x float> %a, i32 36320 %conv = fpext float %vecext to double6321 %vecinit = insertelement <2 x double> undef, double %conv, i32 06322 %vecext1 = extractelement <4 x float> %a, i32 26323 %conv2 = fpext float %vecext1 to double6324 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 16325 ret <2 x double> %vecinit36326}6327 6328define dso_local <2 x double> @fp_extend_two00(<4 x float> %a, <4 x float> %b) {6329; P9BE-LABEL: fp_extend_two00:6330; P9BE: # %bb.0: # %entry6331; P9BE-NEXT: xxmrghd vs0, v2, v36332; P9BE-NEXT: xvcvspdp v2, vs06333; P9BE-NEXT: blr6334;6335; P9LE-LABEL: fp_extend_two00:6336; P9LE: # %bb.0: # %entry6337; P9LE-NEXT: xxmrgld vs0, v3, v26338; P9LE-NEXT: xxsldwi vs0, vs0, vs0, 16339; P9LE-NEXT: xvcvspdp v2, vs06340; P9LE-NEXT: blr6341;6342; P8BE-LABEL: fp_extend_two00:6343; P8BE: # %bb.0: # %entry6344; P8BE-NEXT: xxmrghd vs0, v2, v36345; P8BE-NEXT: xvcvspdp v2, vs06346; P8BE-NEXT: blr6347;6348; P8LE-LABEL: fp_extend_two00:6349; P8LE: # %bb.0: # %entry6350; P8LE-NEXT: xxmrgld vs0, v3, v26351; P8LE-NEXT: xxsldwi vs0, vs0, vs0, 16352; P8LE-NEXT: xvcvspdp v2, vs06353; P8LE-NEXT: blr6354entry:6355 %vecext = extractelement <4 x float> %a, i32 06356 %conv = fpext float %vecext to double6357 %vecinit = insertelement <2 x double> undef, double %conv, i32 06358 %vecext1 = extractelement <4 x float> %b, i32 06359 %conv2 = fpext float %vecext1 to double6360 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 16361 ret <2 x double> %vecinit36362}6363 6364define dso_local <2 x double> @fp_extend_two33(<4 x float> %a, <4 x float> %b) {6365; P9BE-LABEL: fp_extend_two33:6366; P9BE: # %bb.0: # %entry6367; P9BE-NEXT: xxmrgld vs0, v2, v36368; P9BE-NEXT: xxsldwi vs0, vs0, vs0, 16369; P9BE-NEXT: xvcvspdp v2, vs06370; P9BE-NEXT: blr6371;6372; P9LE-LABEL: fp_extend_two33:6373; P9LE: # %bb.0: # %entry6374; P9LE-NEXT: xxmrghd vs0, v3, v26375; P9LE-NEXT: xvcvspdp v2, vs06376; P9LE-NEXT: blr6377;6378; P8BE-LABEL: fp_extend_two33:6379; P8BE: # %bb.0: # %entry6380; P8BE-NEXT: xxmrgld vs0, v2, v36381; P8BE-NEXT: xxsldwi vs0, vs0, vs0, 16382; P8BE-NEXT: xvcvspdp v2, vs06383; P8BE-NEXT: blr6384;6385; P8LE-LABEL: fp_extend_two33:6386; P8LE: # %bb.0: # %entry6387; P8LE-NEXT: xxmrghd vs0, v3, v26388; P8LE-NEXT: xvcvspdp v2, vs06389; P8LE-NEXT: blr6390entry:6391 %vecext = extractelement <4 x float> %a, i32 36392 %conv = fpext float %vecext to double6393 %vecinit = insertelement <2 x double> undef, double %conv, i32 06394 %vecext1 = extractelement <4 x float> %b, i32 36395 %conv2 = fpext float %vecext1 to double6396 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 16397 ret <2 x double> %vecinit36398}6399 6400define dso_local <2 x i64> @test_xvcvspsxds13(<4 x float> %a) local_unnamed_addr {6401; P9BE-LABEL: test_xvcvspsxds13:6402; P9BE: # %bb.0: # %entry6403; P9BE-NEXT: xxsldwi vs0, v2, v2, 16404; P9BE-NEXT: xvcvspsxds v2, vs06405; P9BE-NEXT: blr6406;6407; P9LE-LABEL: test_xvcvspsxds13:6408; P9LE: # %bb.0: # %entry6409; P9LE-NEXT: xvcvspsxds v2, v26410; P9LE-NEXT: blr6411;6412; P8BE-LABEL: test_xvcvspsxds13:6413; P8BE: # %bb.0: # %entry6414; P8BE-NEXT: xxsldwi vs0, v2, v2, 16415; P8BE-NEXT: xvcvspsxds v2, vs06416; P8BE-NEXT: blr6417;6418; P8LE-LABEL: test_xvcvspsxds13:6419; P8LE: # %bb.0: # %entry6420; P8LE-NEXT: xvcvspsxds v2, v26421; P8LE-NEXT: blr6422entry:6423 %vecext = extractelement <4 x float> %a, i32 16424 %conv = fptosi float %vecext to i646425 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 06426 %vecext1 = extractelement <4 x float> %a, i32 36427 %conv2 = fptosi float %vecext1 to i646428 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 16429 ret <2 x i64> %vecinit36430}6431 6432define dso_local <2 x i64> @test_xvcvspuxds13(<4 x float> %a) local_unnamed_addr {6433; P9BE-LABEL: test_xvcvspuxds13:6434; P9BE: # %bb.0: # %entry6435; P9BE-NEXT: xxsldwi vs0, v2, v2, 16436; P9BE-NEXT: xvcvspuxds v2, vs06437; P9BE-NEXT: blr6438;6439; P9LE-LABEL: test_xvcvspuxds13:6440; P9LE: # %bb.0: # %entry6441; P9LE-NEXT: xvcvspuxds v2, v26442; P9LE-NEXT: blr6443;6444; P8BE-LABEL: test_xvcvspuxds13:6445; P8BE: # %bb.0: # %entry6446; P8BE-NEXT: xxsldwi vs0, v2, v2, 16447; P8BE-NEXT: xvcvspuxds v2, vs06448; P8BE-NEXT: blr6449;6450; P8LE-LABEL: test_xvcvspuxds13:6451; P8LE: # %bb.0: # %entry6452; P8LE-NEXT: xvcvspuxds v2, v26453; P8LE-NEXT: blr6454entry:6455 %vecext = extractelement <4 x float> %a, i32 16456 %conv = fptoui float %vecext to i646457 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 06458 %vecext1 = extractelement <4 x float> %a, i32 36459 %conv2 = fptoui float %vecext1 to i646460 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 16461 ret <2 x i64> %vecinit36462}6463 6464define dso_local <2 x i64> @test_xvcvspsxds02(<4 x float> %a) local_unnamed_addr {6465; P9BE-LABEL: test_xvcvspsxds02:6466; P9BE: # %bb.0: # %entry6467; P9BE-NEXT: xvcvspsxds v2, v26468; P9BE-NEXT: blr6469;6470; P9LE-LABEL: test_xvcvspsxds02:6471; P9LE: # %bb.0: # %entry6472; P9LE-NEXT: xxsldwi vs0, v2, v2, 16473; P9LE-NEXT: xvcvspsxds v2, vs06474; P9LE-NEXT: blr6475;6476; P8BE-LABEL: test_xvcvspsxds02:6477; P8BE: # %bb.0: # %entry6478; P8BE-NEXT: xvcvspsxds v2, v26479; P8BE-NEXT: blr6480;6481; P8LE-LABEL: test_xvcvspsxds02:6482; P8LE: # %bb.0: # %entry6483; P8LE-NEXT: xxsldwi vs0, v2, v2, 16484; P8LE-NEXT: xvcvspsxds v2, vs06485; P8LE-NEXT: blr6486entry:6487 %vecext = extractelement <4 x float> %a, i32 06488 %conv = fptosi float %vecext to i646489 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 06490 %vecext1 = extractelement <4 x float> %a, i32 26491 %conv2 = fptosi float %vecext1 to i646492 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 16493 ret <2 x i64> %vecinit36494}6495 6496define dso_local <2 x i64> @test_xvcvspuxds02(<4 x float> %a) local_unnamed_addr {6497; P9BE-LABEL: test_xvcvspuxds02:6498; P9BE: # %bb.0: # %entry6499; P9BE-NEXT: xvcvspuxds v2, v26500; P9BE-NEXT: blr6501;6502; P9LE-LABEL: test_xvcvspuxds02:6503; P9LE: # %bb.0: # %entry6504; P9LE-NEXT: xxsldwi vs0, v2, v2, 16505; P9LE-NEXT: xvcvspuxds v2, vs06506; P9LE-NEXT: blr6507;6508; P8BE-LABEL: test_xvcvspuxds02:6509; P8BE: # %bb.0: # %entry6510; P8BE-NEXT: xvcvspuxds v2, v26511; P8BE-NEXT: blr6512;6513; P8LE-LABEL: test_xvcvspuxds02:6514; P8LE: # %bb.0: # %entry6515; P8LE-NEXT: xxsldwi vs0, v2, v2, 16516; P8LE-NEXT: xvcvspuxds v2, vs06517; P8LE-NEXT: blr6518entry:6519 %vecext = extractelement <4 x float> %a, i32 06520 %conv = fptoui float %vecext to i646521 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 06522 %vecext1 = extractelement <4 x float> %a, i32 26523 %conv2 = fptoui float %vecext1 to i646524 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 16525 ret <2 x i64> %vecinit36526}6527