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1; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mattr=+altivec | FileCheck %s2 3define void @VXOR(ptr %P1, ptr %P2, ptr %P3) {4 %tmp = load <4 x float>, ptr %P3 ; <<4 x float>> [#uses=1]5 %tmp3 = load <4 x float>, ptr %P1 ; <<4 x float>> [#uses=1]6 %tmp4 = fmul <4 x float> %tmp, %tmp3 ; <<4 x float>> [#uses=1]7 store <4 x float> %tmp4, ptr %P38 store <4 x float> zeroinitializer, ptr %P19 store <4 x i32> zeroinitializer, ptr %P210 ret void11}12; The fmul will spill a vspltisw to create a -0.0 vector used as the addend13; to vmaddfp (so it would IEEE compliant with zero sign propagation).14; CHECK: @VXOR15; CHECK: vsplti16; CHECK: vxor17 18define void @VSPLTI(ptr %P2, ptr %P3) {19 store <4 x i32> bitcast (<16 x i8> < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > to <4 x i32>), ptr %P220 store <8 x i16> < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >, ptr %P321 ret void22}23; CHECK: @VSPLTI24; CHECK: vsplti25