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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux \3; RUN: --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s4; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \5; RUN: --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s6 7define i64 @cdtbcd_test(i64 noundef %ll) {8; CHECK-LABEL: cdtbcd_test:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: cdtbcd r3, r311; CHECK-NEXT: blr12entry:13 %0 = tail call i64 @llvm.ppc.cdtbcdd(i64 %ll)14 ret i64 %015}16 17define zeroext i32 @cdtbcd_test_ui(i32 noundef zeroext %ui) {18; CHECK-LABEL: cdtbcd_test_ui:19; CHECK: # %bb.0: # %entry20; CHECK-NEXT: cdtbcd r3, r321; CHECK-NEXT: clrldi r3, r3, 3222; CHECK-NEXT: blr23entry:24 %conv = zext i32 %ui to i6425 %0 = tail call i64 @llvm.ppc.cdtbcdd(i64 %conv)26 %conv1 = trunc i64 %0 to i3227 ret i32 %conv128}29 30define i64 @cbcdtd_test(i64 noundef %ll) {31; CHECK-LABEL: cbcdtd_test:32; CHECK: # %bb.0: # %entry33; CHECK-NEXT: cbcdtd r3, r334; CHECK-NEXT: blr35entry:36 %0 = tail call i64 @llvm.ppc.cbcdtdd(i64 %ll)37 ret i64 %038}39 40define zeroext i32 @cbcdtd_test_ui(i32 noundef zeroext %ui) {41; CHECK-LABEL: cbcdtd_test_ui:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: cbcdtd r3, r344; CHECK-NEXT: clrldi r3, r3, 3245; CHECK-NEXT: blr46entry:47 %conv = zext i32 %ui to i6448 %0 = tail call i64 @llvm.ppc.cbcdtdd(i64 %conv)49 %conv1 = trunc i64 %0 to i3250 ret i32 %conv151}52 53define i64 @addg6s_test(i64 noundef %ll, i64 noundef %ll2) {54; CHECK-LABEL: addg6s_test:55; CHECK: # %bb.0: # %entry56; CHECK-NEXT: addg6s r3, r3, r457; CHECK-NEXT: blr58entry:59 %0 = tail call i64 @llvm.ppc.addg6sd(i64 %ll, i64 %ll2)60 ret i64 %061}62 63define zeroext i32 @addg6s_test_ui(i32 noundef zeroext %ui, i32 noundef zeroext %ui2) {64; CHECK-LABEL: addg6s_test_ui:65; CHECK: # %bb.0: # %entry66; CHECK-NEXT: addg6s r3, r3, r467; CHECK-NEXT: clrldi r3, r3, 3268; CHECK-NEXT: blr69entry:70 %conv = zext i32 %ui to i6471 %conv1 = zext i32 %ui2 to i6472 %0 = tail call i64 @llvm.ppc.addg6sd(i64 %conv, i64 %conv1)73 %conv2 = trunc i64 %0 to i3274 ret i32 %conv275}76 77declare i64 @llvm.ppc.cdtbcdd(i64)78declare i64 @llvm.ppc.cbcdtdd(i64)79declare i64 @llvm.ppc.addg6sd(i64, i64)80