294 lines · plain
1; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s3 4@vda = common global <2 x double> zeroinitializer, align 165@vdb = common global <2 x double> zeroinitializer, align 166@vdr = common global <2 x double> zeroinitializer, align 167@vfa = common global <4 x float> zeroinitializer, align 168@vfb = common global <4 x float> zeroinitializer, align 169@vfr = common global <4 x float> zeroinitializer, align 1610@vbllr = common global <2 x i64> zeroinitializer, align 1611@vbir = common global <4 x i32> zeroinitializer, align 1612@vblla = common global <2 x i64> zeroinitializer, align 1613@vbllb = common global <2 x i64> zeroinitializer, align 1614@vbia = common global <4 x i32> zeroinitializer, align 1615@vbib = common global <4 x i32> zeroinitializer, align 1616 17; Function Attrs: nounwind18define void @test1() {19entry:20 %0 = load <2 x double>, ptr @vda, align 1621 %1 = load <2 x double>, ptr @vdb, align 1622 %2 = call <2 x double> @llvm.ppc.vsx.xvdivdp(<2 x double> %0, <2 x double> %1)23 store <2 x double> %2, ptr @vdr, align 1624 ret void25; CHECK-LABEL: @test126; CHECK: xvdivdp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}27}28 29; Function Attrs: nounwind30define void @test2() {31entry:32 %0 = load <4 x float>, ptr @vfa, align 1633 %1 = load <4 x float>, ptr @vfb, align 1634 %2 = call <4 x float> @llvm.ppc.vsx.xvdivsp(<4 x float> %0, <4 x float> %1)35 store <4 x float> %2, ptr @vfr, align 1636 ret void37; CHECK-LABEL: @test238; CHECK: xvdivsp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}39}40 41; Function Attrs: nounwind42define void @test3() {43entry:44 %0 = load <2 x double>, ptr @vda, align 1645 %1 = load <2 x double>, ptr @vda, align 1646 %2 = call <2 x double> @llvm.ceil.v2f64(<2 x double> %1)47 store <2 x double> %2, ptr @vdr, align 1648 ret void49; CHECK-LABEL: @test350; CHECK: xvrdpip {{[0-9]+}}, {{[0-9]+}}51}52 53; Function Attrs: nounwind54define void @test4() {55entry:56 %0 = load <4 x float>, ptr @vfa, align 1657 %1 = load <4 x float>, ptr @vfa, align 1658 %2 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %1)59 store <4 x float> %2, ptr @vfr, align 1660 ret void61; CHECK-LABEL: @test462; CHECK: xvrspip {{[0-9]+}}, {{[0-9]+}}63}64 65; Function Attrs: nounwind66define void @test5() {67entry:68 %0 = load <2 x double>, ptr @vda, align 1669 %1 = load <2 x double>, ptr @vdb, align 1670 %2 = call <2 x i64> @llvm.ppc.vsx.xvcmpeqdp(<2 x double> %0, <2 x double> %1)71 store <2 x i64> %2, ptr @vbllr, align 1672 ret void73; CHECK-LABEL: @test574; CHECK: xvcmpeqdp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}75}76 77; Function Attrs: nounwind78define void @test6() {79entry:80 %0 = load <4 x float>, ptr @vfa, align 1681 %1 = load <4 x float>, ptr @vfb, align 1682 %2 = call <4 x i32> @llvm.ppc.vsx.xvcmpeqsp(<4 x float> %0, <4 x float> %1)83 store <4 x i32> %2, ptr @vbir, align 1684 ret void85; CHECK-LABEL: @test686; CHECK: xvcmpeqsp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}87}88 89; Function Attrs: nounwind90define void @test7() {91entry:92 %0 = load <2 x double>, ptr @vda, align 1693 %1 = load <2 x double>, ptr @vdb, align 1694 %2 = call <2 x i64> @llvm.ppc.vsx.xvcmpgedp(<2 x double> %0, <2 x double> %1)95 store <2 x i64> %2, ptr @vbllr, align 1696 ret void97; CHECK-LABEL: @test798; CHECK: xvcmpgedp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}99}100 101; Function Attrs: nounwind102define void @test8() {103entry:104 %0 = load <4 x float>, ptr @vfa, align 16105 %1 = load <4 x float>, ptr @vfb, align 16106 %2 = call <4 x i32> @llvm.ppc.vsx.xvcmpgesp(<4 x float> %0, <4 x float> %1)107 store <4 x i32> %2, ptr @vbir, align 16108 ret void109; CHECK-LABEL: @test8110; CHECK: xvcmpgesp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}111}112 113; Function Attrs: nounwind114define void @test9() {115entry:116 %0 = load <2 x double>, ptr @vda, align 16117 %1 = load <2 x double>, ptr @vdb, align 16118 %2 = call <2 x i64> @llvm.ppc.vsx.xvcmpgtdp(<2 x double> %0, <2 x double> %1)119 store <2 x i64> %2, ptr @vbllr, align 16120 ret void121; CHECK-LABEL: @test9122; CHECK: xvcmpgtdp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}123}124 125; Function Attrs: nounwind126define void @test10() {127entry:128 %0 = load <4 x float>, ptr @vfa, align 16129 %1 = load <4 x float>, ptr @vfb, align 16130 %2 = call <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float> %0, <4 x float> %1)131 store <4 x i32> %2, ptr @vbir, align 16132 ret void133; CHECK-LABEL: @test10134; CHECK: xvcmpgtsp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}135}136 137; Function Attrs: nounwind138define <4 x float> @emit_xvresp(<4 x float> %a) {139entry:140 %a.addr = alloca <4 x float>, align 16141 store <4 x float> %a, ptr %a.addr, align 16142 %0 = load <4 x float>, ptr %a.addr, align 16143 %1 = call <4 x float> @llvm.ppc.vsx.xvresp(<4 x float> %0)144 ret <4 x float> %1145; CHECK-LABEL: @emit_xvresp146; CHECK: xvresp {{[0-9]+}}, {{[0-9]+}}147}148 149; Function Attrs: nounwind150define <2 x double> @emit_xvredp(<2 x double> %a) {151entry:152 %a.addr = alloca <2 x double>, align 16153 store <2 x double> %a, ptr %a.addr, align 16154 %0 = load <2 x double>, ptr %a.addr, align 16155 %1 = call <2 x double> @llvm.ppc.vsx.xvredp(<2 x double> %0)156 ret <2 x double> %1157; CHECK-LABEL: @emit_xvredp158; CHECK: xvredp {{[0-9]+}}, {{[0-9]+}}159}160 161; Function Attrs: nounwind readnone162define <4 x i32> @emit_xvcvdpsxws(<2 x double> %a) {163entry:164 %0 = tail call <4 x i32> @llvm.ppc.vsx.xvcvdpsxws(<2 x double> %a)165 ret <4 x i32> %0166; CHECK-LABEL: @emit_xvcvdpsxws167; CHECK: xvcvdpsxws 34, 34168}169 170; Function Attrs: nounwind readnone171define <4 x i32> @emit_xvcvdpuxws(<2 x double> %a) {172entry:173 %0 = tail call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double> %a)174 ret <4 x i32> %0175; CHECK-LABEL: @emit_xvcvdpuxws176; CHECK: xvcvdpuxws 34, 34177}178 179; Function Attrs: nounwind readnone180define <2 x double> @emit_xvcvsxwdp(<4 x i32> %a) {181entry:182 %0 = tail call <2 x double> @llvm.ppc.vsx.xvcvsxwdp(<4 x i32> %a)183 ret <2 x double> %0184; CHECK-LABEL: @emit_xvcvsxwdp185; CHECK: xvcvsxwdp 34, 34186}187 188; Function Attrs: nounwind readnone189define <2 x double> @emit_xvcvuxwdp(<4 x i32> %a) {190entry:191 %0 = tail call <2 x double> @llvm.ppc.vsx.xvcvuxwdp(<4 x i32> %a)192 ret <2 x double> %0193; CHECK-LABEL: @emit_xvcvuxwdp194; CHECK: xvcvuxwdp 34, 34195}196 197; Function Attrs: nounwind readnone198define <2 x double> @emit_xvcvspdp(<4 x float> %a) {199entry:200 %0 = tail call <2 x double> @llvm.ppc.vsx.xvcvspdp(<4 x float> %a)201 ret <2 x double> %0202; CHECK-LABEL: @emit_xvcvspdp203; CHECK: xvcvspdp 34, 34204}205 206; Function Attrs: nounwind readnone207define <4 x float> @emit_xvcvsxdsp(<2 x i64> %a) {208entry:209 %0 = tail call <4 x float> @llvm.ppc.vsx.xvcvsxdsp(<2 x i64> %a)210 ret <4 x float> %0211; CHECK-LABEL: @emit_xvcvsxdsp212; CHECK: xvcvsxdsp 34, 34213}214 215; Function Attrs: nounwind readnone216define <4 x float> @emit_xvcvuxdsp(<2 x i64> %a) {217entry:218 %0 = tail call <4 x float> @llvm.ppc.vsx.xvcvuxdsp(<2 x i64> %a)219 ret <4 x float> %0220; CHECK-LABEL: @emit_xvcvuxdsp221; CHECK: xvcvuxdsp 34, 34222}223 224; Function Attrs: nounwind readnone225define <4 x float> @emit_xvcvdpsp(<2 x double> %a) {226entry:227 %0 = tail call <4 x float> @llvm.ppc.vsx.xvcvdpsp(<2 x double> %a)228 ret <4 x float> %0229; CHECK-LABEL: @emit_xvcvdpsp230; CHECK: xvcvdpsp 34, 34231}232 233define dso_local <2 x i64> @emit_xvcvspsxds(<4 x float> %a) local_unnamed_addr #0 {234entry:235 %0 = tail call <2 x i64> @llvm.ppc.vsx.xvcvspsxds(<4 x float> %a)236 ret <2 x i64> %0237; CHECK-LABEL: @emit_xvcvspsxds238; CHECK: xvcvspsxds 34, 34239}240 241define dso_local <2 x i64> @emit_xvcvspuxds(<4 x float> %a) local_unnamed_addr #0 {242entry:243 %0 = tail call <2 x i64> @llvm.ppc.vsx.xvcvspuxds(<4 x float> %a)244 ret <2 x i64> %0245; CHECK-LABEL: @emit_xvcvspuxds246; CHECK: xvcvspuxds 34, 34247}248 249; Function Attrs: nounwind readnone250declare <4 x float> @llvm.ppc.vsx.xvresp(<4 x float>)251 252; Function Attrs: nounwind readnone253declare <2 x double> @llvm.ppc.vsx.xvredp(<2 x double>)254 255; Function Attrs: nounwind readnone256declare <2 x double> @llvm.ceil.v2f64(<2 x double>)257 258; Function Attrs: nounwind readnone259declare <4 x float> @llvm.ceil.v4f32(<4 x float>)260 261; Function Attrs: nounwind readnone262declare <2 x double> @llvm.ppc.vsx.xvdivdp(<2 x double>, <2 x double>)263 264; Function Attrs: nounwind readnone265declare <4 x float> @llvm.ppc.vsx.xvdivsp(<4 x float>, <4 x float>)266 267; Function Attrs: nounwind readnone268declare <2 x i64> @llvm.ppc.vsx.xvcmpeqdp(<2 x double>, <2 x double>)269 270; Function Attrs: nounwind readnone271declare <4 x i32> @llvm.ppc.vsx.xvcmpeqsp(<4 x float>, <4 x float>)272 273; Function Attrs: nounwind readnone274declare <2 x i64> @llvm.ppc.vsx.xvcmpgedp(<2 x double>, <2 x double>)275 276; Function Attrs: nounwind readnone277declare <4 x i32> @llvm.ppc.vsx.xvcmpgesp(<4 x float>, <4 x float>)278 279; Function Attrs: nounwind readnone280declare <2 x i64> @llvm.ppc.vsx.xvcmpgtdp(<2 x double>, <2 x double>)281 282; Function Attrs: nounwind readnone283declare <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float>, <4 x float>)284declare <4 x float> @llvm.ppc.vsx.xvcvdpsp(<2 x double>) #1285declare <4 x i32> @llvm.ppc.vsx.xvcvdpsxws(<2 x double>) #1286declare <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double>) #1287declare <2 x double> @llvm.ppc.vsx.xvcvsxwdp(<4 x i32>) #1288declare <2 x double> @llvm.ppc.vsx.xvcvuxwdp(<4 x i32>) #1289declare <2 x double> @llvm.ppc.vsx.xvcvspdp(<4 x float>) #1290declare <4 x float> @llvm.ppc.vsx.xvcvsxdsp(<2 x i64>) #1291declare <4 x float> @llvm.ppc.vsx.xvcvuxdsp(<2 x i64>) #1292declare <2 x i64> @llvm.ppc.vsx.xvcvspsxds(<4 x float>) #1293declare <2 x i64> @llvm.ppc.vsx.xvcvspuxds(<4 x float>) #1294