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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr10 \3; RUN: -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s4 5; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr10 \6; RUN: -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s7 8define <16 x i8> @testVSLDBI(<16 x i8> %a, <16 x i8> %b) {9; CHECK-LABEL: testVSLDBI:10; CHECK: # %bb.0: # %entry11; CHECK-NEXT: vsldbi v2, v2, v3, 112; CHECK-NEXT: blr13entry:14 %0 = tail call <16 x i8> @llvm.ppc.altivec.vsldbi(<16 x i8> %a, <16 x i8> %b, i32 1)15 ret <16 x i8> %016}17declare <16 x i8> @llvm.ppc.altivec.vsldbi(<16 x i8>, <16 x i8>, i32 immarg)18 19define <16 x i8> @testVSRDBI(<16 x i8> %a, <16 x i8> %b) {20; CHECK-LABEL: testVSRDBI:21; CHECK: # %bb.0: # %entry22; CHECK-NEXT: vsrdbi v2, v2, v3, 123; CHECK-NEXT: blr24entry:25 %0 = tail call <16 x i8> @llvm.ppc.altivec.vsrdbi(<16 x i8> %a, <16 x i8> %b, i32 1)26 ret <16 x i8> %027}28declare <16 x i8> @llvm.ppc.altivec.vsrdbi(<16 x i8>, <16 x i8>, i32 immarg)29 30define <16 x i8> @testXXPERMX(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {31; CHECK-LABEL: testXXPERMX:32; CHECK: # %bb.0: # %entry33; CHECK-NEXT: xxpermx v2, v2, v3, v4, 134; CHECK-NEXT: blr35entry:36 %0 = tail call <16 x i8> @llvm.ppc.vsx.xxpermx(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, i32 1)37 ret <16 x i8> %038}39declare <16 x i8> @llvm.ppc.vsx.xxpermx(<16 x i8>, <16 x i8>, <16 x i8>, i32 immarg)40 41define <16 x i8> @testXXBLENDVB(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {42; CHECK-LABEL: testXXBLENDVB:43; CHECK: # %bb.0: # %entry44; CHECK-NEXT: xxblendvb v2, v2, v3, v445; CHECK-NEXT: blr46entry:47 %0 = tail call <16 x i8> @llvm.ppc.vsx.xxblendvb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c)48 ret <16 x i8> %049}50declare <16 x i8> @llvm.ppc.vsx.xxblendvb(<16 x i8>, <16 x i8>, <16 x i8>)51 52define <8 x i16> @testXXBLENDVH(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {53; CHECK-LABEL: testXXBLENDVH:54; CHECK: # %bb.0: # %entry55; CHECK-NEXT: xxblendvh v2, v2, v3, v456; CHECK-NEXT: blr57entry:58 %0 = tail call <8 x i16> @llvm.ppc.vsx.xxblendvh(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c)59 ret <8 x i16> %060}61declare <8 x i16> @llvm.ppc.vsx.xxblendvh(<8 x i16>, <8 x i16>, <8 x i16>)62 63define <4 x i32> @testXXBLENDVW(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {64; CHECK-LABEL: testXXBLENDVW:65; CHECK: # %bb.0: # %entry66; CHECK-NEXT: xxblendvw v2, v2, v3, v467; CHECK-NEXT: blr68entry:69 %0 = tail call <4 x i32> @llvm.ppc.vsx.xxblendvw(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c)70 ret <4 x i32> %071}72declare <4 x i32> @llvm.ppc.vsx.xxblendvw(<4 x i32>, <4 x i32>, <4 x i32>)73 74define <2 x i64> @testXXBLENDVD(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {75; CHECK-LABEL: testXXBLENDVD:76; CHECK: # %bb.0: # %entry77; CHECK-NEXT: xxblendvd v2, v2, v3, v478; CHECK-NEXT: blr79entry:80 %0 = tail call <2 x i64> @llvm.ppc.vsx.xxblendvd(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c)81 ret <2 x i64> %082}83declare <2 x i64> @llvm.ppc.vsx.xxblendvd(<2 x i64>, <2 x i64>, <2 x i64>)84 85define <16 x i8> @testVINSBLX(<16 x i8> %a, i32 %b, i32 %c) {86; CHECK-LABEL: testVINSBLX:87; CHECK: # %bb.0: # %entry88; CHECK-NEXT: vinsblx v2, r5, r689; CHECK-NEXT: blr90entry:91 %0 = tail call <16 x i8> @llvm.ppc.altivec.vinsblx(<16 x i8> %a, i32 %b, i32 %c)92 ret <16 x i8> %093}94declare <16 x i8> @llvm.ppc.altivec.vinsblx(<16 x i8>, i32, i32)95 96define <16 x i8> @testVINSBRX(<16 x i8> %a, i32 %b, i32 %c) {97; CHECK-LABEL: testVINSBRX:98; CHECK: # %bb.0: # %entry99; CHECK-NEXT: vinsbrx v2, r5, r6100; CHECK-NEXT: blr101entry:102 %0 = tail call <16 x i8> @llvm.ppc.altivec.vinsbrx(<16 x i8> %a, i32 %b, i32 %c)103 ret <16 x i8> %0104}105declare <16 x i8> @llvm.ppc.altivec.vinsbrx(<16 x i8>, i32, i32)106 107define <8 x i16> @testVINSHLX(<8 x i16> %a, i32 %b, i32 %c) {108; CHECK-LABEL: testVINSHLX:109; CHECK: # %bb.0: # %entry110; CHECK-NEXT: vinshlx v2, r5, r6111; CHECK-NEXT: blr112entry:113 %0 = tail call <8 x i16> @llvm.ppc.altivec.vinshlx(<8 x i16> %a, i32 %b, i32 %c)114 ret <8 x i16> %0115}116declare <8 x i16> @llvm.ppc.altivec.vinshlx(<8 x i16>, i32, i32)117 118define <8 x i16> @testVINSHRX(<8 x i16> %a, i32 %b, i32 %c) {119; CHECK-LABEL: testVINSHRX:120; CHECK: # %bb.0: # %entry121; CHECK-NEXT: vinshrx v2, r5, r6122; CHECK-NEXT: blr123entry:124 %0 = tail call <8 x i16> @llvm.ppc.altivec.vinshrx(<8 x i16> %a, i32 %b, i32 %c)125 ret <8 x i16> %0126}127declare <8 x i16> @llvm.ppc.altivec.vinshrx(<8 x i16>, i32, i32)128 129define <4 x i32> @testVINSWLX(<4 x i32> %a, i32 %b, i32 %c) {130; CHECK-LABEL: testVINSWLX:131; CHECK: # %bb.0: # %entry132; CHECK-NEXT: vinswlx v2, r5, r6133; CHECK-NEXT: blr134entry:135 %0 = tail call <4 x i32> @llvm.ppc.altivec.vinswlx(<4 x i32> %a, i32 %b, i32 %c)136 ret <4 x i32> %0137}138declare <4 x i32> @llvm.ppc.altivec.vinswlx(<4 x i32>, i32, i32)139 140define <4 x i32> @testVINSWRX(<4 x i32> %a, i32 %b, i32 %c) {141; CHECK-LABEL: testVINSWRX:142; CHECK: # %bb.0: # %entry143; CHECK-NEXT: vinswrx v2, r5, r6144; CHECK-NEXT: blr145entry:146 %0 = tail call <4 x i32> @llvm.ppc.altivec.vinswrx(<4 x i32> %a, i32 %b, i32 %c)147 ret <4 x i32> %0148}149declare <4 x i32> @llvm.ppc.altivec.vinswrx(<4 x i32>, i32, i32)150 151define <2 x i64> @testVINSDLX(<2 x i64> %a, i64 %b, i64 %c) {152; CHECK-LABEL: testVINSDLX:153; CHECK: # %bb.0: # %entry154; CHECK-NEXT: vinsdlx v2, r5, r6155; CHECK-NEXT: blr156entry:157 %0 = tail call <2 x i64> @llvm.ppc.altivec.vinsdlx(<2 x i64> %a, i64 %b, i64 %c)158 ret <2 x i64> %0159}160declare <2 x i64> @llvm.ppc.altivec.vinsdlx(<2 x i64>, i64, i64)161 162define <2 x i64> @testVINSDRX(<2 x i64> %a, i64 %b, i64 %c) {163; CHECK-LABEL: testVINSDRX:164; CHECK: # %bb.0: # %entry165; CHECK-NEXT: vinsdrx v2, r5, r6166; CHECK-NEXT: blr167entry:168 %0 = tail call <2 x i64> @llvm.ppc.altivec.vinsdrx(<2 x i64> %a, i64 %b, i64 %c)169 ret <2 x i64> %0170}171declare <2 x i64> @llvm.ppc.altivec.vinsdrx(<2 x i64>, i64, i64)172 173define <16 x i8> @testVINSBVLX(<16 x i8> %a, i32 %b, <16 x i8> %c) {174; CHECK-LABEL: testVINSBVLX:175; CHECK: # %bb.0: # %entry176; CHECK-NEXT: vinsbvlx v2, r5, v3177; CHECK-NEXT: blr178entry:179 %0 = tail call <16 x i8> @llvm.ppc.altivec.vinsbvlx(<16 x i8> %a, i32 %b, <16 x i8> %c)180 ret <16 x i8> %0181}182declare <16 x i8> @llvm.ppc.altivec.vinsbvlx(<16 x i8>, i32, <16 x i8>)183 184define <16 x i8> @testVINSBVRX(<16 x i8> %a, i32 %b, <16 x i8> %c) {185; CHECK-LABEL: testVINSBVRX:186; CHECK: # %bb.0: # %entry187; CHECK-NEXT: vinsbvrx v2, r5, v3188; CHECK-NEXT: blr189entry:190 %0 = tail call <16 x i8> @llvm.ppc.altivec.vinsbvrx(<16 x i8> %a, i32 %b, <16 x i8> %c)191 ret <16 x i8> %0192}193declare <16 x i8> @llvm.ppc.altivec.vinsbvrx(<16 x i8>, i32, <16 x i8>)194 195define <8 x i16> @testVINSHVLX(<8 x i16> %a, i32 %b, <8 x i16> %c) {196; CHECK-LABEL: testVINSHVLX:197; CHECK: # %bb.0: # %entry198; CHECK-NEXT: vinshvlx v2, r5, v3199; CHECK-NEXT: blr200entry:201 %0 = tail call <8 x i16> @llvm.ppc.altivec.vinshvlx(<8 x i16> %a, i32 %b, <8 x i16> %c)202 ret <8 x i16> %0203}204declare <8 x i16> @llvm.ppc.altivec.vinshvlx(<8 x i16>, i32, <8 x i16>)205 206define <8 x i16> @testVINSHVRX(<8 x i16> %a, i32 %b, <8 x i16> %c) {207entry:208 %0 = tail call <8 x i16> @llvm.ppc.altivec.vinshvrx(<8 x i16> %a, i32 %b, <8 x i16> %c)209 ret <8 x i16> %0210}211declare <8 x i16> @llvm.ppc.altivec.vinshvrx(<8 x i16>, i32, <8 x i16>)212 213define <4 x i32> @testVINSWVLX(<4 x i32> %a, i32 %b, <4 x i32> %c) {214; CHECK-LABEL: testVINSWVLX:215; CHECK: # %bb.0: # %entry216; CHECK-NEXT: vinswvlx v2, r5, v3217; CHECK-NEXT: blr218entry:219 %0 = tail call <4 x i32> @llvm.ppc.altivec.vinswvlx(<4 x i32> %a, i32 %b, <4 x i32> %c)220 ret <4 x i32> %0221}222declare <4 x i32> @llvm.ppc.altivec.vinswvlx(<4 x i32>, i32, <4 x i32>)223 224define <4 x i32> @testVINSWVRX(<4 x i32> %a, i32 %b, <4 x i32> %c) {225; CHECK-LABEL: testVINSWVRX:226; CHECK: # %bb.0: # %entry227; CHECK-NEXT: vinswvrx v2, r5, v3228; CHECK-NEXT: blr229entry:230 %0 = tail call <4 x i32> @llvm.ppc.altivec.vinswvrx(<4 x i32> %a, i32 %b, <4 x i32> %c)231 ret <4 x i32> %0232}233declare <4 x i32> @llvm.ppc.altivec.vinswvrx(<4 x i32>, i32, <4 x i32>)234 235define <4 x i32> @testVINSW(<4 x i32> %a, i32 %b) {236; CHECK-LABEL: testVINSW:237; CHECK: # %bb.0: # %entry238; CHECK-NEXT: vinsw v2, r5, 1239; CHECK-NEXT: blr240entry:241 %0 = tail call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> %a, i32 %b, i32 1)242 ret <4 x i32> %0243}244declare <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32>, i32, i32 immarg)245 246define <2 x i64> @testVINSD(<2 x i64> %a, i64 %b) {247; CHECK-LABEL: testVINSD:248; CHECK: # %bb.0: # %entry249; CHECK-NEXT: vinsd v2, r5, 1250; CHECK-NEXT: blr251entry:252 %0 = tail call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> %a, i64 %b, i32 1)253 ret <2 x i64> %0254}255declare <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64>, i64, i32 immarg)256 257define <2 x i64> @testVEXTDUBVLX(<16 x i8> %a, <16 x i8> %b, i32 %c) {258; CHECK-LABEL: testVEXTDUBVLX:259; CHECK: # %bb.0: # %entry260; CHECK-NEXT: vextdubvlx v2, v2, v3, r7261; CHECK-NEXT: blr262entry:263 %0 = tail call <2 x i64> @llvm.ppc.altivec.vextdubvlx(<16 x i8> %a, <16 x i8> %b, i32 %c)264 ret <2 x i64> %0265}266declare <2 x i64> @llvm.ppc.altivec.vextdubvlx(<16 x i8>, <16 x i8>, i32)267 268define <2 x i64> @testVEXTDUBVRX(<16 x i8> %a, <16 x i8> %b, i32 %c) {269; CHECK-LABEL: testVEXTDUBVRX:270; CHECK: # %bb.0: # %entry271; CHECK-NEXT: vextdubvrx v2, v2, v3, r7272; CHECK-NEXT: blr273entry:274 %0 = tail call <2 x i64> @llvm.ppc.altivec.vextdubvrx(<16 x i8> %a, <16 x i8> %b, i32 %c)275 ret <2 x i64> %0276}277declare <2 x i64> @llvm.ppc.altivec.vextdubvrx(<16 x i8>, <16 x i8>, i32)278 279define <2 x i64> @testVEXTDUHVLX(<8 x i16> %a, <8 x i16> %b, i32 %c) {280; CHECK-LABEL: testVEXTDUHVLX:281; CHECK: # %bb.0: # %entry282; CHECK-NEXT: vextduhvlx v2, v2, v3, r7283; CHECK-NEXT: blr284entry:285 %0 = tail call <2 x i64> @llvm.ppc.altivec.vextduhvlx(<8 x i16> %a, <8 x i16> %b, i32 %c)286 ret <2 x i64> %0287}288declare <2 x i64> @llvm.ppc.altivec.vextduhvlx(<8 x i16>, <8 x i16>, i32)289 290define <2 x i64> @testVEXTDUHVRX(<8 x i16> %a, <8 x i16> %b, i32 %c) {291; CHECK-LABEL: testVEXTDUHVRX:292; CHECK: # %bb.0: # %entry293; CHECK-NEXT: vextduhvrx v2, v2, v3, r7294; CHECK-NEXT: blr295entry:296 %0 = tail call <2 x i64> @llvm.ppc.altivec.vextduhvrx(<8 x i16> %a, <8 x i16> %b, i32 %c)297 ret <2 x i64> %0298}299declare <2 x i64> @llvm.ppc.altivec.vextduhvrx(<8 x i16>, <8 x i16>, i32)300 301define <2 x i64> @testVEXTDUWVLX(<4 x i32> %a, <4 x i32> %b, i32 %c) {302; CHECK-LABEL: testVEXTDUWVLX:303; CHECK: # %bb.0: # %entry304; CHECK-NEXT: vextduwvlx v2, v2, v3, r7305; CHECK-NEXT: blr306entry:307 %0 = tail call <2 x i64> @llvm.ppc.altivec.vextduwvlx(<4 x i32> %a, <4 x i32> %b, i32 %c)308 ret <2 x i64> %0309}310declare <2 x i64> @llvm.ppc.altivec.vextduwvlx(<4 x i32>, <4 x i32>, i32)311 312define <2 x i64> @testVEXTDUWVRX(<4 x i32> %a, <4 x i32> %b, i32 %c) {313; CHECK-LABEL: testVEXTDUWVRX:314; CHECK: # %bb.0: # %entry315; CHECK-NEXT: vextduwvrx v2, v2, v3, r7316; CHECK-NEXT: blr317entry:318 %0 = tail call <2 x i64> @llvm.ppc.altivec.vextduwvrx(<4 x i32> %a, <4 x i32> %b, i32 %c)319 ret <2 x i64> %0320}321declare <2 x i64> @llvm.ppc.altivec.vextduwvrx(<4 x i32>, <4 x i32>, i32)322 323define <2 x i64> @testVEXTDDVLX(<2 x i64> %a, <2 x i64> %b, i32 %c) {324; CHECK-LABEL: testVEXTDDVLX:325; CHECK: # %bb.0: # %entry326; CHECK-NEXT: vextddvlx v2, v2, v3, r7327; CHECK-NEXT: blr328entry:329 %0 = tail call <2 x i64> @llvm.ppc.altivec.vextddvlx(<2 x i64> %a, <2 x i64> %b, i32 %c)330 ret <2 x i64> %0331}332declare <2 x i64> @llvm.ppc.altivec.vextddvlx(<2 x i64>, <2 x i64>, i32)333 334define <2 x i64> @testVEXTDDVRX(<2 x i64> %a, <2 x i64> %b, i32 %c) {335; CHECK-LABEL: testVEXTDDVRX:336; CHECK: # %bb.0: # %entry337; CHECK-NEXT: vextddvrx v2, v2, v3, r7338; CHECK-NEXT: blr339entry:340 %0 = tail call <2 x i64> @llvm.ppc.altivec.vextddvrx(<2 x i64> %a, <2 x i64> %b, i32 %c)341 ret <2 x i64> %0342}343declare <2 x i64> @llvm.ppc.altivec.vextddvrx(<2 x i64>, <2 x i64>, i32)344