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1; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+power8-vector -mattr=-vsx < %s | FileCheck %s4; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-VSX5 6@vsc = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 167@vsc2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 168@vuc = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 169@vuc2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 1610@res_vll = common global <2 x i64> zeroinitializer, align 1611@res_vull = common global <2 x i64> zeroinitializer, align 1612@res_vsc = common global <16 x i8> zeroinitializer, align 1613@res_vuc = common global <16 x i8> zeroinitializer, align 1614 15; Function Attrs: nounwind16define void @test1() {17entry:18 %0 = load <16 x i8>, ptr @vsc, align 1619 %1 = load <16 x i8>, ptr @vsc2, align 1620 %2 = call <2 x i64> @llvm.ppc.altivec.vbpermq(<16 x i8> %0, <16 x i8> %1)21 store <2 x i64> %2, ptr @res_vll, align 1622 ret void23; CHECK-LABEL: @test124; CHECK: lvx [[REG1:[0-9]+]], 0, 325; CHECK: lvx [[REG2:[0-9]+]], 0, 326; CHECK: vbpermq {{[0-9]+}}, [[REG1]], [[REG2]]27; CHECK-VSX: vbpermq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}28}29 30; Function Attrs: nounwind31define void @test2() {32entry:33 %0 = load <16 x i8>, ptr @vuc, align 1634 %1 = load <16 x i8>, ptr @vuc2, align 1635 %2 = call <2 x i64> @llvm.ppc.altivec.vbpermq(<16 x i8> %0, <16 x i8> %1)36 store <2 x i64> %2, ptr @res_vull, align 1637 ret void38; CHECK-LABEL: @test239; CHECK: lvx [[REG1:[0-9]+]], 0, 340; CHECK: lvx [[REG2:[0-9]+]], 0, 341; CHECK: vbpermq {{[0-9]+}}, [[REG1]], [[REG2]]42; CHECK-VSX: vbpermq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}43}44 45; Function Attrs: nounwind46define void @test3() {47entry:48 %0 = load <16 x i8>, ptr @vsc, align 1649 %1 = call <16 x i8> @llvm.ppc.altivec.vgbbd(<16 x i8> %0)50 store <16 x i8> %1, ptr @res_vsc, align 1651 ret void52; CHECK-LABEL: @test353; CHECK: lvx [[REG1:[0-9]+]],54; CHECK: vgbbd {{[0-9]+}}, [[REG1]]55; CHECK-VSX: vgbbd {{[0-9]+}}, {{[0-9]+}}56}57 58; Function Attrs: nounwind59define void @test4() {60entry:61 %0 = load <16 x i8>, ptr @vuc, align 1662 %1 = call <16 x i8> @llvm.ppc.altivec.vgbbd(<16 x i8> %0)63 store <16 x i8> %1, ptr @res_vuc, align 1664 ret void65; CHECK-LABEL: @test466; CHECK: lvx [[REG1:[0-9]+]],67; CHECK: vgbbd {{[0-9]+}}, [[REG1]]68; CHECK-VSX: vgbbd {{[0-9]+}}, {{[0-9]+}}69}70 71; Function Attrs: nounwind readnone72declare <2 x i64> @llvm.ppc.altivec.vbpermq(<16 x i8>, <16 x i8>)73 74; Function Attrs: nounwind readnone75declare <16 x i8> @llvm.ppc.altivec.vgbbd(<16 x i8>)76