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1; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \2; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s3 4@A = common global fp128 0xL00000000000000000000000000000000, align 165@B = common global fp128 0xL00000000000000000000000000000000, align 166@C = common global fp128 0xL00000000000000000000000000000000, align 167@D = common global fp128 0xL00000000000000000000000000000000, align 168 9define fp128 @testSqrtOdd(fp128 %a) {10entry:11 %0 = call fp128 @llvm.ppc.sqrtf128.round.to.odd(fp128 %a)12 ret fp128 %013; CHECK-LABEL: testSqrtOdd14; CHECK: xssqrtqpo v2, v215; CHECK: blr16}17 18declare fp128 @llvm.ppc.sqrtf128.round.to.odd(fp128)19 20define void @testFMAOdd(fp128 %a, fp128 %b, fp128 %c) {21entry:22 %0 = call fp128 @llvm.ppc.fmaf128.round.to.odd(fp128 %a, fp128 %b, fp128 %c)23 store fp128 %0, ptr @A, align 1624 %sub = fsub fp128 0xL00000000000000008000000000000000, %c25 %1 = call fp128 @llvm.ppc.fmaf128.round.to.odd(fp128 %a, fp128 %b, fp128 %sub)26 store fp128 %1, ptr @B, align 1627 %2 = call fp128 @llvm.ppc.fmaf128.round.to.odd(fp128 %a, fp128 %b, fp128 %c)28 %sub1 = fsub fp128 0xL00000000000000008000000000000000, %229 store fp128 %sub1, ptr @C, align 1630 %sub2 = fsub fp128 0xL00000000000000008000000000000000, %c31 %3 = call fp128 @llvm.ppc.fmaf128.round.to.odd(fp128 %a, fp128 %b, fp128 %sub2)32 %sub3 = fsub fp128 0xL00000000000000008000000000000000, %333 store fp128 %sub3, ptr @D, align 1634 ret void35; CHECK-LABEL: testFMAOdd36; CHECK-DAG: xsmaddqpo v{{[0-9]+}}, v2, v337; CHECK-DAG: xsmsubqpo v{{[0-9]+}}, v2, v338; CHECK-DAG: xsnmaddqpo v{{[0-9]+}}, v2, v339; CHECK-DAG: xsnmsubqpo v{{[0-9]+}}, v2, v340; CHECK: blr41}42 43declare fp128 @llvm.ppc.fmaf128.round.to.odd(fp128, fp128, fp128)44 45define fp128 @testAddOdd(fp128 %a, fp128 %b) {46entry:47 %0 = call fp128 @llvm.ppc.addf128.round.to.odd(fp128 %a, fp128 %b)48 ret fp128 %049; CHECK-LABEL: testAddOdd50; CHECK: xsaddqpo v2, v2, v351; CHECK: blr52}53 54declare fp128 @llvm.ppc.addf128.round.to.odd(fp128, fp128)55 56define fp128 @testSubOdd(fp128 %a, fp128 %b) {57entry:58 %0 = call fp128 @llvm.ppc.subf128.round.to.odd(fp128 %a, fp128 %b)59 ret fp128 %060; CHECK-LABEL: testSubOdd61; CHECK: xssubqpo v2, v2, v362; CHECK: blr63}64 65; Function Attrs: nounwind readnone66declare fp128 @llvm.ppc.subf128.round.to.odd(fp128, fp128)67 68; Function Attrs: noinline nounwind optnone69define fp128 @testMulOdd(fp128 %a, fp128 %b) {70entry:71 %0 = call fp128 @llvm.ppc.mulf128.round.to.odd(fp128 %a, fp128 %b)72 ret fp128 %073; CHECK-LABEL: testMulOdd74; CHECK: xsmulqpo v2, v2, v375; CHECK: blr76}77 78; Function Attrs: nounwind readnone79declare fp128 @llvm.ppc.mulf128.round.to.odd(fp128, fp128)80 81define fp128 @testDivOdd(fp128 %a, fp128 %b) {82entry:83 %0 = call fp128 @llvm.ppc.divf128.round.to.odd(fp128 %a, fp128 %b)84 ret fp128 %085; CHECK-LABEL: testDivOdd86; CHECK: xsdivqpo v2, v2, v387; CHECK: blr88}89 90declare fp128 @llvm.ppc.divf128.round.to.odd(fp128, fp128)91 92define double @testTruncOdd(fp128 %a) {93entry:94 %0 = call double @llvm.ppc.truncf128.round.to.odd(fp128 %a)95 ret double %096; CHECK-LABEL: testTruncOdd97; CHECK: xscvqpdpo v2, v298; CHECK: xscpsgndp f1, v2, v299; CHECK: blr100}101 102declare double @llvm.ppc.truncf128.round.to.odd(fp128)103 104; Function Attrs: noinline nounwind optnone105define fp128 @insert_exp_qp(i64 %b) {106entry:107 %b.addr = alloca i64, align 8108 store i64 %b, ptr %b.addr, align 8109 %0 = load fp128, ptr @A, align 16110 %1 = load i64, ptr %b.addr, align 8111 %2 = call fp128 @llvm.ppc.scalar.insert.exp.qp(fp128 %0, i64 %1)112 ret fp128 %2113; CHECK-LABEL: insert_exp_qp114; CHECK-DAG: mtfprd [[FPREG:f[0-9]+]], r3115; CHECK-DAG: lxv [[VECREG:v[0-9]+]]116; CHECK: xsiexpqp v2, [[VECREG]], [[FPREG]]117; CHECK: blr118}119 120; Function Attrs: nounwind readnone121declare fp128 @llvm.ppc.scalar.insert.exp.qp(fp128, i64)122 123; Function Attrs: noinline nounwind optnone124define i64 @extract_exp() {125entry:126 %0 = load fp128, ptr @A, align 16127 %1 = call i64 @llvm.ppc.scalar.extract.expq(fp128 %0)128 ret i64 %1129; CHECK-LABEL: extract_exp130; CHECK: lxv [[VECIN:v[0-9]+]]131; CHECK: xsxexpqp [[VECOUT:v[0-9]+]], [[VECIN]]132; CHECK: mfvsrd r3, [[VECOUT]]133; CHECK: blr134}135 136; Function Attrs: nounwind readnone137declare i64 @llvm.ppc.scalar.extract.expq(fp128)138 139define i32 @test_data_class_f128(fp128 %d) {140entry:141 %test_data_class = tail call i32 @llvm.ppc.test.data.class.f128(fp128 %d, i32 0)142 ret i32 %test_data_class143; CHECK-LABEL: test_data_class_f128:144; CHECK: xststdcqp cr0, v2, 0145; CHECK-NEXT: li r3, 0146; CHECK-NEXT: li r4, 1147; CHECK-NEXT: iseleq r3, r4, r3148; CHECK-NEXT: blr149}150 151declare i32 @llvm.ppc.test.data.class.f128(fp128, i32 immarg)152