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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown | FileCheck %s3 4; Infinite loop identified in D62963.5define <4 x double> @fneg_fdiv_splat(double %a0, <4 x double> %a1) {6; CHECK-LABEL: fneg_fdiv_splat:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha9; CHECK-NEXT: xxspltd 0, 1, 010; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l11; CHECK-NEXT: xvredp 1, 012; CHECK-NEXT: lxvd2x 2, 0, 313; CHECK-NEXT: xxlor 3, 2, 214; CHECK-NEXT: xvmaddadp 3, 0, 115; CHECK-NEXT: xvnmsubadp 1, 1, 316; CHECK-NEXT: xvmaddadp 2, 0, 117; CHECK-NEXT: xvmsubadp 1, 1, 218; CHECK-NEXT: xvmuldp 34, 34, 119; CHECK-NEXT: xvmuldp 35, 35, 120; CHECK-NEXT: blr21entry:22 %splat.splatinsert = insertelement <4 x double> undef, double %a0, i32 023 %splat.splat = shufflevector <4 x double> %splat.splatinsert, <4 x double> undef, <4 x i32> zeroinitializer24 %div = fdiv contract reassoc nsz arcp ninf <4 x double> %a1, %splat.splat25 %sub = fsub contract reassoc nsz <4 x double> <double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00>, %div26 ret <4 x double> %sub27}28