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1; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \2; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \3; RUN: FileCheck %s4 5; These tests show that for 32-bit and 64-bit scalars, combining a shift to6; a single multiply-high is only valid when the shift amount is the same as7; the width of the narrow type.8 9; That is, combining a shift to mulh is only valid for 32-bit when the shift10; amount is 32.11; Likewise, combining a shift to mulh is only valid for 64-bit when the shift12; amount is 64.13 14define i32 @test_mulhw(i32 %a, i32 %b) {15; CHECK-LABEL: test_mulhw:16; CHECK: mulld17; CHECK-NOT: mulhw18; CHECK: blr19 %1 = sext i32 %a to i6420 %2 = sext i32 %b to i6421 %mul = mul i64 %1, %222 %shr = lshr i64 %mul, 3323 %tr = trunc i64 %shr to i3224 ret i32 %tr25}26 27define i32 @test_mulhu(i32 %a, i32 %b) {28; CHECK-LABEL: test_mulhu:29; CHECK: mulld30; CHECK-NOT: mulhwu31; CHECK: blr32 %1 = zext i32 %a to i6433 %2 = zext i32 %b to i6434 %mul = mul i64 %1, %235 %shr = lshr i64 %mul, 3336 %tr = trunc i64 %shr to i3237 ret i32 %tr38}39 40define i64 @test_mulhd(i64 %a, i64 %b) {41; CHECK-LABEL: test_mulhd:42; CHECK: mulhd43; CHECK: mulld44; CHECK: blr45 %1 = sext i64 %a to i12846 %2 = sext i64 %b to i12847 %mul = mul i128 %1, %248 %shr = lshr i128 %mul, 6349 %tr = trunc i128 %shr to i6450 ret i64 %tr51}52 53define i64 @test_mulhdu(i64 %a, i64 %b) {54; CHECK-LABEL: test_mulhdu:55; CHECK: mulhdu56; CHECK: mulld57; CHECK: blr58 %1 = zext i64 %a to i12859 %2 = zext i64 %b to i12860 %mul = mul i128 %1, %261 %shr = lshr i128 %mul, 6362 %tr = trunc i128 %shr to i6463 ret i64 %tr64}65 66define signext i32 @test_mulhw_signext(i32 %a, i32 %b) {67; CHECK-LABEL: test_mulhw_signext:68; CHECK: mulld69; CHECK-NOT: mulhw70; CHECK: blr71 %1 = sext i32 %a to i6472 %2 = sext i32 %b to i6473 %mul = mul i64 %1, %274 %shr = lshr i64 %mul, 3375 %tr = trunc i64 %shr to i3276 ret i32 %tr77}78 79define zeroext i32 @test_mulhu_zeroext(i32 %a, i32 %b) {80; CHECK-LABEL: test_mulhu_zeroext:81; CHECK: mulld82; CHECK-NOT: mulhwu83; CHECK: blr84 %1 = zext i32 %a to i6485 %2 = zext i32 %b to i6486 %mul = mul i64 %1, %287 %shr = lshr i64 %mul, 3388 %tr = trunc i64 %shr to i3289 ret i32 %tr90}91 92define signext i64 @test_mulhd_signext(i64 %a, i64 %b) {93; CHECK-LABEL: test_mulhd_signext:94; CHECK: mulhd95; CHECK: mulld96; CHECK: blr97 %1 = sext i64 %a to i12898 %2 = sext i64 %b to i12899 %mul = mul i128 %1, %2100 %shr = lshr i128 %mul, 63101 %tr = trunc i128 %shr to i64102 ret i64 %tr103}104 105define zeroext i64 @test_mulhdu_zeroext(i64 %a, i64 %b) {106; CHECK-LABEL: test_mulhdu_zeroext:107; CHECK: mulhdu108; CHECK: mulld109; CHECK: blr110 %1 = zext i64 %a to i128111 %2 = zext i64 %b to i128112 %mul = mul i128 %1, %2113 %shr = lshr i128 %mul, 63114 %tr = trunc i128 %shr to i64115 ret i64 %tr116}117