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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -verify-machineinstrs \3; RUN: -mtriple=powerpc64-- -mcpu=pwr7 < %s | FileCheck \4; RUN: --check-prefix=PWR7-BE %s5; RUN: llc -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -verify-machineinstrs \6; RUN: -mtriple=powerpc64-- -mcpu=pwr8 < %s | FileCheck \7; RUN: --check-prefix=PWR8-BE %s8; RUN: llc -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -verify-machineinstrs \9; RUN: -mtriple=powerpc64le-- -mcpu=pwr8 < %s | FileCheck \10; RUN: --check-prefix=PWR8-LE %s11 12define <16 x i8> @i8(ptr nocapture noundef readonly %p) {13; PWR7-BE-LABEL: i8:14; PWR7-BE: # %bb.0: # %entry15; PWR7-BE-NEXT: lxvw4x v3, 0, r316; PWR7-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha17; PWR7-BE-NEXT: vspltisb v2, 1018; PWR7-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l19; PWR7-BE-NEXT: lxvw4x v4, 0, r320; PWR7-BE-NEXT: vperm v2, v3, v2, v421; PWR7-BE-NEXT: blr22;23; PWR8-BE-LABEL: i8:24; PWR8-BE: # %bb.0: # %entry25; PWR8-BE-NEXT: lxvw4x v2, 0, r326; PWR8-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha27; PWR8-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l28; PWR8-BE-NEXT: lxvw4x v3, 0, r329; PWR8-BE-NEXT: li r3, 1030; PWR8-BE-NEXT: mtvsrwz v4, r331; PWR8-BE-NEXT: vperm v2, v2, v4, v332; PWR8-BE-NEXT: blr33;34; PWR8-LE-LABEL: i8:35; PWR8-LE: # %bb.0: # %entry36; PWR8-LE-NEXT: lxvd2x vs0, 0, r337; PWR8-LE-NEXT: addis r3, r2, .LCPI0_0@toc@ha38; PWR8-LE-NEXT: addi r3, r3, .LCPI0_0@toc@l39; PWR8-LE-NEXT: xxswapd v2, vs040; PWR8-LE-NEXT: lxvd2x vs0, 0, r341; PWR8-LE-NEXT: li r3, 1042; PWR8-LE-NEXT: mtvsrd v4, r343; PWR8-LE-NEXT: xxswapd v3, vs044; PWR8-LE-NEXT: vperm v2, v4, v2, v345; PWR8-LE-NEXT: blr46entry:47 %0 = load <16 x i8>, ptr %p, align 1648 %vecinit1 = insertelement <16 x i8> %0, i8 10, i64 149 ret <16 x i8> %vecinit150}51 52define <8 x i16> @i16(ptr nocapture noundef readonly %p) {53; PWR7-BE-LABEL: i16:54; PWR7-BE: # %bb.0: # %entry55; PWR7-BE-NEXT: lxvw4x v3, 0, r356; PWR7-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha57; PWR7-BE-NEXT: vspltish v2, 958; PWR7-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l59; PWR7-BE-NEXT: lxvw4x v4, 0, r360; PWR7-BE-NEXT: vperm v2, v3, v2, v461; PWR7-BE-NEXT: blr62;63; PWR8-BE-LABEL: i16:64; PWR8-BE: # %bb.0: # %entry65; PWR8-BE-NEXT: lxvw4x v2, 0, r366; PWR8-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha67; PWR8-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l68; PWR8-BE-NEXT: lxvw4x v3, 0, r369; PWR8-BE-NEXT: li r3, 970; PWR8-BE-NEXT: mtvsrwz v4, r371; PWR8-BE-NEXT: vperm v2, v2, v4, v372; PWR8-BE-NEXT: blr73;74; PWR8-LE-LABEL: i16:75; PWR8-LE: # %bb.0: # %entry76; PWR8-LE-NEXT: lxvd2x vs0, 0, r377; PWR8-LE-NEXT: addis r3, r2, .LCPI1_0@toc@ha78; PWR8-LE-NEXT: addi r3, r3, .LCPI1_0@toc@l79; PWR8-LE-NEXT: xxswapd v2, vs080; PWR8-LE-NEXT: lxvd2x vs0, 0, r381; PWR8-LE-NEXT: li r3, 982; PWR8-LE-NEXT: mtvsrd v4, r383; PWR8-LE-NEXT: xxswapd v3, vs084; PWR8-LE-NEXT: vperm v2, v4, v2, v385; PWR8-LE-NEXT: blr86entry:87 %0 = load <8 x i16>, ptr %p, align 1688 %vecinit1 = insertelement <8 x i16> %0, i16 9, i64 189 ret <8 x i16> %vecinit190}91 92define <4 x i32> @i32(ptr nocapture noundef readonly %p) {93; PWR7-BE-LABEL: i32:94; PWR7-BE: # %bb.0: # %entry95; PWR7-BE-NEXT: lxvw4x v3, 0, r396; PWR7-BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha97; PWR7-BE-NEXT: vspltisw v2, 798; PWR7-BE-NEXT: addi r3, r3, .LCPI2_0@toc@l99; PWR7-BE-NEXT: lxvw4x v4, 0, r3100; PWR7-BE-NEXT: vperm v2, v3, v2, v4101; PWR7-BE-NEXT: blr102;103; PWR8-BE-LABEL: i32:104; PWR8-BE: # %bb.0: # %entry105; PWR8-BE-NEXT: lxvw4x v2, 0, r3106; PWR8-BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha107; PWR8-BE-NEXT: addi r3, r3, .LCPI2_0@toc@l108; PWR8-BE-NEXT: lxvw4x v3, 0, r3109; PWR8-BE-NEXT: li r3, 7110; PWR8-BE-NEXT: mtvsrwz v4, r3111; PWR8-BE-NEXT: vperm v2, v2, v4, v3112; PWR8-BE-NEXT: blr113;114; PWR8-LE-LABEL: i32:115; PWR8-LE: # %bb.0: # %entry116; PWR8-LE-NEXT: lxvd2x vs0, 0, r3117; PWR8-LE-NEXT: addis r3, r2, .LCPI2_0@toc@ha118; PWR8-LE-NEXT: addi r3, r3, .LCPI2_0@toc@l119; PWR8-LE-NEXT: xxswapd v2, vs0120; PWR8-LE-NEXT: lxvd2x vs0, 0, r3121; PWR8-LE-NEXT: li r3, 7122; PWR8-LE-NEXT: mtvsrwz v4, r3123; PWR8-LE-NEXT: xxswapd v3, vs0124; PWR8-LE-NEXT: vperm v2, v4, v2, v3125; PWR8-LE-NEXT: blr126entry:127 %0 = load <4 x i32>, ptr %p, align 16128 %vecinit1 = insertelement <4 x i32> %0, i32 7, i64 1129 ret <4 x i32> %vecinit1130}131 132define <2 x i64> @i64(ptr nocapture noundef readonly %p) {133; PWR7-BE-LABEL: i64:134; PWR7-BE: # %bb.0: # %entry135; PWR7-BE-NEXT: lxvd2x v2, 0, r3136; PWR7-BE-NEXT: li r3, 10137; PWR7-BE-NEXT: std r3, -16(r1)138; PWR7-BE-NEXT: std r3, -8(r1)139; PWR7-BE-NEXT: addi r3, r1, -16140; PWR7-BE-NEXT: lxvd2x v3, 0, r3141; PWR7-BE-NEXT: xxmrghd v2, v2, v3142; PWR7-BE-NEXT: blr143;144; PWR8-BE-LABEL: i64:145; PWR8-BE: # %bb.0: # %entry146; PWR8-BE-NEXT: lxvd2x v2, 0, r3147; PWR8-BE-NEXT: li r3, 10148; PWR8-BE-NEXT: mtfprd f0, r3149; PWR8-BE-NEXT: xxmrghd v2, v2, vs0150; PWR8-BE-NEXT: blr151;152; PWR8-LE-LABEL: i64:153; PWR8-LE: # %bb.0: # %entry154; PWR8-LE-NEXT: lxvd2x vs0, 0, r3155; PWR8-LE-NEXT: li r3, 10156; PWR8-LE-NEXT: xxswapd v2, vs0157; PWR8-LE-NEXT: mtfprd f0, r3158; PWR8-LE-NEXT: xxpermdi v2, vs0, v2, 1159; PWR8-LE-NEXT: blr160entry:161 %0 = load <2 x i64>, ptr %p, align 16162 %vecinit1 = insertelement <2 x i64> %0, i64 10, i64 1163 ret <2 x i64> %vecinit1164}165