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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple powerpc64-unknown-linux-gnu -mcpu=ppc64 < %s | FileCheck %s3; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=ppc64 < %s | FileCheck %s4 5; Function Attrs: nounwind readnone6define i64 @cn1() #0 {7; CHECK-LABEL: cn1:8; CHECK: # %bb.0: # %entry9; CHECK-NEXT: li 3, -110; CHECK-NEXT: rldic 3, 3, 0, 1611; CHECK-NEXT: blr12entry:13 ret i64 28147497671065514 15}16 17; Function Attrs: nounwind readnone18define i64 @cnb() #0 {19; CHECK-LABEL: cnb:20; CHECK: # %bb.0: # %entry21; CHECK-NEXT: li 3, -8122; CHECK-NEXT: rldic 3, 3, 0, 1623; CHECK-NEXT: blr24entry:25 ret i64 28147497671057526 27}28 29; Function Attrs: nounwind readnone30define i64 @f2(i64 %x) #0 {31; CHECK-LABEL: f2:32; CHECK: # %bb.0: # %entry33; CHECK-NEXT: li 3, -134; CHECK-NEXT: rldic 3, 3, 36, 035; CHECK-NEXT: blr36entry:37 ret i64 -6871947673638 39}40 41; Function Attrs: nounwind readnone42define i64 @f2a(i64 %x) #0 {43; CHECK-LABEL: f2a:44; CHECK: # %bb.0: # %entry45; CHECK-NEXT: li 3, -33746; CHECK-NEXT: rldic 3, 3, 30, 047; CHECK-NEXT: blr48entry:49 ret i64 -36185099468850 51}52 53; Function Attrs: nounwind readnone54define i64 @f2n(i64 %x) #0 {55; CHECK-LABEL: f2n:56; CHECK: # %bb.0: # %entry57; CHECK-NEXT: li 3, -158; CHECK-NEXT: rldic 3, 3, 0, 2859; CHECK-NEXT: blr60entry:61 ret i64 6871947673562 63}64 65; Function Attrs: nounwind readnone66define i64 @f3(i64 %x) #0 {67; CHECK-LABEL: f3:68; CHECK: # %bb.0: # %entry69; CHECK-NEXT: li 3, -170; CHECK-NEXT: rldic 3, 3, 0, 3171; CHECK-NEXT: blr72entry:73 ret i64 858993459174 75}76 77; Function Attrs: nounwind readnone78define i64 @cn2n() #0 {79; CHECK-LABEL: cn2n:80; CHECK: # %bb.0: # %entry81; CHECK-NEXT: lis 3, -512182; CHECK-NEXT: ori 3, 3, 6553483; CHECK-NEXT: rotldi 3, 3, 2284; CHECK-NEXT: blr85entry:86 ret i64 -140737488774758587 88}89 90define i64 @uint32_1() #0 {91; CHECK-LABEL: uint32_1:92; CHECK: # %bb.0: # %entry93; CHECK-NEXT: li 3, 1817694; CHECK-NEXT: oris 3, 3, 5950995; CHECK-NEXT: blr96entry:97 ret i64 390000000098 99}100 101define i32 @uint32_1_i32() #0 {102; CHECK-LABEL: uint32_1_i32:103; CHECK: # %bb.0: # %entry104; CHECK-NEXT: li 3, 18176105; CHECK-NEXT: oris 3, 3, 59509106; CHECK-NEXT: blr107entry:108 ret i32 -394967296109 110}111 112define i64 @uint32_2() #0 {113; CHECK-LABEL: uint32_2:114; CHECK: # %bb.0: # %entry115; CHECK-NEXT: li 3, -1116; CHECK-NEXT: rldic 3, 3, 0, 32117; CHECK-NEXT: blr118entry:119 ret i64 4294967295120 121}122 123define i32 @uint32_2_i32() #0 {124; CHECK-LABEL: uint32_2_i32:125; CHECK: # %bb.0: # %entry126; CHECK-NEXT: li 3, -1127; CHECK-NEXT: rldic 3, 3, 0, 32128; CHECK-NEXT: blr129entry:130 ret i32 -1131 132}133 134define i64 @uint32_3() #0 {135; CHECK-LABEL: uint32_3:136; CHECK: # %bb.0: # %entry137; CHECK-NEXT: li 3, 1138; CHECK-NEXT: rldic 3, 3, 31, 32139; CHECK-NEXT: blr140entry:141 ret i64 2147483648142 143}144 145define i64 @uint32_4() #0 {146; CHECK-LABEL: uint32_4:147; CHECK: # %bb.0: # %entry148; CHECK-NEXT: lis 3, -6027149; CHECK-NEXT: ori 3, 3, 18177150; CHECK-NEXT: rldic 3, 3, 5, 27151; CHECK-NEXT: blr152entry:153 ret i64 124800000032154 155}156 157define i64 @cn_ones_1() #0 {158; CHECK-LABEL: cn_ones_1:159; CHECK: # %bb.0: # %entry160; CHECK-NEXT: li 3, -25633161; CHECK-NEXT: rldicl 3, 3, 18, 30162; CHECK-NEXT: blr163entry:164 ret i64 10460594175165 166}167 168define i64 @cn_ones_2() #0 {169; CHECK-LABEL: cn_ones_2:170; CHECK: # %bb.0: # %entry171; CHECK-NEXT: lis 3, -25638172; CHECK-NEXT: ori 3, 3, 24575173; CHECK-NEXT: rldicl 3, 3, 2, 30174; CHECK-NEXT: blr175entry:176 ret i64 10459119615177 178}179 180define i64 @imm1() #0 {181; CHECK-LABEL: imm1:182; CHECK: # %bb.0: # %entry183; CHECK-NEXT: li 3, 8465184; CHECK-NEXT: rldic 3, 3, 28, 22185; CHECK-NEXT: blr186entry:187 ret i64 2272306135040 ;0x21110000000188}189 190define i64 @imm2() #0 {191; CHECK-LABEL: imm2:192; CHECK: # %bb.0: # %entry193; CHECK-NEXT: li 3, -28536194; CHECK-NEXT: rldicl 3, 3, 1, 32195; CHECK-NEXT: blr196entry:197 ret i64 4294910225 ;0xFFFF2111198}199 200define i64 @imm3() #0 {201; CHECK-LABEL: imm3:202; CHECK: # %bb.0: # %entry203; CHECK-NEXT: li 3, -32495204; CHECK-NEXT: rldic 3, 3, 0, 32205; CHECK-NEXT: blr206entry:207 ret i64 4294934801 ;0xFFFF8111208}209 210define i64 @imm4() #0 {211; CHECK-LABEL: imm4:212; CHECK: # %bb.0: # %entry213; CHECK-NEXT: lis 3, 33214; CHECK-NEXT: ori 3, 3, 4352215; CHECK-NEXT: rldimi 3, 3, 32, 0216; CHECK-NEXT: blr217entry:218 ret i64 9307365931290880 ;0x21110000211100219}220 221define i64 @imm5() #0 {222; CHECK-LABEL: imm5:223; CHECK: # %bb.0: # %entry224; CHECK-NEXT: li 3, 28685225; CHECK-NEXT: rotldi 3, 3, 52226; CHECK-NEXT: blr227entry:228 ret i64 58546795155816455 ;0xd0000000000007229}230 231define i64 @imm6() #0 {232; CHECK-LABEL: imm6:233; CHECK: # %bb.0: # %entry234; CHECK-NEXT: lis 3, -1235; CHECK-NEXT: ori 3, 3, 28674236; CHECK-NEXT: rotldi 3, 3, 52237; CHECK-NEXT: blr238entry:239 ret i64 13510798882111479 ;0x2ffffffffffff7240}241 242define i64 @imm7() #0 {243; CHECK-LABEL: imm7:244; CHECK: # %bb.0: # %entry245; CHECK-NEXT: li 3, -3823246; CHECK-NEXT: rldic 3, 3, 28, 20247; CHECK-NEXT: blr248entry:249 ret i64 16565957296128 ;0xf1110000000250}251 252define i64 @imm8() #0 {253; CHECK-LABEL: imm8:254; CHECK: # %bb.0: # %entry255; CHECK-NEXT: li 3, -7919256; CHECK-NEXT: rldic 3, 3, 22, 22257; CHECK-NEXT: blr258entry:259 ret i64 4364831817728 ;0x3f844400000260}261 262define i64 @imm9() #0 {263; CHECK-LABEL: imm9:264; CHECK: # %bb.0: # %entry265; CHECK-NEXT: lis 3, -1266; CHECK-NEXT: ori 3, 3, 28674267; CHECK-NEXT: rotldi 3, 3, 52268; CHECK-NEXT: blr269entry:270 ret i64 13510798882111479 ;0x2ffffffffffff7271}272 273define i64 @imm10() #0 {274; CHECK-LABEL: imm10:275; CHECK: # %bb.0: # %entry276; CHECK-NEXT: li 3, -3823277; CHECK-NEXT: rldic 3, 3, 28, 20278; CHECK-NEXT: blr279entry:280 ret i64 16565957296128 ;0xf1110000000281}282 283define i64 @imm11() #0 {284; CHECK-LABEL: imm11:285; CHECK: # %bb.0: # %entry286; CHECK-NEXT: li 3, -7919287; CHECK-NEXT: rldic 3, 3, 22, 22288; CHECK-NEXT: blr289entry:290 ret i64 4364831817728 ;0x3f844400000291}292 293define i64 @imm12() #0 {294; CHECK-LABEL: imm12:295; CHECK: # %bb.0: # %entry296; CHECK-NEXT: lis 3, -29297; CHECK-NEXT: ori 3, 3, 64577298; CHECK-NEXT: rldic 3, 3, 12, 20299; CHECK-NEXT: blr300entry:301 ret i64 17584665923584 ;0xffe3fc41000302}303 304define i64 @imm13() #0 {305; CHECK-LABEL: imm13:306; CHECK: # %bb.0: # %entry307; CHECK-NEXT: li 3, -24847308; CHECK-NEXT: rldicl 3, 3, 21, 27309; CHECK-NEXT: blr310entry:311 ret i64 85333114879 ;0x13de3fffff312}313 314define i64 @imm13_2() #0 {315; CHECK-LABEL: imm13_2:316; CHECK: # %bb.0: # %entry317; CHECK-NEXT: li 3, -12424318; CHECK-NEXT: rldicl 3, 3, 22, 26319; CHECK-NEXT: blr320entry:321 ret i64 222772068351 ;0x33de3fffff322}323 324define i64 @imm14() #0 {325; CHECK-LABEL: imm14:326; CHECK: # %bb.0: # %entry327; CHECK-NEXT: li 3, -3960328; CHECK-NEXT: rldicl 3, 3, 21, 24329; CHECK-NEXT: blr330entry:331 ret i64 1091209003007 ;0xfe111fffff332}333 334define i64 @imm15() #0 {335; CHECK-LABEL: imm15:336; CHECK: # %bb.0: # %entry337; CHECK-NEXT: li 3, -8065338; CHECK-NEXT: rldic 3, 3, 24, 0339; CHECK-NEXT: blr340entry:341 ret i64 -135308247040342}343 344define i64 @imm16() #0 {345; CHECK-LABEL: imm16:346; CHECK: # %bb.0: # %entry347; CHECK-NEXT: lis 3, -16392348; CHECK-NEXT: ori 3, 3, 57217349; CHECK-NEXT: rldic 3, 3, 16, 0350; CHECK-NEXT: blr351entry:352 ret i64 -70399354142720353}354 355define i64 @imm17() #0 {356; CHECK-LABEL: imm17:357; CHECK: # %bb.0: # %entry358; CHECK-NEXT: lis 3, 20344359; CHECK-NEXT: ori 3, 3, 32847360; CHECK-NEXT: rotldi 3, 3, 49361; CHECK-NEXT: blr362entry:363 ret i64 44473046320324337 ;0x9e000000009ef1364}365 366define i64 @imm18() #0 {367; CHECK-LABEL: imm18:368; CHECK: # %bb.0: # %entry369; CHECK-NEXT: li 3, 1370; CHECK-NEXT: rldic 3, 3, 33, 30371; CHECK-NEXT: oris 3, 3, 39436372; CHECK-NEXT: ori 3, 3, 61633373; CHECK-NEXT: blr374entry:375 ret i64 11174473921376}377 378define i64 @imm19() {379; CHECK-LABEL: imm19:380; CHECK: # %bb.0: # %entry381; CHECK-NEXT: lis 3, -13105382; CHECK-NEXT: ori 3, 3, 52479383; CHECK-NEXT: rldic 3, 3, 32, 0384; CHECK-NEXT: oris 3, 3, 52431385; CHECK-NEXT: ori 3, 3, 291386; CHECK-NEXT: blr387entry:388 ret i64 14758239902941249827 ;0xCCCFCCFFCCCF0123389}390 391define i64 @imm20() {392; CHECK-LABEL: imm20:393; CHECK: # %bb.0: # %entry394; CHECK-NEXT: lis 3, 291395; CHECK-NEXT: ori 3, 3, 52479396; CHECK-NEXT: rldimi 3, 3, 32, 0397; CHECK-NEXT: rldimi 3, 3, 48, 0398; CHECK-NEXT: blr399entry:400 ret i64 14771750698406366463 ;0xCCFFCCFF0123CCFF401}402 403define i64 @imm21() {404; CHECK-LABEL: imm21:405; CHECK: # %bb.0: # %entry406; CHECK-NEXT: lis 3, -13057407; CHECK-NEXT: ori 3, 3, 291408; CHECK-NEXT: rldimi 3, 3, 32, 0409; CHECK-NEXT: rlwimi 3, 3, 16, 16, 31410; CHECK-NEXT: blr411entry:412 ret i64 14771526556073315583 ;0xCCFF0123CCFFCCFF413}414 415define i64 @imm22() {416; CHECK-LABEL: imm22:417; CHECK: # %bb.0: # %entry418; CHECK-NEXT: lis 3, 291419; CHECK-NEXT: ori 3, 3, 52479420; CHECK-NEXT: rldimi 3, 3, 32, 0421; CHECK-NEXT: rlwimi 3, 3, 16, 0, 15422; CHECK-NEXT: blr423entry:424 ret i64 82134617250843903 ;0x0123CCFFCCFFCCFF425}426 427define i64 @imm23() {428; CHECK-LABEL: imm23:429; CHECK: # %bb.0: # %entry430; CHECK-NEXT: li 3, 32767431; CHECK-NEXT: rldimi 3, 3, 32, 0432; CHECK-NEXT: blr433entry:434 ret i64 140733193420799 ;0x00007FFF00007FFF435}436 437define i64 @imm24() {438; CHECK-LABEL: imm24:439; CHECK: # %bb.0: # %entry440; CHECK-NEXT: lis 3, -9441; CHECK-NEXT: rldimi 3, 3, 32, 0442; CHECK-NEXT: blr443entry:444 ret i64 18444210803213533184 ;0xFFF70000FFF70000445}446 447attributes #0 = { nounwind readnone }448