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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mcpu=ppc64 -mtriple=powerpc64-unknown-linux-gnu \3; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \4; RUN: < %s | FileCheck %s5 6define void @_blah() {7; CHECK-LABEL: _blah:8; CHECK: # %bb.0: # %entry9; CHECK-NEXT: li r3, 010; CHECK-NEXT: li r4, 1511; CHECK-NEXT: lvx v3, 0, r412; CHECK-NEXT: addi r5, r1, -6413; CHECK-NEXT: lvx v4, 0, r314; CHECK-NEXT: lvsl v2, 0, r315; CHECK-NEXT: vperm v2, v4, v3, v216; CHECK-NEXT: lwz r4, 16(0)17; CHECK-NEXT: stvx v2, 0, r518; CHECK-NEXT: lhz r5, -64(r1)19; CHECK-NEXT: lhz r6, -58(r1)20; CHECK-NEXT: lhz r7, -52(r1)21; CHECK-NEXT: sth r4, -34(r1)22; CHECK-NEXT: sth r3, -36(r1)23; CHECK-NEXT: sth r3, -40(r1)24; CHECK-NEXT: sth r3, -44(r1)25; CHECK-NEXT: sth r3, -48(r1)26; CHECK-NEXT: addi r3, r1, -4827; CHECK-NEXT: sth r7, -38(r1)28; CHECK-NEXT: sth r6, -42(r1)29; CHECK-NEXT: sth r5, -46(r1)30; CHECK-NEXT: lvx v2, 0, r331; CHECK-NEXT: addi r3, r1, -3232; CHECK-NEXT: vsldoi v3, v2, v2, 833; CHECK-NEXT: vmaxuw v2, v2, v334; CHECK-NEXT: vspltw v3, v2, 135; CHECK-NEXT: vmaxuw v2, v2, v336; CHECK-NEXT: stvx v2, 0, r337; CHECK-NEXT: lwz r3, -32(r1)38; CHECK-NEXT: cmplwi r3, 039; CHECK-NEXT: blr40entry:41 %wide.vec904 = load <12 x i16>, ptr null, align 242 %strided.vec905 = shufflevector <12 x i16> %wide.vec904, <12 x i16> zeroinitializer, <4 x i32> <i32 0, i32 3, i32 6, i32 9>43 %0 = zext <4 x i16> %strided.vec905 to <4 x i32>44 %1 = tail call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %0)45 %cmp55.not823 = icmp ugt i32 1, %146 br i1 %cmp55.not823, label %for.cond.cleanup56, label %for.body57.lr.ph47 48for.body57.lr.ph: ; preds = %entry49 ret void50 51for.cond.cleanup56: ; preds = %entry52 ret void53}54 55declare i32 @llvm.vector.reduce.umax.v4i32(<4 x i32>)56