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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: -mcpu=future -enable-subreg-liveness -ppc-asm-full-reg-names \4; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \6; RUN: -mcpu=future -enable-subreg-liveness -ppc-asm-full-reg-names \7; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE8 9declare <1024 x i1> @llvm.ppc.mma.dmxvi8gerx4(<256 x i1>, <16 x i8>)10 11define void @test_dmxvi8gerx4(ptr %vpp, ptr %vcp, ptr %resp) {12; CHECK-LABEL: test_dmxvi8gerx4:13; CHECK: # %bb.0: # %entry14; CHECK-NEXT: lxv v2, 16(r3)15; CHECK-NEXT: lxv vs0, 0(r4)16; CHECK-NEXT: lxv v3, 0(r3)17; CHECK-NEXT: dmxvi8gerx4 dmr0, vsp34, vs018; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 019; CHECK-NEXT: stxvp vsp34, 96(r5)20; CHECK-NEXT: stxvp vsp36, 64(r5)21; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 122; CHECK-NEXT: stxvp vsp34, 32(r5)23; CHECK-NEXT: stxvp vsp36, 0(r5)24; CHECK-NEXT: blr25;26; CHECK-BE-LABEL: test_dmxvi8gerx4:27; CHECK-BE: # %bb.0: # %entry28; CHECK-BE-NEXT: lxv v2, 0(r3)29; CHECK-BE-NEXT: lxv vs0, 0(r4)30; CHECK-BE-NEXT: lxv v3, 16(r3)31; CHECK-BE-NEXT: dmxvi8gerx4 dmr0, vsp34, vs032; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 133; CHECK-BE-NEXT: stxvp vsp36, 96(r5)34; CHECK-BE-NEXT: stxvp vsp34, 64(r5)35; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 036; CHECK-BE-NEXT: stxvp vsp36, 32(r5)37; CHECK-BE-NEXT: stxvp vsp34, 0(r5)38; CHECK-BE-NEXT: blr39entry:40 %v1 = load <256 x i1>, ptr %vpp, align 3241 %v2 = load <16 x i8>, ptr %vcp, align 3242 %call = tail call <1024 x i1> @llvm.ppc.mma.dmxvi8gerx4(<256 x i1> %v1, <16 x i8> %v2)43 store <1024 x i1> %call, ptr %resp, align 6444 ret void45}46 47declare <1024 x i1> @llvm.ppc.mma.dmxvi8gerx4pp(<1024 x i1>, <256 x i1>, <16 x i8>)48 49define void @test_dmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {50; CHECK-LABEL: test_dmxvi8gerx4pp:51; CHECK: # %bb.0: # %entry52; CHECK-NEXT: lxvp vsp34, 0(r3)53; CHECK-NEXT: lxvp vsp36, 32(r3)54; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 155; CHECK-NEXT: lxvp vsp34, 64(r3)56; CHECK-NEXT: lxvp vsp36, 96(r3)57; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 058; CHECK-NEXT: lxv v2, 16(r4)59; CHECK-NEXT: lxv vs0, 0(r5)60; CHECK-NEXT: lxv v3, 0(r4)61; CHECK-NEXT: dmxvi8gerx4pp dmr0, vsp34, vs062; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 063; CHECK-NEXT: stxvp vsp34, 96(r6)64; CHECK-NEXT: stxvp vsp36, 64(r6)65; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 166; CHECK-NEXT: stxvp vsp34, 32(r6)67; CHECK-NEXT: stxvp vsp36, 0(r6)68; CHECK-NEXT: blr69;70; CHECK-BE-LABEL: test_dmxvi8gerx4pp:71; CHECK-BE: # %bb.0: # %entry72; CHECK-BE-NEXT: lxvp vsp34, 96(r3)73; CHECK-BE-NEXT: lxvp vsp36, 64(r3)74; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 175; CHECK-BE-NEXT: lxvp vsp34, 32(r3)76; CHECK-BE-NEXT: lxvp vsp36, 0(r3)77; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 078; CHECK-BE-NEXT: lxv v2, 0(r4)79; CHECK-BE-NEXT: lxv vs0, 0(r5)80; CHECK-BE-NEXT: lxv v3, 16(r4)81; CHECK-BE-NEXT: dmxvi8gerx4pp dmr0, vsp34, vs082; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 183; CHECK-BE-NEXT: stxvp vsp36, 96(r6)84; CHECK-BE-NEXT: stxvp vsp34, 64(r6)85; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 086; CHECK-BE-NEXT: stxvp vsp36, 32(r6)87; CHECK-BE-NEXT: stxvp vsp34, 0(r6)88; CHECK-BE-NEXT: blr89entry:90 %v.dmr = load <1024 x i1>, ptr %vop, align 6491 %v1 = load <256 x i1>, ptr %vpp, align 3292 %v2 = load <16 x i8>, ptr %vcp, align 3293 %call = tail call <1024 x i1> @llvm.ppc.mma.dmxvi8gerx4pp(<1024 x i1> %v.dmr, <256 x i1> %v1, <16 x i8> %v2)94 store <1024 x i1> %call, ptr %resp, align 6495 ret void96}97 98declare <1024 x i1> @llvm.ppc.mma.dmxvi8gerx4spp(<1024 x i1>, <256 x i1>, <16 x i8>)99 100define void @test_dmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {101; CHECK-LABEL: test_dmxvi8gerx4spp:102; CHECK: # %bb.0: # %entry103; CHECK-NEXT: lxvp vsp34, 0(r3)104; CHECK-NEXT: lxvp vsp36, 32(r3)105; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1106; CHECK-NEXT: lxvp vsp34, 64(r3)107; CHECK-NEXT: lxvp vsp36, 96(r3)108; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0109; CHECK-NEXT: lxv v2, 16(r4)110; CHECK-NEXT: lxv vs0, 0(r5)111; CHECK-NEXT: lxv v3, 0(r4)112; CHECK-NEXT: dmxvi8gerx4spp dmr0, vsp34, vs0113; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0114; CHECK-NEXT: stxvp vsp34, 96(r6)115; CHECK-NEXT: stxvp vsp36, 64(r6)116; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1117; CHECK-NEXT: stxvp vsp34, 32(r6)118; CHECK-NEXT: stxvp vsp36, 0(r6)119; CHECK-NEXT: blr120;121; CHECK-BE-LABEL: test_dmxvi8gerx4spp:122; CHECK-BE: # %bb.0: # %entry123; CHECK-BE-NEXT: lxvp vsp34, 96(r3)124; CHECK-BE-NEXT: lxvp vsp36, 64(r3)125; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1126; CHECK-BE-NEXT: lxvp vsp34, 32(r3)127; CHECK-BE-NEXT: lxvp vsp36, 0(r3)128; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0129; CHECK-BE-NEXT: lxv v2, 0(r4)130; CHECK-BE-NEXT: lxv vs0, 0(r5)131; CHECK-BE-NEXT: lxv v3, 16(r4)132; CHECK-BE-NEXT: dmxvi8gerx4spp dmr0, vsp34, vs0133; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1134; CHECK-BE-NEXT: stxvp vsp36, 96(r6)135; CHECK-BE-NEXT: stxvp vsp34, 64(r6)136; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0137; CHECK-BE-NEXT: stxvp vsp36, 32(r6)138; CHECK-BE-NEXT: stxvp vsp34, 0(r6)139; CHECK-BE-NEXT: blr140entry:141 %v.dmr = load <1024 x i1>, ptr %vop, align 64142 %v1 = load <256 x i1>, ptr %vpp, align 32143 %v2 = load <16 x i8>, ptr %vcp, align 32144 %call = tail call <1024 x i1> @llvm.ppc.mma.dmxvi8gerx4spp(<1024 x i1> %v.dmr, <256 x i1> %v1, <16 x i8> %v2)145 store <1024 x i1> %call, ptr %resp, align 64146 ret void147}148 149declare <1024 x i1> @llvm.ppc.mma.pmdmxvi8gerx4pp(<1024 x i1>, <256 x i1>, <16 x i8>, i32, i32, i32)150 151define void @test_pmdmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {152; CHECK-LABEL: test_pmdmxvi8gerx4pp:153; CHECK: # %bb.0: # %entry154; CHECK-NEXT: lxvp vsp34, 0(r3)155; CHECK-NEXT: lxvp vsp36, 32(r3)156; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1157; CHECK-NEXT: lxvp vsp34, 64(r3)158; CHECK-NEXT: lxvp vsp36, 96(r3)159; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0160; CHECK-NEXT: lxv v2, 16(r4)161; CHECK-NEXT: lxv vs0, 0(r5)162; CHECK-NEXT: lxv v3, 0(r4)163; CHECK-NEXT: pmdmxvi8gerx4pp dmr0, vsp34, vs0, 42, 7, 9164; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0165; CHECK-NEXT: stxvp vsp34, 96(r6)166; CHECK-NEXT: stxvp vsp36, 64(r6)167; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1168; CHECK-NEXT: stxvp vsp34, 32(r6)169; CHECK-NEXT: stxvp vsp36, 0(r6)170; CHECK-NEXT: blr171;172; CHECK-BE-LABEL: test_pmdmxvi8gerx4pp:173; CHECK-BE: # %bb.0: # %entry174; CHECK-BE-NEXT: lxvp vsp34, 96(r3)175; CHECK-BE-NEXT: lxvp vsp36, 64(r3)176; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1177; CHECK-BE-NEXT: lxvp vsp34, 32(r3)178; CHECK-BE-NEXT: lxvp vsp36, 0(r3)179; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0180; CHECK-BE-NEXT: lxv v2, 0(r4)181; CHECK-BE-NEXT: lxv vs0, 0(r5)182; CHECK-BE-NEXT: lxv v3, 16(r4)183; CHECK-BE-NEXT: pmdmxvi8gerx4pp dmr0, vsp34, vs0, 42, 7, 9184; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1185; CHECK-BE-NEXT: stxvp vsp36, 96(r6)186; CHECK-BE-NEXT: stxvp vsp34, 64(r6)187; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0188; CHECK-BE-NEXT: stxvp vsp36, 32(r6)189; CHECK-BE-NEXT: stxvp vsp34, 0(r6)190; CHECK-BE-NEXT: blr191entry:192 %v.dmr = load <1024 x i1>, ptr %vop, align 64193 %v1 = load <256 x i1>, ptr %vpp, align 32194 %v2 = load <16 x i8>, ptr %vcp, align 32195 %call = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvi8gerx4pp(<1024 x i1> %v.dmr, <256 x i1> %v1, <16 x i8> %v2, i32 42, i32 7, i32 9)196 store <1024 x i1> %call, ptr %resp, align 64197 ret void198}199 200declare <1024 x i1> @llvm.ppc.mma.pmdmxvi8gerx4(<256 x i1>, <16 x i8>, i32, i32, i32)201 202define void @test_pmdmxvi8gerx4(ptr %vpp, ptr %vcp, ptr %resp) {203; CHECK-LABEL: test_pmdmxvi8gerx4:204; CHECK: # %bb.0: # %entry205; CHECK-NEXT: lxv v2, 16(r3)206; CHECK-NEXT: lxv vs0, 0(r4)207; CHECK-NEXT: lxv v3, 0(r3)208; CHECK-NEXT: pmdmxvi8gerx4 dmr0, vsp34, vs0, 55, 5, 10209; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0210; CHECK-NEXT: stxvp vsp34, 96(r5)211; CHECK-NEXT: stxvp vsp36, 64(r5)212; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1213; CHECK-NEXT: stxvp vsp34, 32(r5)214; CHECK-NEXT: stxvp vsp36, 0(r5)215; CHECK-NEXT: blr216;217; CHECK-BE-LABEL: test_pmdmxvi8gerx4:218; CHECK-BE: # %bb.0: # %entry219; CHECK-BE-NEXT: lxv v2, 0(r3)220; CHECK-BE-NEXT: lxv vs0, 0(r4)221; CHECK-BE-NEXT: lxv v3, 16(r3)222; CHECK-BE-NEXT: pmdmxvi8gerx4 dmr0, vsp34, vs0, 55, 5, 10223; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1224; CHECK-BE-NEXT: stxvp vsp36, 96(r5)225; CHECK-BE-NEXT: stxvp vsp34, 64(r5)226; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0227; CHECK-BE-NEXT: stxvp vsp36, 32(r5)228; CHECK-BE-NEXT: stxvp vsp34, 0(r5)229; CHECK-BE-NEXT: blr230entry:231 %v1 = load <256 x i1>, ptr %vpp, align 32232 %v2 = load <16 x i8>, ptr %vcp, align 32233 %call = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvi8gerx4(<256 x i1> %v1, <16 x i8> %v2, i32 55, i32 5, i32 10)234 store <1024 x i1> %call, ptr %resp, align 64235 ret void236}237 238declare <1024 x i1> @llvm.ppc.mma.pmdmxvi8gerx4spp(<1024 x i1>, <256 x i1>, <16 x i8>, i32, i32, i32)239 240define dso_local void @test_pmdmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {241; CHECK-LABEL: test_pmdmxvi8gerx4spp:242; CHECK: # %bb.0: # %entry243; CHECK-NEXT: lxvp vsp34, 0(r3)244; CHECK-NEXT: lxvp vsp36, 32(r3)245; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1246; CHECK-NEXT: lxvp vsp34, 64(r3)247; CHECK-NEXT: lxvp vsp36, 96(r3)248; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0249; CHECK-NEXT: lxv v2, 16(r4)250; CHECK-NEXT: lxv vs0, 0(r5)251; CHECK-NEXT: lxv v3, 0(r4)252; CHECK-NEXT: pmdmxvi8gerx4spp dmr0, vsp34, vs0, 100, 6, 12253; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0254; CHECK-NEXT: stxvp vsp34, 96(r6)255; CHECK-NEXT: stxvp vsp36, 64(r6)256; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1257; CHECK-NEXT: stxvp vsp34, 32(r6)258; CHECK-NEXT: stxvp vsp36, 0(r6)259; CHECK-NEXT: blr260;261; CHECK-BE-LABEL: test_pmdmxvi8gerx4spp:262; CHECK-BE: # %bb.0: # %entry263; CHECK-BE-NEXT: lxvp vsp34, 96(r3)264; CHECK-BE-NEXT: lxvp vsp36, 64(r3)265; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1266; CHECK-BE-NEXT: lxvp vsp34, 32(r3)267; CHECK-BE-NEXT: lxvp vsp36, 0(r3)268; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0269; CHECK-BE-NEXT: lxv v2, 0(r4)270; CHECK-BE-NEXT: lxv vs0, 0(r5)271; CHECK-BE-NEXT: lxv v3, 16(r4)272; CHECK-BE-NEXT: pmdmxvi8gerx4spp dmr0, vsp34, vs0, 100, 6, 12273; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1274; CHECK-BE-NEXT: stxvp vsp36, 96(r6)275; CHECK-BE-NEXT: stxvp vsp34, 64(r6)276; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0277; CHECK-BE-NEXT: stxvp vsp36, 32(r6)278; CHECK-BE-NEXT: stxvp vsp34, 0(r6)279; CHECK-BE-NEXT: blr280entry:281 %v.dmr = load <1024 x i1>, ptr %vop, align 64282 %v1 = load <256 x i1>, ptr %vpp, align 32283 %v2 = load <16 x i8>, ptr %vcp, align 32284 %call = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvi8gerx4spp(<1024 x i1> %v.dmr, <256 x i1> %v1, <16 x i8> %v2, i32 100, i32 6, i32 12)285 store <1024 x i1> %call, ptr %resp, align 64286 ret void287}288 289declare <1024 x i1> @llvm.ppc.mma.dmxvbf16gerx2(<256 x i1>, <16 x i8>)290 291define void @test_dmxvbf16gerx2(ptr %vpp, ptr %vcp, ptr %resp) {292; CHECK-LABEL: test_dmxvbf16gerx2:293; CHECK: # %bb.0: # %entry294; CHECK-NEXT: lxv v2, 16(r3)295; CHECK-NEXT: lxv vs0, 0(r4)296; CHECK-NEXT: lxv v3, 0(r3)297; CHECK-NEXT: dmxvbf16gerx2 dmr0, vsp34, vs0298; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0299; CHECK-NEXT: stxvp vsp34, 96(r5)300; CHECK-NEXT: stxvp vsp36, 64(r5)301; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1302; CHECK-NEXT: stxvp vsp34, 32(r5)303; CHECK-NEXT: stxvp vsp36, 0(r5)304; CHECK-NEXT: blr305;306; CHECK-BE-LABEL: test_dmxvbf16gerx2:307; CHECK-BE: # %bb.0: # %entry308; CHECK-BE-NEXT: lxv v2, 0(r3)309; CHECK-BE-NEXT: lxv vs0, 0(r4)310; CHECK-BE-NEXT: lxv v3, 16(r3)311; CHECK-BE-NEXT: dmxvbf16gerx2 dmr0, vsp34, vs0312; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1313; CHECK-BE-NEXT: stxvp vsp36, 96(r5)314; CHECK-BE-NEXT: stxvp vsp34, 64(r5)315; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0316; CHECK-BE-NEXT: stxvp vsp36, 32(r5)317; CHECK-BE-NEXT: stxvp vsp34, 0(r5)318; CHECK-BE-NEXT: blr319entry:320 %v1 = load <256 x i1>, ptr %vpp, align 32321 %v2 = load <16 x i8>, ptr %vcp, align 32322 %call = tail call <1024 x i1> @llvm.ppc.mma.dmxvbf16gerx2(<256 x i1> %v1, <16 x i8> %v2)323 store <1024 x i1> %call, ptr %resp, align 64324 ret void325}326 327declare <1024 x i1> @llvm.ppc.mma.dmxvbf16gerx2pp(<1024 x i1>, <256 x i1>, <16 x i8>)328 329define void @test_dmxvbf16gerx2pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {330; CHECK-LABEL: test_dmxvbf16gerx2pp:331; CHECK: # %bb.0: # %entry332; CHECK-NEXT: lxvp vsp34, 0(r3)333; CHECK-NEXT: lxvp vsp36, 32(r3)334; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1335; CHECK-NEXT: lxvp vsp34, 64(r3)336; CHECK-NEXT: lxvp vsp36, 96(r3)337; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0338; CHECK-NEXT: lxv v2, 16(r4)339; CHECK-NEXT: lxv vs0, 0(r5)340; CHECK-NEXT: lxv v3, 0(r4)341; CHECK-NEXT: dmxvbf16gerx2pp dmr0, vsp34, vs0342; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0343; CHECK-NEXT: stxvp vsp34, 96(r6)344; CHECK-NEXT: stxvp vsp36, 64(r6)345; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1346; CHECK-NEXT: stxvp vsp34, 32(r6)347; CHECK-NEXT: stxvp vsp36, 0(r6)348; CHECK-NEXT: blr349;350; CHECK-BE-LABEL: test_dmxvbf16gerx2pp:351; CHECK-BE: # %bb.0: # %entry352; CHECK-BE-NEXT: lxvp vsp34, 96(r3)353; CHECK-BE-NEXT: lxvp vsp36, 64(r3)354; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1355; CHECK-BE-NEXT: lxvp vsp34, 32(r3)356; CHECK-BE-NEXT: lxvp vsp36, 0(r3)357; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0358; CHECK-BE-NEXT: lxv v2, 0(r4)359; CHECK-BE-NEXT: lxv vs0, 0(r5)360; CHECK-BE-NEXT: lxv v3, 16(r4)361; CHECK-BE-NEXT: dmxvbf16gerx2pp dmr0, vsp34, vs0362; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1363; CHECK-BE-NEXT: stxvp vsp36, 96(r6)364; CHECK-BE-NEXT: stxvp vsp34, 64(r6)365; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0366; CHECK-BE-NEXT: stxvp vsp36, 32(r6)367; CHECK-BE-NEXT: stxvp vsp34, 0(r6)368; CHECK-BE-NEXT: blr369entry:370 %v.dmr = load <1024 x i1>, ptr %vop, align 64371 %v1 = load <256 x i1>, ptr %vpp, align 32372 %v2 = load <16 x i8>, ptr %vcp, align 32373 %call = tail call <1024 x i1> @llvm.ppc.mma.dmxvbf16gerx2pp(<1024 x i1> %v.dmr, <256 x i1> %v1, <16 x i8> %v2)374 store <1024 x i1> %call, ptr %resp, align 64375 ret void376}377 378declare <1024 x i1> @llvm.ppc.mma.dmxvbf16gerx2pn(<1024 x i1>, <256 x i1>, <16 x i8>)379 380define void @test_dmxvbf16gerx2pn(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {381; CHECK-LABEL: test_dmxvbf16gerx2pn:382; CHECK: # %bb.0: # %entry383; CHECK-NEXT: lxvp vsp34, 0(r3)384; CHECK-NEXT: lxvp vsp36, 32(r3)385; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1386; CHECK-NEXT: lxvp vsp34, 64(r3)387; CHECK-NEXT: lxvp vsp36, 96(r3)388; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0389; CHECK-NEXT: lxv v2, 16(r4)390; CHECK-NEXT: lxv vs0, 0(r5)391; CHECK-NEXT: lxv v3, 0(r4)392; CHECK-NEXT: dmxvbf16gerx2pn dmr0, vsp34, vs0393; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0394; CHECK-NEXT: stxvp vsp34, 96(r6)395; CHECK-NEXT: stxvp vsp36, 64(r6)396; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1397; CHECK-NEXT: stxvp vsp34, 32(r6)398; CHECK-NEXT: stxvp vsp36, 0(r6)399; CHECK-NEXT: blr400;401; CHECK-BE-LABEL: test_dmxvbf16gerx2pn:402; CHECK-BE: # %bb.0: # %entry403; CHECK-BE-NEXT: lxvp vsp34, 96(r3)404; CHECK-BE-NEXT: lxvp vsp36, 64(r3)405; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1406; CHECK-BE-NEXT: lxvp vsp34, 32(r3)407; CHECK-BE-NEXT: lxvp vsp36, 0(r3)408; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0409; CHECK-BE-NEXT: lxv v2, 0(r4)410; CHECK-BE-NEXT: lxv vs0, 0(r5)411; CHECK-BE-NEXT: lxv v3, 16(r4)412; CHECK-BE-NEXT: dmxvbf16gerx2pn dmr0, vsp34, vs0413; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1414; CHECK-BE-NEXT: stxvp vsp36, 96(r6)415; CHECK-BE-NEXT: stxvp vsp34, 64(r6)416; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0417; CHECK-BE-NEXT: stxvp vsp36, 32(r6)418; CHECK-BE-NEXT: stxvp vsp34, 0(r6)419; CHECK-BE-NEXT: blr420entry:421 %v.dmr = load <1024 x i1>, ptr %vop, align 64422 %v1 = load <256 x i1>, ptr %vpp, align 32423 %v2 = load <16 x i8>, ptr %vcp, align 32424 %call = tail call <1024 x i1> @llvm.ppc.mma.dmxvbf16gerx2pn(<1024 x i1> %v.dmr, <256 x i1> %v1, <16 x i8> %v2)425 store <1024 x i1> %call, ptr %resp, align 64426 ret void427}428 429declare <1024 x i1> @llvm.ppc.mma.dmxvbf16gerx2np(<1024 x i1>, <256 x i1>, <16 x i8>)430 431define void @test_dmxvbf16gerx2np(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {432; CHECK-LABEL: test_dmxvbf16gerx2np:433; CHECK: # %bb.0: # %entry434; CHECK-NEXT: lxvp vsp34, 0(r3)435; CHECK-NEXT: lxvp vsp36, 32(r3)436; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1437; CHECK-NEXT: lxvp vsp34, 64(r3)438; CHECK-NEXT: lxvp vsp36, 96(r3)439; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0440; CHECK-NEXT: lxv v2, 16(r4)441; CHECK-NEXT: lxv vs0, 0(r5)442; CHECK-NEXT: lxv v3, 0(r4)443; CHECK-NEXT: dmxvbf16gerx2np dmr0, vsp34, vs0444; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0445; CHECK-NEXT: stxvp vsp34, 96(r6)446; CHECK-NEXT: stxvp vsp36, 64(r6)447; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1448; CHECK-NEXT: stxvp vsp34, 32(r6)449; CHECK-NEXT: stxvp vsp36, 0(r6)450; CHECK-NEXT: blr451;452; CHECK-BE-LABEL: test_dmxvbf16gerx2np:453; CHECK-BE: # %bb.0: # %entry454; CHECK-BE-NEXT: lxvp vsp34, 96(r3)455; CHECK-BE-NEXT: lxvp vsp36, 64(r3)456; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1457; CHECK-BE-NEXT: lxvp vsp34, 32(r3)458; CHECK-BE-NEXT: lxvp vsp36, 0(r3)459; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0460; CHECK-BE-NEXT: lxv v2, 0(r4)461; CHECK-BE-NEXT: lxv vs0, 0(r5)462; CHECK-BE-NEXT: lxv v3, 16(r4)463; CHECK-BE-NEXT: dmxvbf16gerx2np dmr0, vsp34, vs0464; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1465; CHECK-BE-NEXT: stxvp vsp36, 96(r6)466; CHECK-BE-NEXT: stxvp vsp34, 64(r6)467; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0468; CHECK-BE-NEXT: stxvp vsp36, 32(r6)469; CHECK-BE-NEXT: stxvp vsp34, 0(r6)470; CHECK-BE-NEXT: blr471entry:472 %v.dmr = load <1024 x i1>, ptr %vop, align 64473 %v1 = load <256 x i1>, ptr %vpp, align 32474 %v2 = load <16 x i8>, ptr %vcp, align 32475 %call = tail call <1024 x i1> @llvm.ppc.mma.dmxvbf16gerx2np(<1024 x i1> %v.dmr, <256 x i1> %v1, <16 x i8> %v2)476 store <1024 x i1> %call, ptr %resp, align 64477 ret void478}479 480declare <1024 x i1> @llvm.ppc.mma.dmxvbf16gerx2nn(<1024 x i1>, <256 x i1>, <16 x i8>)481 482define void @test_dmxvbf16gerx2nn(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {483; CHECK-LABEL: test_dmxvbf16gerx2nn:484; CHECK: # %bb.0: # %entry485; CHECK-NEXT: lxvp vsp34, 0(r3)486; CHECK-NEXT: lxvp vsp36, 32(r3)487; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1488; CHECK-NEXT: lxvp vsp34, 64(r3)489; CHECK-NEXT: lxvp vsp36, 96(r3)490; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0491; CHECK-NEXT: lxv v2, 16(r4)492; CHECK-NEXT: lxv vs0, 0(r5)493; CHECK-NEXT: lxv v3, 0(r4)494; CHECK-NEXT: dmxvbf16gerx2nn dmr0, vsp34, vs0495; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0496; CHECK-NEXT: stxvp vsp34, 96(r6)497; CHECK-NEXT: stxvp vsp36, 64(r6)498; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1499; CHECK-NEXT: stxvp vsp34, 32(r6)500; CHECK-NEXT: stxvp vsp36, 0(r6)501; CHECK-NEXT: blr502;503; CHECK-BE-LABEL: test_dmxvbf16gerx2nn:504; CHECK-BE: # %bb.0: # %entry505; CHECK-BE-NEXT: lxvp vsp34, 96(r3)506; CHECK-BE-NEXT: lxvp vsp36, 64(r3)507; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1508; CHECK-BE-NEXT: lxvp vsp34, 32(r3)509; CHECK-BE-NEXT: lxvp vsp36, 0(r3)510; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0511; CHECK-BE-NEXT: lxv v2, 0(r4)512; CHECK-BE-NEXT: lxv vs0, 0(r5)513; CHECK-BE-NEXT: lxv v3, 16(r4)514; CHECK-BE-NEXT: dmxvbf16gerx2nn dmr0, vsp34, vs0515; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1516; CHECK-BE-NEXT: stxvp vsp36, 96(r6)517; CHECK-BE-NEXT: stxvp vsp34, 64(r6)518; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0519; CHECK-BE-NEXT: stxvp vsp36, 32(r6)520; CHECK-BE-NEXT: stxvp vsp34, 0(r6)521; CHECK-BE-NEXT: blr522entry:523 %v.dmr = load <1024 x i1>, ptr %vop, align 64524 %v1 = load <256 x i1>, ptr %vpp, align 32525 %v2 = load <16 x i8>, ptr %vcp, align 32526 %call = tail call <1024 x i1> @llvm.ppc.mma.dmxvbf16gerx2nn(<1024 x i1> %v.dmr, <256 x i1> %v1, <16 x i8> %v2)527 store <1024 x i1> %call, ptr %resp, align 64528 ret void529}530 531declare <1024 x i1> @llvm.ppc.mma.pmdmxvbf16gerx2(<256 x i1>, <16 x i8>, i32, i32, i32)532 533define void @test_pmdmxvbf16gerx2(ptr %vpp, ptr %vcp, ptr %resp) {534; CHECK-LABEL: test_pmdmxvbf16gerx2:535; CHECK: # %bb.0: # %entry536; CHECK-NEXT: lxv v2, 16(r3)537; CHECK-NEXT: lxv vs0, 0(r4)538; CHECK-NEXT: lxv v3, 0(r3)539; CHECK-NEXT: pmdmxvbf16gerx2 dmr0, vsp34, vs0, 33, 5, 2540; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0541; CHECK-NEXT: stxvp vsp34, 96(r5)542; CHECK-NEXT: stxvp vsp36, 64(r5)543; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1544; CHECK-NEXT: stxvp vsp34, 32(r5)545; CHECK-NEXT: stxvp vsp36, 0(r5)546; CHECK-NEXT: blr547;548; CHECK-BE-LABEL: test_pmdmxvbf16gerx2:549; CHECK-BE: # %bb.0: # %entry550; CHECK-BE-NEXT: lxv v2, 0(r3)551; CHECK-BE-NEXT: lxv vs0, 0(r4)552; CHECK-BE-NEXT: lxv v3, 16(r3)553; CHECK-BE-NEXT: pmdmxvbf16gerx2 dmr0, vsp34, vs0, 33, 5, 2554; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1555; CHECK-BE-NEXT: stxvp vsp36, 96(r5)556; CHECK-BE-NEXT: stxvp vsp34, 64(r5)557; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0558; CHECK-BE-NEXT: stxvp vsp36, 32(r5)559; CHECK-BE-NEXT: stxvp vsp34, 0(r5)560; CHECK-BE-NEXT: blr561entry:562 %v1 = load <256 x i1>, ptr %vpp, align 32563 %v2 = load <16 x i8>, ptr %vcp, align 32564 %call = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvbf16gerx2(<256 x i1> %v1, <16 x i8> %v2, i32 33, i32 5, i32 2)565 store <1024 x i1> %call, ptr %resp, align 64566 ret void567}568 569declare <1024 x i1> @llvm.ppc.mma.pmdmxvbf16gerx2pp(<1024 x i1>, <256 x i1>, <16 x i8>, i32, i32, i32)570 571define void @test_pmdmxvbf16gerx2pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {572; CHECK-LABEL: test_pmdmxvbf16gerx2pp:573; CHECK: # %bb.0: # %entry574; CHECK-NEXT: lxvp vsp34, 0(r3)575; CHECK-NEXT: lxvp vsp36, 32(r3)576; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1577; CHECK-NEXT: lxvp vsp34, 64(r3)578; CHECK-NEXT: lxvp vsp36, 96(r3)579; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0580; CHECK-NEXT: lxv v2, 16(r4)581; CHECK-NEXT: lxv vs0, 0(r5)582; CHECK-NEXT: lxv v3, 0(r4)583; CHECK-NEXT: pmdmxvbf16gerx2pp dmr0, vsp34, vs0, 33, 5, 2584; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0585; CHECK-NEXT: stxvp vsp34, 96(r6)586; CHECK-NEXT: stxvp vsp36, 64(r6)587; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1588; CHECK-NEXT: stxvp vsp34, 32(r6)589; CHECK-NEXT: stxvp vsp36, 0(r6)590; CHECK-NEXT: blr591;592; CHECK-BE-LABEL: test_pmdmxvbf16gerx2pp:593; CHECK-BE: # %bb.0: # %entry594; CHECK-BE-NEXT: lxvp vsp34, 96(r3)595; CHECK-BE-NEXT: lxvp vsp36, 64(r3)596; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1597; CHECK-BE-NEXT: lxvp vsp34, 32(r3)598; CHECK-BE-NEXT: lxvp vsp36, 0(r3)599; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0600; CHECK-BE-NEXT: lxv v2, 0(r4)601; CHECK-BE-NEXT: lxv vs0, 0(r5)602; CHECK-BE-NEXT: lxv v3, 16(r4)603; CHECK-BE-NEXT: pmdmxvbf16gerx2pp dmr0, vsp34, vs0, 33, 5, 2604; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1605; CHECK-BE-NEXT: stxvp vsp36, 96(r6)606; CHECK-BE-NEXT: stxvp vsp34, 64(r6)607; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0608; CHECK-BE-NEXT: stxvp vsp36, 32(r6)609; CHECK-BE-NEXT: stxvp vsp34, 0(r6)610; CHECK-BE-NEXT: blr611entry:612 %v.dmr = load <1024 x i1>, ptr %vop, align 64613 %v1 = load <256 x i1>, ptr %vpp, align 32614 %v2 = load <16 x i8>, ptr %vcp, align 32615 %call = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvbf16gerx2pp(<1024 x i1> %v.dmr, <256 x i1> %v1, <16 x i8> %v2, i32 33, i32 5, i32 2)616 store <1024 x i1> %call, ptr %resp, align 64617 ret void618}619 620declare <1024 x i1> @llvm.ppc.mma.pmdmxvbf16gerx2pn(<1024 x i1>, <256 x i1>, <16 x i8>, i32, i32, i32)621 622define void @test_pmdmxvbf16gerx2pn(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {623; CHECK-LABEL: test_pmdmxvbf16gerx2pn:624; CHECK: # %bb.0: # %entry625; CHECK-NEXT: lxvp vsp34, 0(r3)626; CHECK-NEXT: lxvp vsp36, 32(r3)627; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1628; CHECK-NEXT: lxvp vsp34, 64(r3)629; CHECK-NEXT: lxvp vsp36, 96(r3)630; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0631; CHECK-NEXT: lxv v2, 16(r4)632; CHECK-NEXT: lxv vs0, 0(r5)633; CHECK-NEXT: lxv v3, 0(r4)634; CHECK-NEXT: pmdmxvbf16gerx2pn dmr0, vsp34, vs0, 33, 5, 2635; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0636; CHECK-NEXT: stxvp vsp34, 96(r6)637; CHECK-NEXT: stxvp vsp36, 64(r6)638; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1639; CHECK-NEXT: stxvp vsp34, 32(r6)640; CHECK-NEXT: stxvp vsp36, 0(r6)641; CHECK-NEXT: blr642;643; CHECK-BE-LABEL: test_pmdmxvbf16gerx2pn:644; CHECK-BE: # %bb.0: # %entry645; CHECK-BE-NEXT: lxvp vsp34, 96(r3)646; CHECK-BE-NEXT: lxvp vsp36, 64(r3)647; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1648; CHECK-BE-NEXT: lxvp vsp34, 32(r3)649; CHECK-BE-NEXT: lxvp vsp36, 0(r3)650; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0651; CHECK-BE-NEXT: lxv v2, 0(r4)652; CHECK-BE-NEXT: lxv vs0, 0(r5)653; CHECK-BE-NEXT: lxv v3, 16(r4)654; CHECK-BE-NEXT: pmdmxvbf16gerx2pn dmr0, vsp34, vs0, 33, 5, 2655; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1656; CHECK-BE-NEXT: stxvp vsp36, 96(r6)657; CHECK-BE-NEXT: stxvp vsp34, 64(r6)658; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0659; CHECK-BE-NEXT: stxvp vsp36, 32(r6)660; CHECK-BE-NEXT: stxvp vsp34, 0(r6)661; CHECK-BE-NEXT: blr662entry:663 %v.dmr = load <1024 x i1>, ptr %vop, align 64664 %v1 = load <256 x i1>, ptr %vpp, align 32665 %v2 = load <16 x i8>, ptr %vcp, align 32666 %call = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvbf16gerx2pn(<1024 x i1> %v.dmr, <256 x i1> %v1, <16 x i8> %v2, i32 33, i32 5, i32 2)667 store <1024 x i1> %call, ptr %resp, align 64668 ret void669}670 671declare <1024 x i1> @llvm.ppc.mma.pmdmxvbf16gerx2np(<1024 x i1>, <256 x i1>, <16 x i8>, i32, i32, i32)672 673define void @test_pmdmxvbf16gerx2np(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {674; CHECK-LABEL: test_pmdmxvbf16gerx2np:675; CHECK: # %bb.0: # %entry676; CHECK-NEXT: lxvp vsp34, 0(r3)677; CHECK-NEXT: lxvp vsp36, 32(r3)678; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1679; CHECK-NEXT: lxvp vsp34, 64(r3)680; CHECK-NEXT: lxvp vsp36, 96(r3)681; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0682; CHECK-NEXT: lxv v2, 16(r4)683; CHECK-NEXT: lxv vs0, 0(r5)684; CHECK-NEXT: lxv v3, 0(r4)685; CHECK-NEXT: pmdmxvbf16gerx2np dmr0, vsp34, vs0, 33, 5, 2686; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0687; CHECK-NEXT: stxvp vsp34, 96(r6)688; CHECK-NEXT: stxvp vsp36, 64(r6)689; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1690; CHECK-NEXT: stxvp vsp34, 32(r6)691; CHECK-NEXT: stxvp vsp36, 0(r6)692; CHECK-NEXT: blr693;694; CHECK-BE-LABEL: test_pmdmxvbf16gerx2np:695; CHECK-BE: # %bb.0: # %entry696; CHECK-BE-NEXT: lxvp vsp34, 96(r3)697; CHECK-BE-NEXT: lxvp vsp36, 64(r3)698; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1699; CHECK-BE-NEXT: lxvp vsp34, 32(r3)700; CHECK-BE-NEXT: lxvp vsp36, 0(r3)701; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0702; CHECK-BE-NEXT: lxv v2, 0(r4)703; CHECK-BE-NEXT: lxv vs0, 0(r5)704; CHECK-BE-NEXT: lxv v3, 16(r4)705; CHECK-BE-NEXT: pmdmxvbf16gerx2np dmr0, vsp34, vs0, 33, 5, 2706; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1707; CHECK-BE-NEXT: stxvp vsp36, 96(r6)708; CHECK-BE-NEXT: stxvp vsp34, 64(r6)709; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0710; CHECK-BE-NEXT: stxvp vsp36, 32(r6)711; CHECK-BE-NEXT: stxvp vsp34, 0(r6)712; CHECK-BE-NEXT: blr713entry:714 %v.dmr = load <1024 x i1>, ptr %vop, align 64715 %v1 = load <256 x i1>, ptr %vpp, align 32716 %v2 = load <16 x i8>, ptr %vcp, align 32717 %call = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvbf16gerx2np(<1024 x i1> %v.dmr, <256 x i1> %v1, <16 x i8> %v2, i32 33, i32 5, i32 2)718 store <1024 x i1> %call, ptr %resp, align 64719 ret void720}721 722declare <1024 x i1> @llvm.ppc.mma.pmdmxvbf16gerx2nn(<1024 x i1>, <256 x i1>, <16 x i8>, i32, i32, i32)723 724define void @test_pmdmxvbf16gerx2nn(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {725; CHECK-LABEL: test_pmdmxvbf16gerx2nn:726; CHECK: # %bb.0: # %entry727; CHECK-NEXT: lxvp vsp34, 0(r3)728; CHECK-NEXT: lxvp vsp36, 32(r3)729; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1730; CHECK-NEXT: lxvp vsp34, 64(r3)731; CHECK-NEXT: lxvp vsp36, 96(r3)732; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0733; CHECK-NEXT: lxv v2, 16(r4)734; CHECK-NEXT: lxv vs0, 0(r5)735; CHECK-NEXT: lxv v3, 0(r4)736; CHECK-NEXT: pmdmxvbf16gerx2nn dmr0, vsp34, vs0, 33, 5, 2737; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0738; CHECK-NEXT: stxvp vsp34, 96(r6)739; CHECK-NEXT: stxvp vsp36, 64(r6)740; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1741; CHECK-NEXT: stxvp vsp34, 32(r6)742; CHECK-NEXT: stxvp vsp36, 0(r6)743; CHECK-NEXT: blr744;745; CHECK-BE-LABEL: test_pmdmxvbf16gerx2nn:746; CHECK-BE: # %bb.0: # %entry747; CHECK-BE-NEXT: lxvp vsp34, 96(r3)748; CHECK-BE-NEXT: lxvp vsp36, 64(r3)749; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1750; CHECK-BE-NEXT: lxvp vsp34, 32(r3)751; CHECK-BE-NEXT: lxvp vsp36, 0(r3)752; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0753; CHECK-BE-NEXT: lxv v2, 0(r4)754; CHECK-BE-NEXT: lxv vs0, 0(r5)755; CHECK-BE-NEXT: lxv v3, 16(r4)756; CHECK-BE-NEXT: pmdmxvbf16gerx2nn dmr0, vsp34, vs0, 33, 5, 2757; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1758; CHECK-BE-NEXT: stxvp vsp36, 96(r6)759; CHECK-BE-NEXT: stxvp vsp34, 64(r6)760; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0761; CHECK-BE-NEXT: stxvp vsp36, 32(r6)762; CHECK-BE-NEXT: stxvp vsp34, 0(r6)763; CHECK-BE-NEXT: blr764entry:765 %v.dmr = load <1024 x i1>, ptr %vop, align 64766 %v1 = load <256 x i1>, ptr %vpp, align 32767 %v2 = load <16 x i8>, ptr %vcp, align 32768 %call = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvbf16gerx2nn(<1024 x i1> %v.dmr, <256 x i1> %v1, <16 x i8> %v2, i32 33, i32 5, i32 2)769 store <1024 x i1> %call, ptr %resp, align 64770 ret void771}772 773declare <1024 x i1> @llvm.ppc.mma.dmxvf16gerx2(<256 x i1>, <16 x i8>)774define void @test_dmxvf16gerx2(ptr %vpp, ptr %vcp, ptr %resp) {775; CHECK-LABEL: test_dmxvf16gerx2:776; CHECK: # %bb.0: # %entry777; CHECK-NEXT: lxv v2, 16(r3)778; CHECK-NEXT: lxv vs0, 0(r4)779; CHECK-NEXT: lxv v3, 0(r3)780; CHECK-NEXT: dmxvf16gerx2 dmr0, vsp34, vs0781; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0782; CHECK-NEXT: stxvp vsp34, 96(r5)783; CHECK-NEXT: stxvp vsp36, 64(r5)784; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1785; CHECK-NEXT: stxvp vsp34, 32(r5)786; CHECK-NEXT: stxvp vsp36, 0(r5)787; CHECK-NEXT: blr788;789; CHECK-BE-LABEL: test_dmxvf16gerx2:790; CHECK-BE: # %bb.0: # %entry791; CHECK-BE-NEXT: lxv v2, 0(r3)792; CHECK-BE-NEXT: lxv vs0, 0(r4)793; CHECK-BE-NEXT: lxv v3, 16(r3)794; CHECK-BE-NEXT: dmxvf16gerx2 dmr0, vsp34, vs0795; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1796; CHECK-BE-NEXT: stxvp vsp36, 96(r5)797; CHECK-BE-NEXT: stxvp vsp34, 64(r5)798; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0799; CHECK-BE-NEXT: stxvp vsp36, 32(r5)800; CHECK-BE-NEXT: stxvp vsp34, 0(r5)801; CHECK-BE-NEXT: blr802entry:803 %v1 = load <256 x i1>, ptr %vpp, align 32804 %v2 = load <16 x i8>, ptr %vcp, align 32805 %call = tail call <1024 x i1> @llvm.ppc.mma.dmxvf16gerx2(<256 x i1> %v1, <16 x i8> %v2)806 store <1024 x i1> %call, ptr %resp, align 64807 ret void808}809 810declare <1024 x i1> @llvm.ppc.mma.dmxvf16gerx2pp(<1024 x i1>, <256 x i1>, <16 x i8>)811 812define void @test_dmxvf16gerx2pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {813; CHECK-LABEL: test_dmxvf16gerx2pp:814; CHECK: # %bb.0: # %entry815; CHECK-NEXT: lxvp vsp34, 0(r3)816; CHECK-NEXT: lxvp vsp36, 32(r3)817; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1818; CHECK-NEXT: lxvp vsp34, 64(r3)819; CHECK-NEXT: lxvp vsp36, 96(r3)820; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0821; CHECK-NEXT: lxv v2, 16(r4)822; CHECK-NEXT: lxv vs0, 0(r5)823; CHECK-NEXT: lxv v3, 0(r4)824; CHECK-NEXT: dmxvf16gerx2pp dmr0, vsp34, vs0825; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0826; CHECK-NEXT: stxvp vsp34, 96(r6)827; CHECK-NEXT: stxvp vsp36, 64(r6)828; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1829; CHECK-NEXT: stxvp vsp34, 32(r6)830; CHECK-NEXT: stxvp vsp36, 0(r6)831; CHECK-NEXT: blr832;833; CHECK-BE-LABEL: test_dmxvf16gerx2pp:834; CHECK-BE: # %bb.0: # %entry835; CHECK-BE-NEXT: lxvp vsp34, 96(r3)836; CHECK-BE-NEXT: lxvp vsp36, 64(r3)837; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1838; CHECK-BE-NEXT: lxvp vsp34, 32(r3)839; CHECK-BE-NEXT: lxvp vsp36, 0(r3)840; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0841; CHECK-BE-NEXT: lxv v2, 0(r4)842; CHECK-BE-NEXT: lxv vs0, 0(r5)843; CHECK-BE-NEXT: lxv v3, 16(r4)844; CHECK-BE-NEXT: dmxvf16gerx2pp dmr0, vsp34, vs0845; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1846; CHECK-BE-NEXT: stxvp vsp36, 96(r6)847; CHECK-BE-NEXT: stxvp vsp34, 64(r6)848; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0849; CHECK-BE-NEXT: stxvp vsp36, 32(r6)850; CHECK-BE-NEXT: stxvp vsp34, 0(r6)851; CHECK-BE-NEXT: blr852entry:853 %v.dmr = load <1024 x i1>, ptr %vop, align 64854 %v1 = load <256 x i1>, ptr %vpp, align 32855 %v2 = load <16 x i8>, ptr %vcp, align 32856 %call = tail call <1024 x i1> @llvm.ppc.mma.dmxvf16gerx2pp(<1024 x i1> %v.dmr, <256 x i1> %v1, <16 x i8> %v2)857 store <1024 x i1> %call, ptr %resp, align 64858 ret void859}860 861declare <1024 x i1> @llvm.ppc.mma.dmxvf16gerx2pn(<1024 x i1>, <256 x i1>, <16 x i8>)862 863define void @test_dmxvf16gerx2pn(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {864; CHECK-LABEL: test_dmxvf16gerx2pn:865; CHECK: # %bb.0: # %entry866; CHECK-NEXT: lxvp vsp34, 0(r3)867; CHECK-NEXT: lxvp vsp36, 32(r3)868; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1869; CHECK-NEXT: lxvp vsp34, 64(r3)870; CHECK-NEXT: lxvp vsp36, 96(r3)871; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0872; CHECK-NEXT: lxv v2, 16(r4)873; CHECK-NEXT: lxv vs0, 0(r5)874; CHECK-NEXT: lxv v3, 0(r4)875; CHECK-NEXT: dmxvf16gerx2pn dmr0, vsp34, vs0876; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0877; CHECK-NEXT: stxvp vsp34, 96(r6)878; CHECK-NEXT: stxvp vsp36, 64(r6)879; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1880; CHECK-NEXT: stxvp vsp34, 32(r6)881; CHECK-NEXT: stxvp vsp36, 0(r6)882; CHECK-NEXT: blr883;884; CHECK-BE-LABEL: test_dmxvf16gerx2pn:885; CHECK-BE: # %bb.0: # %entry886; CHECK-BE-NEXT: lxvp vsp34, 96(r3)887; CHECK-BE-NEXT: lxvp vsp36, 64(r3)888; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1889; CHECK-BE-NEXT: lxvp vsp34, 32(r3)890; CHECK-BE-NEXT: lxvp vsp36, 0(r3)891; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0892; CHECK-BE-NEXT: lxv v2, 0(r4)893; CHECK-BE-NEXT: lxv vs0, 0(r5)894; CHECK-BE-NEXT: lxv v3, 16(r4)895; CHECK-BE-NEXT: dmxvf16gerx2pn dmr0, vsp34, vs0896; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1897; CHECK-BE-NEXT: stxvp vsp36, 96(r6)898; CHECK-BE-NEXT: stxvp vsp34, 64(r6)899; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0900; CHECK-BE-NEXT: stxvp vsp36, 32(r6)901; CHECK-BE-NEXT: stxvp vsp34, 0(r6)902; CHECK-BE-NEXT: blr903entry:904 %v.dmr = load <1024 x i1>, ptr %vop, align 64905 %v1 = load <256 x i1>, ptr %vpp, align 32906 %v2 = load <16 x i8>, ptr %vcp, align 32907 %call = tail call <1024 x i1> @llvm.ppc.mma.dmxvf16gerx2pn(<1024 x i1> %v.dmr, <256 x i1> %v1, <16 x i8> %v2)908 store <1024 x i1> %call, ptr %resp, align 64909 ret void910}911 912declare <1024 x i1> @llvm.ppc.mma.dmxvf16gerx2np(<1024 x i1>, <256 x i1>, <16 x i8>)913 914define void @test_dmxvf16gerx2np(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {915; CHECK-LABEL: test_dmxvf16gerx2np:916; CHECK: # %bb.0: # %entry917; CHECK-NEXT: lxvp vsp34, 0(r3)918; CHECK-NEXT: lxvp vsp36, 32(r3)919; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1920; CHECK-NEXT: lxvp vsp34, 64(r3)921; CHECK-NEXT: lxvp vsp36, 96(r3)922; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0923; CHECK-NEXT: lxv v2, 16(r4)924; CHECK-NEXT: lxv vs0, 0(r5)925; CHECK-NEXT: lxv v3, 0(r4)926; CHECK-NEXT: dmxvf16gerx2np dmr0, vsp34, vs0927; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0928; CHECK-NEXT: stxvp vsp34, 96(r6)929; CHECK-NEXT: stxvp vsp36, 64(r6)930; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1931; CHECK-NEXT: stxvp vsp34, 32(r6)932; CHECK-NEXT: stxvp vsp36, 0(r6)933; CHECK-NEXT: blr934;935; CHECK-BE-LABEL: test_dmxvf16gerx2np:936; CHECK-BE: # %bb.0: # %entry937; CHECK-BE-NEXT: lxvp vsp34, 96(r3)938; CHECK-BE-NEXT: lxvp vsp36, 64(r3)939; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1940; CHECK-BE-NEXT: lxvp vsp34, 32(r3)941; CHECK-BE-NEXT: lxvp vsp36, 0(r3)942; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0943; CHECK-BE-NEXT: lxv v2, 0(r4)944; CHECK-BE-NEXT: lxv vs0, 0(r5)945; CHECK-BE-NEXT: lxv v3, 16(r4)946; CHECK-BE-NEXT: dmxvf16gerx2np dmr0, vsp34, vs0947; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1948; CHECK-BE-NEXT: stxvp vsp36, 96(r6)949; CHECK-BE-NEXT: stxvp vsp34, 64(r6)950; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0951; CHECK-BE-NEXT: stxvp vsp36, 32(r6)952; CHECK-BE-NEXT: stxvp vsp34, 0(r6)953; CHECK-BE-NEXT: blr954entry:955 %v.dmr = load <1024 x i1>, ptr %vop, align 64956 %v1 = load <256 x i1>, ptr %vpp, align 32957 %v2 = load <16 x i8>, ptr %vcp, align 32958 %call = tail call <1024 x i1> @llvm.ppc.mma.dmxvf16gerx2np(<1024 x i1> %v.dmr, <256 x i1> %v1, <16 x i8> %v2)959 store <1024 x i1> %call, ptr %resp, align 64960 ret void961}962 963declare <1024 x i1> @llvm.ppc.mma.dmxvf16gerx2nn(<1024 x i1>, <256 x i1>, <16 x i8>)964 965define void @test_dmxvf16gerx2nn(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {966; CHECK-LABEL: test_dmxvf16gerx2nn:967; CHECK: # %bb.0: # %entry968; CHECK-NEXT: lxvp vsp34, 0(r3)969; CHECK-NEXT: lxvp vsp36, 32(r3)970; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1971; CHECK-NEXT: lxvp vsp34, 64(r3)972; CHECK-NEXT: lxvp vsp36, 96(r3)973; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0974; CHECK-NEXT: lxv v2, 16(r4)975; CHECK-NEXT: lxv vs0, 0(r5)976; CHECK-NEXT: lxv v3, 0(r4)977; CHECK-NEXT: dmxvf16gerx2nn dmr0, vsp34, vs0978; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0979; CHECK-NEXT: stxvp vsp34, 96(r6)980; CHECK-NEXT: stxvp vsp36, 64(r6)981; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1982; CHECK-NEXT: stxvp vsp34, 32(r6)983; CHECK-NEXT: stxvp vsp36, 0(r6)984; CHECK-NEXT: blr985;986; CHECK-BE-LABEL: test_dmxvf16gerx2nn:987; CHECK-BE: # %bb.0: # %entry988; CHECK-BE-NEXT: lxvp vsp34, 96(r3)989; CHECK-BE-NEXT: lxvp vsp36, 64(r3)990; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1991; CHECK-BE-NEXT: lxvp vsp34, 32(r3)992; CHECK-BE-NEXT: lxvp vsp36, 0(r3)993; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0994; CHECK-BE-NEXT: lxv v2, 0(r4)995; CHECK-BE-NEXT: lxv vs0, 0(r5)996; CHECK-BE-NEXT: lxv v3, 16(r4)997; CHECK-BE-NEXT: dmxvf16gerx2nn dmr0, vsp34, vs0998; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1999; CHECK-BE-NEXT: stxvp vsp36, 96(r6)1000; CHECK-BE-NEXT: stxvp vsp34, 64(r6)1001; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 01002; CHECK-BE-NEXT: stxvp vsp36, 32(r6)1003; CHECK-BE-NEXT: stxvp vsp34, 0(r6)1004; CHECK-BE-NEXT: blr1005entry:1006 %v.dmr = load <1024 x i1>, ptr %vop, align 641007 %v1 = load <256 x i1>, ptr %vpp, align 321008 %v2 = load <16 x i8>, ptr %vcp, align 321009 %call = tail call <1024 x i1> @llvm.ppc.mma.dmxvf16gerx2nn(<1024 x i1> %v.dmr, <256 x i1> %v1, <16 x i8> %v2)1010 store <1024 x i1> %call, ptr %resp, align 641011 ret void1012}1013 1014declare <1024 x i1> @llvm.ppc.mma.pmdmxvf16gerx2(<256 x i1>, <16 x i8>, i32, i32, i32)1015 1016define void @test_pmdmxvf16gerx2(ptr %vpp, ptr %vcp, ptr %resp) {1017; CHECK-LABEL: test_pmdmxvf16gerx2:1018; CHECK: # %bb.0: # %entry1019; CHECK-NEXT: lxv v2, 16(r3)1020; CHECK-NEXT: lxv vs0, 0(r4)1021; CHECK-NEXT: lxv v3, 0(r3)1022; CHECK-NEXT: pmdmxvf16gerx2 dmr0, vsp34, vs0, 33, 5, 21023; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 01024; CHECK-NEXT: stxvp vsp34, 96(r5)1025; CHECK-NEXT: stxvp vsp36, 64(r5)1026; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 11027; CHECK-NEXT: stxvp vsp34, 32(r5)1028; CHECK-NEXT: stxvp vsp36, 0(r5)1029; CHECK-NEXT: blr1030;1031; CHECK-BE-LABEL: test_pmdmxvf16gerx2:1032; CHECK-BE: # %bb.0: # %entry1033; CHECK-BE-NEXT: lxv v2, 0(r3)1034; CHECK-BE-NEXT: lxv vs0, 0(r4)1035; CHECK-BE-NEXT: lxv v3, 16(r3)1036; CHECK-BE-NEXT: pmdmxvf16gerx2 dmr0, vsp34, vs0, 33, 5, 21037; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 11038; CHECK-BE-NEXT: stxvp vsp36, 96(r5)1039; CHECK-BE-NEXT: stxvp vsp34, 64(r5)1040; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 01041; CHECK-BE-NEXT: stxvp vsp36, 32(r5)1042; CHECK-BE-NEXT: stxvp vsp34, 0(r5)1043; CHECK-BE-NEXT: blr1044entry:1045 %v1 = load <256 x i1>, ptr %vpp, align 321046 %v2 = load <16 x i8>, ptr %vcp, align 321047 %call = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvf16gerx2(<256 x i1> %v1, <16 x i8> %v2, i32 33, i32 5, i32 2)1048 store <1024 x i1> %call, ptr %resp, align 641049 ret void1050}1051 1052declare <1024 x i1> @llvm.ppc.mma.pmdmxvf16gerx2pp(<1024 x i1>, <256 x i1>, <16 x i8>, i32, i32, i32)1053 1054define void @test_pmdmxvf16gerx2pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {1055; CHECK-LABEL: test_pmdmxvf16gerx2pp:1056; CHECK: # %bb.0: # %entry1057; CHECK-NEXT: lxvp vsp34, 0(r3)1058; CHECK-NEXT: lxvp vsp36, 32(r3)1059; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 11060; CHECK-NEXT: lxvp vsp34, 64(r3)1061; CHECK-NEXT: lxvp vsp36, 96(r3)1062; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 01063; CHECK-NEXT: lxv v2, 16(r4)1064; CHECK-NEXT: lxv vs0, 0(r5)1065; CHECK-NEXT: lxv v3, 0(r4)1066; CHECK-NEXT: pmdmxvf16gerx2pp dmr0, vsp34, vs0, 33, 5, 21067; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 01068; CHECK-NEXT: stxvp vsp34, 96(r6)1069; CHECK-NEXT: stxvp vsp36, 64(r6)1070; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 11071; CHECK-NEXT: stxvp vsp34, 32(r6)1072; CHECK-NEXT: stxvp vsp36, 0(r6)1073; CHECK-NEXT: blr1074;1075; CHECK-BE-LABEL: test_pmdmxvf16gerx2pp:1076; CHECK-BE: # %bb.0: # %entry1077; CHECK-BE-NEXT: lxvp vsp34, 96(r3)1078; CHECK-BE-NEXT: lxvp vsp36, 64(r3)1079; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 11080; CHECK-BE-NEXT: lxvp vsp34, 32(r3)1081; CHECK-BE-NEXT: lxvp vsp36, 0(r3)1082; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 01083; CHECK-BE-NEXT: lxv v2, 0(r4)1084; CHECK-BE-NEXT: lxv vs0, 0(r5)1085; CHECK-BE-NEXT: lxv v3, 16(r4)1086; CHECK-BE-NEXT: pmdmxvf16gerx2pp dmr0, vsp34, vs0, 33, 5, 21087; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 11088; CHECK-BE-NEXT: stxvp vsp36, 96(r6)1089; CHECK-BE-NEXT: stxvp vsp34, 64(r6)1090; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 01091; CHECK-BE-NEXT: stxvp vsp36, 32(r6)1092; CHECK-BE-NEXT: stxvp vsp34, 0(r6)1093; CHECK-BE-NEXT: blr1094entry:1095 %v.dmr = load <1024 x i1>, ptr %vop, align 641096 %v1 = load <256 x i1>, ptr %vpp, align 321097 %v2 = load <16 x i8>, ptr %vcp, align 321098 %call = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvf16gerx2pp(<1024 x i1> %v.dmr, <256 x i1> %v1, <16 x i8> %v2, i32 33, i32 5, i32 2)1099 store <1024 x i1> %call, ptr %resp, align 641100 ret void1101}1102 1103declare <1024 x i1> @llvm.ppc.mma.pmdmxvf16gerx2pn(<1024 x i1>, <256 x i1>, <16 x i8>, i32, i32, i32)1104 1105define void @test_pmdmxvf16gerx2pn(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {1106; CHECK-LABEL: test_pmdmxvf16gerx2pn:1107; CHECK: # %bb.0: # %entry1108; CHECK-NEXT: lxvp vsp34, 0(r3)1109; CHECK-NEXT: lxvp vsp36, 32(r3)1110; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 11111; CHECK-NEXT: lxvp vsp34, 64(r3)1112; CHECK-NEXT: lxvp vsp36, 96(r3)1113; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 01114; CHECK-NEXT: lxv v2, 16(r4)1115; CHECK-NEXT: lxv vs0, 0(r5)1116; CHECK-NEXT: lxv v3, 0(r4)1117; CHECK-NEXT: pmdmxvf16gerx2pn dmr0, vsp34, vs0, 33, 5, 21118; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 01119; CHECK-NEXT: stxvp vsp34, 96(r6)1120; CHECK-NEXT: stxvp vsp36, 64(r6)1121; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 11122; CHECK-NEXT: stxvp vsp34, 32(r6)1123; CHECK-NEXT: stxvp vsp36, 0(r6)1124; CHECK-NEXT: blr1125;1126; CHECK-BE-LABEL: test_pmdmxvf16gerx2pn:1127; CHECK-BE: # %bb.0: # %entry1128; CHECK-BE-NEXT: lxvp vsp34, 96(r3)1129; CHECK-BE-NEXT: lxvp vsp36, 64(r3)1130; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 11131; CHECK-BE-NEXT: lxvp vsp34, 32(r3)1132; CHECK-BE-NEXT: lxvp vsp36, 0(r3)1133; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 01134; CHECK-BE-NEXT: lxv v2, 0(r4)1135; CHECK-BE-NEXT: lxv vs0, 0(r5)1136; CHECK-BE-NEXT: lxv v3, 16(r4)1137; CHECK-BE-NEXT: pmdmxvf16gerx2pn dmr0, vsp34, vs0, 33, 5, 21138; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 11139; CHECK-BE-NEXT: stxvp vsp36, 96(r6)1140; CHECK-BE-NEXT: stxvp vsp34, 64(r6)1141; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 01142; CHECK-BE-NEXT: stxvp vsp36, 32(r6)1143; CHECK-BE-NEXT: stxvp vsp34, 0(r6)1144; CHECK-BE-NEXT: blr1145entry:1146 %v.dmr = load <1024 x i1>, ptr %vop, align 641147 %v1 = load <256 x i1>, ptr %vpp, align 321148 %v2 = load <16 x i8>, ptr %vcp, align 321149 %call = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvf16gerx2pn(<1024 x i1> %v.dmr, <256 x i1> %v1, <16 x i8> %v2, i32 33, i32 5, i32 2)1150 store <1024 x i1> %call, ptr %resp, align 641151 ret void1152}1153 1154declare <1024 x i1> @llvm.ppc.mma.pmdmxvf16gerx2np(<1024 x i1>, <256 x i1>, <16 x i8>, i32, i32, i32)1155 1156define void @test_pmdmxvf16gerx2np(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {1157; CHECK-LABEL: test_pmdmxvf16gerx2np:1158; CHECK: # %bb.0: # %entry1159; CHECK-NEXT: lxvp vsp34, 0(r3)1160; CHECK-NEXT: lxvp vsp36, 32(r3)1161; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 11162; CHECK-NEXT: lxvp vsp34, 64(r3)1163; CHECK-NEXT: lxvp vsp36, 96(r3)1164; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 01165; CHECK-NEXT: lxv v2, 16(r4)1166; CHECK-NEXT: lxv vs0, 0(r5)1167; CHECK-NEXT: lxv v3, 0(r4)1168; CHECK-NEXT: pmdmxvf16gerx2np dmr0, vsp34, vs0, 33, 5, 21169; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 01170; CHECK-NEXT: stxvp vsp34, 96(r6)1171; CHECK-NEXT: stxvp vsp36, 64(r6)1172; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 11173; CHECK-NEXT: stxvp vsp34, 32(r6)1174; CHECK-NEXT: stxvp vsp36, 0(r6)1175; CHECK-NEXT: blr1176;1177; CHECK-BE-LABEL: test_pmdmxvf16gerx2np:1178; CHECK-BE: # %bb.0: # %entry1179; CHECK-BE-NEXT: lxvp vsp34, 96(r3)1180; CHECK-BE-NEXT: lxvp vsp36, 64(r3)1181; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 11182; CHECK-BE-NEXT: lxvp vsp34, 32(r3)1183; CHECK-BE-NEXT: lxvp vsp36, 0(r3)1184; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 01185; CHECK-BE-NEXT: lxv v2, 0(r4)1186; CHECK-BE-NEXT: lxv vs0, 0(r5)1187; CHECK-BE-NEXT: lxv v3, 16(r4)1188; CHECK-BE-NEXT: pmdmxvf16gerx2np dmr0, vsp34, vs0, 33, 5, 21189; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 11190; CHECK-BE-NEXT: stxvp vsp36, 96(r6)1191; CHECK-BE-NEXT: stxvp vsp34, 64(r6)1192; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 01193; CHECK-BE-NEXT: stxvp vsp36, 32(r6)1194; CHECK-BE-NEXT: stxvp vsp34, 0(r6)1195; CHECK-BE-NEXT: blr1196entry:1197 %v.dmr = load <1024 x i1>, ptr %vop, align 641198 %v1 = load <256 x i1>, ptr %vpp, align 321199 %v2 = load <16 x i8>, ptr %vcp, align 321200 %call = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvf16gerx2np(<1024 x i1> %v.dmr, <256 x i1> %v1, <16 x i8> %v2, i32 33, i32 5, i32 2)1201 store <1024 x i1> %call, ptr %resp, align 641202 ret void1203}1204 1205declare <1024 x i1> @llvm.ppc.mma.pmdmxvf16gerx2nn(<1024 x i1>, <256 x i1>, <16 x i8>, i32, i32, i32)1206 1207define void @test_pmdmxvf16gerx2nn(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {1208; CHECK-LABEL: test_pmdmxvf16gerx2nn:1209; CHECK: # %bb.0: # %entry1210; CHECK-NEXT: lxvp vsp34, 0(r3)1211; CHECK-NEXT: lxvp vsp36, 32(r3)1212; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 11213; CHECK-NEXT: lxvp vsp34, 64(r3)1214; CHECK-NEXT: lxvp vsp36, 96(r3)1215; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 01216; CHECK-NEXT: lxv v2, 16(r4)1217; CHECK-NEXT: lxv vs0, 0(r5)1218; CHECK-NEXT: lxv v3, 0(r4)1219; CHECK-NEXT: pmdmxvbf16gerx2nn dmr0, vsp34, vs0, 33, 5, 21220; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 01221; CHECK-NEXT: stxvp vsp34, 96(r6)1222; CHECK-NEXT: stxvp vsp36, 64(r6)1223; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 11224; CHECK-NEXT: stxvp vsp34, 32(r6)1225; CHECK-NEXT: stxvp vsp36, 0(r6)1226; CHECK-NEXT: blr1227;1228; CHECK-BE-LABEL: test_pmdmxvf16gerx2nn:1229; CHECK-BE: # %bb.0: # %entry1230; CHECK-BE-NEXT: lxvp vsp34, 96(r3)1231; CHECK-BE-NEXT: lxvp vsp36, 64(r3)1232; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 11233; CHECK-BE-NEXT: lxvp vsp34, 32(r3)1234; CHECK-BE-NEXT: lxvp vsp36, 0(r3)1235; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 01236; CHECK-BE-NEXT: lxv v2, 0(r4)1237; CHECK-BE-NEXT: lxv vs0, 0(r5)1238; CHECK-BE-NEXT: lxv v3, 16(r4)1239; CHECK-BE-NEXT: pmdmxvbf16gerx2nn dmr0, vsp34, vs0, 33, 5, 21240; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 11241; CHECK-BE-NEXT: stxvp vsp36, 96(r6)1242; CHECK-BE-NEXT: stxvp vsp34, 64(r6)1243; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 01244; CHECK-BE-NEXT: stxvp vsp36, 32(r6)1245; CHECK-BE-NEXT: stxvp vsp34, 0(r6)1246; CHECK-BE-NEXT: blr1247entry:1248 %v.dmr = load <1024 x i1>, ptr %vop, align 641249 %v1 = load <256 x i1>, ptr %vpp, align 321250 %v2 = load <16 x i8>, ptr %vcp, align 321251 %call = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvbf16gerx2nn(<1024 x i1> %v.dmr, <256 x i1> %v1, <16 x i8> %v2, i32 33, i32 5, i32 2)1252 store <1024 x i1> %call, ptr %resp, align 641253 ret void1254}1255